arch/blackfin/Kconfig

   1 config SYMBOL_PREFIX
   2         string
   3         default "_"
   4
   5 config MMU
   6         def_bool n
   7
   8 config FPU
   9         def_bool n
  10
  11 config RWSEM_GENERIC_SPINLOCK
  12         def_bool y
  13
  14 config RWSEM_XCHGADD_ALGORITHM
  15         def_bool n
  16
  17 config BLACKFIN
  18         def_bool y
  19         select HAVE_ARCH_KGDB
  20         select HAVE_ARCH_TRACEHOOK
  21         select HAVE_DYNAMIC_FTRACE
  22         select HAVE_FTRACE_MCOUNT_RECORD
  23         select HAVE_FUNCTION_GRAPH_TRACER
  24         select HAVE_FUNCTION_TRACER
  25         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  26         select HAVE_IDE
  27         select HAVE_KERNEL_GZIP if RAMKERNEL
  28         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  29         select HAVE_KERNEL_LZMA if RAMKERNEL
  30         select HAVE_KERNEL_LZO if RAMKERNEL
  31         select HAVE_OPROFILE
  32         select ARCH_WANT_OPTIONAL_GPIOLIB
  33
  34 config GENERIC_CSUM
  35         def_bool y
  36
  37 config GENERIC_BUG
  38         def_bool y
  39         depends on BUG
  40
  41 config ZONE_DMA
  42         def_bool y
  43
  44 config GENERIC_FIND_NEXT_BIT
  45         def_bool y
  46
  47 config GENERIC_HARDIRQS
  48         def_bool y
  49
  50 config GENERIC_IRQ_PROBE
  51         def_bool y
  52
  53 config GENERIC_HARDIRQS_NO__DO_IRQ
  54         def_bool y
  55
  56 config GENERIC_GPIO
  57         def_bool y
  58
  59 config FORCE_MAX_ZONEORDER
  60         int
  61         default "14"
  62
  63 config GENERIC_CALIBRATE_DELAY
  64         def_bool y
  65
  66 config LOCKDEP_SUPPORT
  67         def_bool y
  68
  69 config STACKTRACE_SUPPORT
  70         def_bool y
  71
  72 config TRACE_IRQFLAGS_SUPPORT
  73         def_bool y
  74
  75 source "init/Kconfig"
  76
  77 source "kernel/Kconfig.preempt"
  78
  79 source "kernel/Kconfig.freezer"
  80
  81 menu "Blackfin Processor Options"
  82
  83 comment "Processor and Board Settings"
  84
  85 choice
  86         prompt "CPU"
  87         default BF533
  88
  89 config BF512
  90         bool "BF512"
  91         help
  92           BF512 Processor Support.
  93
  94 config BF514
  95         bool "BF514"
  96         help
  97           BF514 Processor Support.
  98
  99 config BF516
 100         bool "BF516"
 101         help
 102           BF516 Processor Support.
 103
 104 config BF518
 105         bool "BF518"
 106         help
 107           BF518 Processor Support.
 108
 109 config BF522
 110         bool "BF522"
 111         help
 112           BF522 Processor Support.
 113
 114 config BF523
 115         bool "BF523"
 116         help
 117           BF523 Processor Support.
 118
 119 config BF524
 120         bool "BF524"
 121         help
 122           BF524 Processor Support.
 123
 124 config BF525
 125         bool "BF525"
 126         help
 127           BF525 Processor Support.
 128
 129 config BF526
 130         bool "BF526"
 131         help
 132           BF526 Processor Support.
 133
 134 config BF527
 135         bool "BF527"
 136         help
 137           BF527 Processor Support.
 138
 139 config BF531
 140         bool "BF531"
 141         help
 142           BF531 Processor Support.
 143
 144 config BF532
 145         bool "BF532"
 146         help
 147           BF532 Processor Support.
 148
 149 config BF533
 150         bool "BF533"
 151         help
 152           BF533 Processor Support.
 153
 154 config BF534
 155         bool "BF534"
 156         help
 157           BF534 Processor Support.
 158
 159 config BF536
 160         bool "BF536"
 161         help
 162           BF536 Processor Support.
 163
 164 config BF537
 165         bool "BF537"
 166         help
 167           BF537 Processor Support.
 168
 169 config BF538
 170         bool "BF538"
 171         help
 172           BF538 Processor Support.
 173
 174 config BF539
 175         bool "BF539"
 176         help
 177           BF539 Processor Support.
 178
 179 config BF542_std
 180         bool "BF542"
 181         help
 182           BF542 Processor Support.
 183
 184 config BF542M
 185         bool "BF542m"
 186         help
 187           BF542 Processor Support.
 188
 189 config BF544_std
 190         bool "BF544"
 191         help
 192           BF544 Processor Support.
 193
 194 config BF544M
 195         bool "BF544m"
 196         help
 197           BF544 Processor Support.
 198
 199 config BF547_std
 200         bool "BF547"
 201         help
 202           BF547 Processor Support.
 203
 204 config BF547M
 205         bool "BF547m"
 206         help
 207           BF547 Processor Support.
 208
 209 config BF548_std
 210         bool "BF548"
 211         help
 212           BF548 Processor Support.
 213
 214 config BF548M
 215         bool "BF548m"
 216         help
 217           BF548 Processor Support.
 218
 219 config BF549_std
 220         bool "BF549"
 221         help
 222           BF549 Processor Support.
 223
 224 config BF549M
 225         bool "BF549m"
 226         help
 227           BF549 Processor Support.
 228
 229 config BF561
 230         bool "BF561"
 231         help
 232           BF561 Processor Support.
 233
 234 endchoice
 235
 236 config SMP
 237         depends on BF561
 238         select TICKSOURCE_CORETMR
 239         bool "Symmetric multi-processing support"
 240         ---help---
 241           This enables support for systems with more than one CPU,
 242           like the dual core BF561. If you have a system with only one
 243           CPU, say N. If you have a system with more than one CPU, say Y.
 244
 245           If you don't know what to do here, say N.
 246
 247 config NR_CPUS
 248         int
 249         depends on SMP
 250         default 2 if BF561
 251
 252 config HOTPLUG_CPU
 253         bool "Support for hot-pluggable CPUs"
 254         depends on SMP && HOTPLUG
 255         default y
 256
 257 config IRQ_PER_CPU
 258         bool
 259         depends on SMP
 260         default y
 261
 262 config HAVE_LEGACY_PER_CPU_AREA
 263         def_bool y
 264         depends on SMP
 265
 266 config BF_REV_MIN
 267         int
 268         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 269         default 2 if (BF537 || BF536 || BF534)
 270         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 271         default 4 if (BF538 || BF539)
 272
 273 config BF_REV_MAX
 274         int
 275         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 276         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 277         default 5 if (BF561 || BF538 || BF539)
 278         default 6 if (BF533 || BF532 || BF531)
 279
 280 choice
 281         prompt "Silicon Rev"
 282         default BF_REV_0_0 if (BF51x || BF52x)
 283         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 284         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 285
 286 config BF_REV_0_0
 287         bool "0.0"
 288         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 289
 290 config BF_REV_0_1
 291         bool "0.1"
 292         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 293
 294 config BF_REV_0_2
 295         bool "0.2"
 296         depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 297
 298 config BF_REV_0_3
 299         bool "0.3"
 300         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 301
 302 config BF_REV_0_4
 303         bool "0.4"
 304         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 305
 306 config BF_REV_0_5
 307         bool "0.5"
 308         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 309
 310 config BF_REV_0_6
 311         bool "0.6"
 312         depends on (BF533 || BF532 || BF531)
 313
 314 config BF_REV_ANY
 315         bool "any"
 316
 317 config BF_REV_NONE
 318         bool "none"
 319
 320 endchoice
 321
 322 config BF53x
 323         bool
 324         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 325         default y
 326
 327 config MEM_MT48LC64M4A2FB_7E
 328         bool
 329         depends on (BFIN533_STAMP)
 330         default y
 331
 332 config MEM_MT48LC16M16A2TG_75
 333         bool
 334         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 335                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 336                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 337                 || BFIN527_BLUETECHNIX_CM)
 338         default y
 339
 340 config MEM_MT48LC32M8A2_75
 341         bool
 342         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 343         default y
 344
 345 config MEM_MT48LC8M32B2B5_7
 346         bool
 347         depends on (BFIN561_BLUETECHNIX_CM)
 348         default y
 349
 350 config MEM_MT48LC32M16A2TG_75
 351         bool
 352         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
 353         default y
 354
 355 config MEM_MT48H32M16LFCJ_75
 356         bool
 357         depends on (BFIN526_EZBRD)
 358         default y
 359
 360 source "arch/blackfin/mach-bf518/Kconfig"
 361 source "arch/blackfin/mach-bf527/Kconfig"
 362 source "arch/blackfin/mach-bf533/Kconfig"
 363 source "arch/blackfin/mach-bf561/Kconfig"
 364 source "arch/blackfin/mach-bf537/Kconfig"
 365 source "arch/blackfin/mach-bf538/Kconfig"
 366 source "arch/blackfin/mach-bf548/Kconfig"
 367
 368 menu "Board customizations"
 369
 370 config CMDLINE_BOOL
 371         bool "Default bootloader kernel arguments"
 372
 373 config CMDLINE
 374         string "Initial kernel command string"
 375         depends on CMDLINE_BOOL
 376         default "console=ttyBF0,57600"
 377         help
 378           If you don't have a boot loader capable of passing a command line string
 379           to the kernel, you may specify one here. As a minimum, you should specify
 380           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 381
 382 config BOOT_LOAD
 383         hex "Kernel load address for booting"
 384         default "0x1000"
 385         range 0x1000 0x20000000
 386         help
 387           This option allows you to set the load address of the kernel.
 388           This can be useful if you are on a board which has a small amount
 389           of memory or you wish to reserve some memory at the beginning of
 390           the address space.
 391
 392           Note that you need to keep this value above 4k (0x1000) as this
 393           memory region is used to capture NULL pointer references as well
 394           as some core kernel functions.
 395
 396 config ROM_BASE
 397         hex "Kernel ROM Base"
 398         depends on ROMKERNEL
 399         default "0x20040040"
 400         range 0x20000000 0x20400000 if !(BF54x || BF561)
 401         range 0x20000000 0x30000000 if (BF54x || BF561)
 402         help
 403           Make sure your ROM base does not include any file-header
 404           information that is prepended to the kernel.
 405
 406           For example, the bootable U-Boot format (created with
 407           mkimage) has a 64 byte header (0x40).  So while the image
 408           you write to flash might start at say 0x20080000, you have
 409           to add 0x40 to get the kernel's ROM base as it will come
 410           after the header.
 411
 412 comment "Clock/PLL Setup"
 413
 414 config CLKIN_HZ
 415         int "Frequency of the crystal on the board in Hz"
 416         default "10000000" if BFIN532_IP0X
 417         default "11059200" if BFIN533_STAMP
 418         default "24576000" if PNAV10
 419         default "25000000" # most people use this
 420         default "27000000" if BFIN533_EZKIT
 421         default "30000000" if BFIN561_EZKIT
 422         help
 423           The frequency of CLKIN crystal oscillator on the board in Hz.
 424           Warning: This value should match the crystal on the board. Otherwise,
 425           peripherals won't work properly.
 426
 427 config BFIN_KERNEL_CLOCK
 428         bool "Re-program Clocks while Kernel boots?"
 429         default n
 430         help
 431           This option decides if kernel clocks are re-programed from the
 432           bootloader settings. If the clocks are not set, the SDRAM settings
 433           are also not changed, and the Bootloader does 100% of the hardware
 434           configuration.
 435
 436 config PLL_BYPASS
 437         bool "Bypass PLL"
 438         depends on BFIN_KERNEL_CLOCK
 439         default n
 440
 441 config CLKIN_HALF
 442         bool "Half Clock In"
 443         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 444         default n
 445         help
 446           If this is set the clock will be divided by 2, before it goes to the PLL.
 447
 448 config VCO_MULT
 449         int "VCO Multiplier"
 450         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 451         range 1 64
 452         default "22" if BFIN533_EZKIT
 453         default "45" if BFIN533_STAMP
 454         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 455         default "22" if BFIN533_BLUETECHNIX_CM
 456         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 457         default "20" if BFIN561_EZKIT
 458         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 459         help
 460           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 461           PLL Frequency = (Crystal Frequency) * (this setting)
 462
 463 choice
 464         prompt "Core Clock Divider"
 465         depends on BFIN_KERNEL_CLOCK
 466         default CCLK_DIV_1
 467         help
 468           This sets the frequency of the core. It can be 1, 2, 4 or 8
 469           Core Frequency = (PLL frequency) / (this setting)
 470
 471 config CCLK_DIV_1
 472         bool "1"
 473
 474 config CCLK_DIV_2
 475         bool "2"
 476
 477 config CCLK_DIV_4
 478         bool "4"
 479
 480 config CCLK_DIV_8
 481         bool "8"
 482 endchoice
 483
 484 config SCLK_DIV
 485         int "System Clock Divider"
 486         depends on BFIN_KERNEL_CLOCK
 487         range 1 15
 488         default 5
 489         help
 490           This sets the frequency of the system clock (including SDRAM or DDR).
 491           This can be between 1 and 15
 492           System Clock = (PLL frequency) / (this setting)
 493
 494 choice
 495         prompt "DDR SDRAM Chip Type"
 496         depends on BFIN_KERNEL_CLOCK
 497         depends on BF54x
 498         default MEM_MT46V32M16_5B
 499
 500 config MEM_MT46V32M16_6T
 501         bool "MT46V32M16_6T"
 502
 503 config MEM_MT46V32M16_5B
 504         bool "MT46V32M16_5B"
 505 endchoice
 506
 507 choice
 508         prompt "DDR/SDRAM Timing"
 509         depends on BFIN_KERNEL_CLOCK
 510         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 511         help
 512           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 513           The calculated SDRAM timing parameters may not be 100%
 514           accurate - This option is therefore marked experimental.
 515
 516 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 517         bool "Calculate Timings (EXPERIMENTAL)"
 518         depends on EXPERIMENTAL
 519
 520 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 521         bool "Provide accurate Timings based on target SCLK"
 522         help
 523           Please consult the Blackfin Hardware Reference Manuals as well
 524           as the memory device datasheet.
 525           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 526 endchoice
 527
 528 menu "Memory Init Control"
 529         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 530
 531 config MEM_DDRCTL0
 532         depends on BF54x
 533         hex "DDRCTL0"
 534         default 0x0
 535
 536 config MEM_DDRCTL1
 537         depends on BF54x
 538         hex "DDRCTL1"
 539         default 0x0
 540
 541 config MEM_DDRCTL2
 542         depends on BF54x
 543         hex "DDRCTL2"
 544         default 0x0
 545
 546 config MEM_EBIU_DDRQUE
 547         depends on BF54x
 548         hex "DDRQUE"
 549         default 0x0
 550
 551 config MEM_SDRRC
 552         depends on !BF54x
 553         hex "SDRRC"
 554         default 0x0
 555
 556 config MEM_SDGCTL
 557         depends on !BF54x
 558         hex "SDGCTL"
 559         default 0x0
 560 endmenu
 561
 562 #
 563 # Max & Min Speeds for various Chips
 564 #
 565 config MAX_VCO_HZ
 566         int
 567         default 400000000 if BF512
 568         default 400000000 if BF514
 569         default 400000000 if BF516
 570         default 400000000 if BF518
 571         default 400000000 if BF522
 572         default 600000000 if BF523
 573         default 400000000 if BF524
 574         default 600000000 if BF525
 575         default 400000000 if BF526
 576         default 600000000 if BF527
 577         default 400000000 if BF531
 578         default 400000000 if BF532
 579         default 750000000 if BF533
 580         default 500000000 if BF534
 581         default 400000000 if BF536
 582         default 600000000 if BF537
 583         default 533333333 if BF538
 584         default 533333333 if BF539
 585         default 600000000 if BF542
 586         default 533333333 if BF544
 587         default 600000000 if BF547
 588         default 600000000 if BF548
 589         default 533333333 if BF549
 590         default 600000000 if BF561
 591
 592 config MIN_VCO_HZ
 593         int
 594         default 50000000
 595
 596 config MAX_SCLK_HZ
 597         int
 598         default 133333333
 599
 600 config MIN_SCLK_HZ
 601         int
 602         default 27000000
 603
 604 comment "Kernel Timer/Scheduler"
 605
 606 source kernel/Kconfig.hz
 607
 608 config GENERIC_CLOCKEVENTS
 609         bool "Generic clock events"
 610         default y
 611
 612 menu "Clock event device"
 613         depends on GENERIC_CLOCKEVENTS
 614 config TICKSOURCE_GPTMR0
 615         bool "GPTimer0"
 616         depends on !SMP
 617         select BFIN_GPTIMERS
 618
 619 config TICKSOURCE_CORETMR
 620         bool "Core timer"
 621         default y
 622 endmenu
 623
 624 menu "Clock souce"
 625         depends on GENERIC_CLOCKEVENTS
 626 config CYCLES_CLOCKSOURCE
 627         bool "CYCLES"
 628         default y
 629         depends on !BFIN_SCRATCH_REG_CYCLES
 630         depends on !SMP
 631         help
 632           If you say Y here, you will enable support for using the 'cycles'
 633           registers as a clock source.  Doing so means you will be unable to
 634           safely write to the 'cycles' register during runtime.  You will
 635           still be able to read it (such as for performance monitoring), but
 636           writing the registers will most likely crash the kernel.
 637
 638 config GPTMR0_CLOCKSOURCE
 639         bool "GPTimer0"
 640         select BFIN_GPTIMERS
 641         depends on !TICKSOURCE_GPTMR0
 642 endmenu
 643
 644 config ARCH_USES_GETTIMEOFFSET
 645         depends on !GENERIC_CLOCKEVENTS
 646         def_bool y
 647
 648 source kernel/time/Kconfig
 649
 650 comment "Misc"
 651
 652 choice
 653         prompt "Blackfin Exception Scratch Register"
 654         default BFIN_SCRATCH_REG_RETN
 655         help
 656           Select the resource to reserve for the Exception handler:
 657             - RETN: Non-Maskable Interrupt (NMI)
 658             - RETE: Exception Return (JTAG/ICE)
 659             - CYCLES: Performance counter
 660
 661           If you are unsure, please select "RETN".
 662
 663 config BFIN_SCRATCH_REG_RETN
 664         bool "RETN"
 665         help
 666           Use the RETN register in the Blackfin exception handler
 667           as a stack scratch register.  This means you cannot
 668           safely use NMI on the Blackfin while running Linux, but
 669           you can debug the system with a JTAG ICE and use the
 670           CYCLES performance registers.
 671
 672           If you are unsure, please select "RETN".
 673
 674 config BFIN_SCRATCH_REG_RETE
 675         bool "RETE"
 676         help
 677           Use the RETE register in the Blackfin exception handler
 678           as a stack scratch register.  This means you cannot
 679           safely use a JTAG ICE while debugging a Blackfin board,
 680           but you can safely use the CYCLES performance registers
 681           and the NMI.
 682
 683           If you are unsure, please select "RETN".
 684
 685 config BFIN_SCRATCH_REG_CYCLES
 686         bool "CYCLES"
 687         help
 688           Use the CYCLES register in the Blackfin exception handler
 689           as a stack scratch register.  This means you cannot
 690           safely use the CYCLES performance registers on a Blackfin
 691           board at anytime, but you can debug the system with a JTAG
 692           ICE and use the NMI.
 693
 694           If you are unsure, please select "RETN".
 695
 696 endchoice
 697
 698 endmenu
 699
 700
 701 menu "Blackfin Kernel Optimizations"
 702         depends on !SMP
 703
 704 comment "Memory Optimizations"
 705
 706 config I_ENTRY_L1
 707         bool "Locate interrupt entry code in L1 Memory"
 708         default y
 709         help
 710           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 711           into L1 instruction memory. (less latency)
 712
 713 config EXCPT_IRQ_SYSC_L1
 714         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 715         default y
 716         help
 717           If enabled, the entire ASM lowlevel exception and interrupt entry code
 718           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 719           (less latency)
 720
 721 config DO_IRQ_L1
 722         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 723         default y
 724         help
 725           If enabled, the frequently called do_irq dispatcher function is linked
 726           into L1 instruction memory. (less latency)
 727
 728 config CORE_TIMER_IRQ_L1
 729         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 730         default y
 731         help
 732           If enabled, the frequently called timer_interrupt() function is linked
 733           into L1 instruction memory. (less latency)
 734
 735 config IDLE_L1
 736         bool "Locate frequently idle function in L1 Memory"
 737         default y
 738         help
 739           If enabled, the frequently called idle function is linked
 740           into L1 instruction memory. (less latency)
 741
 742 config SCHEDULE_L1
 743         bool "Locate kernel schedule function in L1 Memory"
 744         default y
 745         help
 746           If enabled, the frequently called kernel schedule is linked
 747           into L1 instruction memory. (less latency)
 748
 749 config ARITHMETIC_OPS_L1
 750         bool "Locate kernel owned arithmetic functions in L1 Memory"
 751         default y
 752         help
 753           If enabled, arithmetic functions are linked
 754           into L1 instruction memory. (less latency)
 755
 756 config ACCESS_OK_L1
 757         bool "Locate access_ok function in L1 Memory"
 758         default y
 759         help
 760           If enabled, the access_ok function is linked
 761           into L1 instruction memory. (less latency)
 762
 763 config MEMSET_L1
 764         bool "Locate memset function in L1 Memory"
 765         default y
 766         help
 767           If enabled, the memset function is linked
 768           into L1 instruction memory. (less latency)
 769
 770 config MEMCPY_L1
 771         bool "Locate memcpy function in L1 Memory"
 772         default y
 773         help
 774           If enabled, the memcpy function is linked
 775           into L1 instruction memory. (less latency)
 776
 777 config STRCMP_L1
 778         bool "locate strcmp function in L1 Memory"
 779         default y
 780         help
 781           If enabled, the strcmp function is linked
 782           into L1 instruction memory (less latency).
 783
 784 config STRNCMP_L1
 785         bool "locate strncmp function in L1 Memory"
 786         default y
 787         help
 788           If enabled, the strncmp function is linked
 789           into L1 instruction memory (less latency).
 790
 791 config STRCPY_L1
 792         bool "locate strcpy function in L1 Memory"
 793         default y
 794         help
 795           If enabled, the strcpy function is linked
 796           into L1 instruction memory (less latency).
 797
 798 config STRNCPY_L1
 799         bool "locate strncpy function in L1 Memory"
 800         default y
 801         help
 802           If enabled, the strncpy function is linked
 803           into L1 instruction memory (less latency).
 804
 805 config SYS_BFIN_SPINLOCK_L1
 806         bool "Locate sys_bfin_spinlock function in L1 Memory"
 807         default y
 808         help
 809           If enabled, sys_bfin_spinlock function is linked
 810           into L1 instruction memory. (less latency)
 811
 812 config IP_CHECKSUM_L1
 813         bool "Locate IP Checksum function in L1 Memory"
 814         default n
 815         help
 816           If enabled, the IP Checksum function is linked
 817           into L1 instruction memory. (less latency)
 818
 819 config CACHELINE_ALIGNED_L1
 820         bool "Locate cacheline_aligned data to L1 Data Memory"
 821         default y if !BF54x
 822         default n if BF54x
 823         depends on !BF531
 824         help
 825           If enabled, cacheline_aligned data is linked
 826           into L1 data memory. (less latency)
 827
 828 config SYSCALL_TAB_L1
 829         bool "Locate Syscall Table L1 Data Memory"
 830         default n
 831         depends on !BF531
 832         help
 833           If enabled, the Syscall LUT is linked
 834           into L1 data memory. (less latency)
 835
 836 config CPLB_SWITCH_TAB_L1
 837         bool "Locate CPLB Switch Tables L1 Data Memory"
 838         default n
 839         depends on !BF531
 840         help
 841           If enabled, the CPLB Switch Tables are linked
 842           into L1 data memory. (less latency)
 843
 844 config CACHE_FLUSH_L1
 845         bool "Locate cache flush funcs in L1 Inst Memory"
 846         default y
 847         help
 848           If enabled, the Blackfin cache flushing functions are linked
 849           into L1 instruction memory.
 850
 851           Note that this might be required to address anomalies, but
 852           these functions are pretty small, so it shouldn't be too bad.
 853           If you are using a processor affected by an anomaly, the build
 854           system will double check for you and prevent it.
 855
 856 config APP_STACK_L1
 857         bool "Support locating application stack in L1 Scratch Memory"
 858         default y
 859         help
 860           If enabled the application stack can be located in L1
 861           scratch memory (less latency).
 862
 863           Currently only works with FLAT binaries.
 864
 865 config EXCEPTION_L1_SCRATCH
 866         bool "Locate exception stack in L1 Scratch Memory"
 867         default n
 868         depends on !APP_STACK_L1
 869         help
 870           Whenever an exception occurs, use the L1 Scratch memory for
 871           stack storage.  You cannot place the stacks of FLAT binaries
 872           in L1 when using this option.
 873
 874           If you don't use L1 Scratch, then you should say Y here.
 875
 876 comment "Speed Optimizations"
 877 config BFIN_INS_LOWOVERHEAD
 878         bool "ins[bwl] low overhead, higher interrupt latency"
 879         default y
 880         help
 881           Reads on the Blackfin are speculative. In Blackfin terms, this means
 882           they can be interrupted at any time (even after they have been issued
 883           on to the external bus), and re-issued after the interrupt occurs.
 884           For memory - this is not a big deal, since memory does not change if
 885           it sees a read.
 886
 887           If a FIFO is sitting on the end of the read, it will see two reads,
 888           when the core only sees one since the FIFO receives both the read
 889           which is cancelled (and not delivered to the core) and the one which
 890           is re-issued (which is delivered to the core).
 891
 892           To solve this, interrupts are turned off before reads occur to
 893           I/O space. This option controls which the overhead/latency of
 894           controlling interrupts during this time
 895            "n" turns interrupts off every read
 896                 (higher overhead, but lower interrupt latency)
 897            "y" turns interrupts off every loop
 898                 (low overhead, but longer interrupt latency)
 899
 900           default behavior is to leave this set to on (type "Y"). If you are experiencing
 901           interrupt latency issues, it is safe and OK to turn this off.
 902
 903 endmenu
 904
 905 choice
 906         prompt "Kernel executes from"
 907         help
 908           Choose the memory type that the kernel will be running in.
 909
 910 config RAMKERNEL
 911         bool "RAM"
 912         help
 913           The kernel will be resident in RAM when running.
 914
 915 config ROMKERNEL
 916         bool "ROM"
 917         help
 918           The kernel will be resident in FLASH/ROM when running.
 919
 920 endchoice
 921
 922 source "mm/Kconfig"
 923
 924 config BFIN_GPTIMERS
 925         tristate "Enable Blackfin General Purpose Timers API"
 926         default n
 927         help
 928           Enable support for the General Purpose Timers API.  If you
 929           are unsure, say N.
 930
 931           To compile this driver as a module, choose M here: the module
 932           will be called gptimers.
 933
 934 choice
 935         prompt "Uncached DMA region"
 936         default DMA_UNCACHED_1M
 937 config DMA_UNCACHED_4M
 938         bool "Enable 4M DMA region"
 939 config DMA_UNCACHED_2M
 940         bool "Enable 2M DMA region"
 941 config DMA_UNCACHED_1M
 942         bool "Enable 1M DMA region"
 943 config DMA_UNCACHED_512K
 944         bool "Enable 512K DMA region"
 945 config DMA_UNCACHED_256K
 946         bool "Enable 256K DMA region"
 947 config DMA_UNCACHED_128K
 948         bool "Enable 128K DMA region"
 949 config DMA_UNCACHED_NONE
 950         bool "Disable DMA region"
 951 endchoice
 952
 953
 954 comment "Cache Support"
 955
 956 config BFIN_ICACHE
 957         bool "Enable ICACHE"
 958         default y
 959 config BFIN_EXTMEM_ICACHEABLE
 960         bool "Enable ICACHE for external memory"
 961         depends on BFIN_ICACHE
 962         default y
 963 config BFIN_L2_ICACHEABLE
 964         bool "Enable ICACHE for L2 SRAM"
 965         depends on BFIN_ICACHE
 966         depends on BF54x || BF561
 967         default n
 968
 969 config BFIN_DCACHE
 970         bool "Enable DCACHE"
 971         default y
 972 config BFIN_DCACHE_BANKA
 973         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 974         depends on BFIN_DCACHE && !BF531
 975         default n
 976 config BFIN_EXTMEM_DCACHEABLE
 977         bool "Enable DCACHE for external memory"
 978         depends on BFIN_DCACHE
 979         default y
 980 choice
 981         prompt "External memory DCACHE policy"
 982         depends on BFIN_EXTMEM_DCACHEABLE
 983         default BFIN_EXTMEM_WRITEBACK if !SMP
 984         default BFIN_EXTMEM_WRITETHROUGH if SMP
 985 config BFIN_EXTMEM_WRITEBACK
 986         bool "Write back"
 987         depends on !SMP
 988         help
 989           Write Back Policy:
 990             Cached data will be written back to SDRAM only when needed.
 991             This can give a nice increase in performance, but beware of
 992             broken drivers that do not properly invalidate/flush their
 993             cache.
 994
 995           Write Through Policy:
 996             Cached data will always be written back to SDRAM when the
 997             cache is updated.  This is a completely safe setting, but
 998             performance is worse than Write Back.
 999
1000           If you are unsure of the options and you want to be safe,
1001           then go with Write Through.
1002
1003 config BFIN_EXTMEM_WRITETHROUGH
1004         bool "Write through"
1005         help
1006           Write Back Policy:
1007             Cached data will be written back to SDRAM only when needed.
1008             This can give a nice increase in performance, but beware of
1009             broken drivers that do not properly invalidate/flush their
1010             cache.
1011
1012           Write Through Policy:
1013             Cached data will always be written back to SDRAM when the
1014             cache is updated.  This is a completely safe setting, but
1015             performance is worse than Write Back.
1016
1017           If you are unsure of the options and you want to be safe,
1018           then go with Write Through.
1019
1020 endchoice
1021
1022 config BFIN_L2_DCACHEABLE
1023         bool "Enable DCACHE for L2 SRAM"
1024         depends on BFIN_DCACHE
1025         depends on (BF54x || BF561) && !SMP
1026         default n
1027 choice
1028         prompt "L2 SRAM DCACHE policy"
1029         depends on BFIN_L2_DCACHEABLE
1030         default BFIN_L2_WRITEBACK
1031 config BFIN_L2_WRITEBACK
1032         bool "Write back"
1033
1034 config BFIN_L2_WRITETHROUGH
1035         bool "Write through"
1036 endchoice
1037
1038
1039 comment "Memory Protection Unit"
1040 config MPU
1041         bool "Enable the memory protection unit (EXPERIMENTAL)"
1042         default n
1043         help
1044           Use the processor's MPU to protect applications from accessing
1045           memory they do not own.  This comes at a performance penalty
1046           and is recommended only for debugging.
1047
1048 comment "Asynchronous Memory Configuration"
1049
1050 menu "EBIU_AMGCTL Global Control"
1051 config C_AMCKEN
1052         bool "Enable CLKOUT"
1053         default y
1054
1055 config C_CDPRIO
1056         bool "DMA has priority over core for ext. accesses"
1057         default n
1058
1059 config C_B0PEN
1060         depends on BF561
1061         bool "Bank 0 16 bit packing enable"
1062         default y
1063
1064 config C_B1PEN
1065         depends on BF561
1066         bool "Bank 1 16 bit packing enable"
1067         default y
1068
1069 config C_B2PEN
1070         depends on BF561
1071         bool "Bank 2 16 bit packing enable"
1072         default y
1073
1074 config C_B3PEN
1075         depends on BF561
1076         bool "Bank 3 16 bit packing enable"
1077         default n
1078
1079 choice
1080         prompt "Enable Asynchronous Memory Banks"
1081         default C_AMBEN_ALL
1082
1083 config C_AMBEN
1084         bool "Disable All Banks"
1085
1086 config C_AMBEN_B0
1087         bool "Enable Bank 0"
1088
1089 config C_AMBEN_B0_B1
1090         bool "Enable Bank 0 & 1"
1091
1092 config C_AMBEN_B0_B1_B2
1093         bool "Enable Bank 0 & 1 & 2"
1094
1095 config C_AMBEN_ALL
1096         bool "Enable All Banks"
1097 endchoice
1098 endmenu
1099
1100 menu "EBIU_AMBCTL Control"
1101 config BANK_0
1102         hex "Bank 0 (AMBCTL0.L)"
1103         default 0x7BB0
1104         help
1105           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1106           used to control the Asynchronous Memory Bank 0 settings.
1107
1108 config BANK_1
1109         hex "Bank 1 (AMBCTL0.H)"
1110         default 0x7BB0
1111         default 0x5558 if BF54x
1112         help
1113           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1114           used to control the Asynchronous Memory Bank 1 settings.
1115
1116 config BANK_2
1117         hex "Bank 2 (AMBCTL1.L)"
1118         default 0x7BB0
1119         help
1120           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1121           used to control the Asynchronous Memory Bank 2 settings.
1122
1123 config BANK_3
1124         hex "Bank 3 (AMBCTL1.H)"
1125         default 0x99B3
1126         help
1127           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1128           used to control the Asynchronous Memory Bank 3 settings.
1129
1130 endmenu
1131
1132 config EBIU_MBSCTLVAL
1133         hex "EBIU Bank Select Control Register"
1134         depends on BF54x
1135         default 0
1136
1137 config EBIU_MODEVAL
1138         hex "Flash Memory Mode Control Register"
1139         depends on BF54x
1140         default 1
1141
1142 config EBIU_FCTLVAL
1143         hex "Flash Memory Bank Control Register"
1144         depends on BF54x
1145         default 6
1146 endmenu
1147
1148 #############################################################################
1149 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1150
1151 config PCI
1152         bool "PCI support"
1153         depends on BROKEN
1154         help
1155           Support for PCI bus.
1156
1157 source "drivers/pci/Kconfig"
1158
1159 source "drivers/pcmcia/Kconfig"
1160
1161 source "drivers/pci/hotplug/Kconfig"
1162
1163 endmenu
1164
1165 menu "Executable file formats"
1166
1167 source "fs/Kconfig.binfmt"
1168
1169 endmenu
1170
1171 menu "Power management options"
1172
1173 source "kernel/power/Kconfig"
1174
1175 config ARCH_SUSPEND_POSSIBLE
1176         def_bool y
1177
1178 choice
1179         prompt "Standby Power Saving Mode"
1180         depends on PM
1181         default PM_BFIN_SLEEP_DEEPER
1182 config  PM_BFIN_SLEEP_DEEPER
1183         bool "Sleep Deeper"
1184         help
1185           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1186           power dissipation by disabling the clock to the processor core (CCLK).
1187           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1188           to 0.85 V to provide the greatest power savings, while preserving the
1189           processor state.
1190           The PLL and system clock (SCLK) continue to operate at a very low
1191           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1192           the SDRAM is put into Self Refresh Mode. Typically an external event
1193           such as GPIO interrupt or RTC activity wakes up the processor.
1194           Various Peripherals such as UART, SPORT, PPI may not function as
1195           normal during Sleep Deeper, due to the reduced SCLK frequency.
1196           When in the sleep mode, system DMA access to L1 memory is not supported.
1197
1198           If unsure, select "Sleep Deeper".
1199
1200 config  PM_BFIN_SLEEP
1201         bool "Sleep"
1202         help
1203           Sleep Mode (High Power Savings) - The sleep mode reduces power
1204           dissipation by disabling the clock to the processor core (CCLK).
1205           The PLL and system clock (SCLK), however, continue to operate in
1206           this mode. Typically an external event or RTC activity will wake
1207           up the processor. When in the sleep mode, system DMA access to L1
1208           memory is not supported.
1209
1210           If unsure, select "Sleep Deeper".
1211 endchoice
1212
1213 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1214         depends on PM
1215
1216 config PM_BFIN_WAKE_PH6
1217         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1218         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1219         default n
1220         help
1221           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1222
1223 config PM_BFIN_WAKE_GP
1224         bool "Allow Wake-Up from GPIOs"
1225         depends on PM && BF54x
1226         default n
1227         help
1228           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1229           (all processors, except ADSP-BF549). This option sets
1230           the general-purpose wake-up enable (GPWE) control bit to enable
1231           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1232           On ADSP-BF549 this option enables the the same functionality on the
1233           /MRXON pin also PH7.
1234
1235 endmenu
1236
1237 menu "CPU Frequency scaling"
1238
1239 source "drivers/cpufreq/Kconfig"
1240
1241 config BFIN_CPU_FREQ
1242         bool
1243         depends on CPU_FREQ
1244         select CPU_FREQ_TABLE
1245         default y
1246
1247 config CPU_VOLTAGE
1248         bool "CPU Voltage scaling"
1249         depends on EXPERIMENTAL
1250         depends on CPU_FREQ
1251         default n
1252         help
1253           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1254           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1255           manuals. There is a theoretical risk that during VDDINT transitions
1256           the PLL may unlock.
1257
1258 endmenu
1259
1260 source "net/Kconfig"
1261
1262 source "drivers/Kconfig"
1263
1264 source "drivers/firmware/Kconfig"
1265
1266 source "fs/Kconfig"
1267
1268 source "arch/blackfin/Kconfig.debug"
1269
1270 source "security/Kconfig"
1271
1272 source "crypto/Kconfig"
1273
1274 source "lib/Kconfig"