arch/avr32/mach-at32ap/intc.c

   1 /*
   2  * Copyright (C) 2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/err.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <asm/io.h>
  17
  18 #include "intc.h"
  19
  20 struct intc {
  21         void __iomem    *regs;
  22         struct irq_chip chip;
  23 };
  24
  25 extern struct platform_device at32_intc0_device;
  26
  27 /*
  28  * TODO: We may be able to implement mask/unmask by setting IxM flags
  29  * in the status register.
  30  */
  31 static void intc_mask_irq(unsigned int irq)
  32 {
  33
  34 }
  35
  36 static void intc_unmask_irq(unsigned int irq)
  37 {
  38
  39 }
  40
  41 static struct intc intc0 = {
  42         .chip = {
  43                 .name           = "intc",
  44                 .mask           = intc_mask_irq,
  45                 .unmask         = intc_unmask_irq,
  46         },
  47 };
  48
  49 /*
  50  * All interrupts go via intc at some point.
  51  */
  52 asmlinkage void do_IRQ(int level, struct pt_regs *regs)
  53 {
  54         struct irq_desc *desc;
  55         unsigned int irq;
  56         unsigned long status_reg;
  57
  58         local_irq_disable();
  59
  60         irq_enter();
  61
  62         irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
  63         desc = irq_desc + irq;
  64         desc->handle_irq(irq, desc, regs);
  65
  66         /*
  67          * Clear all interrupt level masks so that we may handle
  68          * interrupts during softirq processing.  If this is a nested
  69          * interrupt, interrupts must stay globally disabled until we
  70          * return.
  71          */
  72         status_reg = sysreg_read(SR);
  73         status_reg &= ~(SYSREG_BIT(I0M) | SYSREG_BIT(I1M)
  74                         | SYSREG_BIT(I2M) | SYSREG_BIT(I3M));
  75         sysreg_write(SR, status_reg);
  76
  77         irq_exit();
  78 }
  79
  80 void __init init_IRQ(void)
  81 {
  82         extern void _evba(void);
  83         extern void irq_level0(void);
  84         struct resource *regs;
  85         struct clk *pclk;
  86         unsigned int i;
  87         u32 offset, readback;
  88
  89         regs = platform_get_resource(&at32_intc0_device, IORESOURCE_MEM, 0);
  90         if (!regs) {
  91                 printk(KERN_EMERG "intc: no mmio resource defined\n");
  92                 goto fail;
  93         }
  94         pclk = clk_get(&at32_intc0_device.dev, "pclk");
  95         if (IS_ERR(pclk)) {
  96                 printk(KERN_EMERG "intc: no clock defined\n");
  97                 goto fail;
  98         }
  99
 100         clk_enable(pclk);
 101
 102         intc0.regs = ioremap(regs->start, regs->end - regs->start + 1);
 103         if (!intc0.regs) {
 104                 printk(KERN_EMERG "intc: failed to map registers (0x%08lx)\n",
 105                        (unsigned long)regs->start);
 106                 goto fail;
 107         }
 108
 109         /*
 110          * Initialize all interrupts to level 0 (lowest priority). The
 111          * priority level may be changed by calling
 112          * irq_set_priority().
 113          *
 114          */
 115         offset = (unsigned long)&irq_level0 - (unsigned long)&_evba;
 116         for (i = 0; i < NR_INTERNAL_IRQS; i++) {
 117                 intc_writel(&intc0, INTPR0 + 4 * i, offset);
 118                 readback = intc_readl(&intc0, INTPR0 + 4 * i);
 119                 if (readback == offset)
 120                         set_irq_chip_and_handler(i, &intc0.chip,
 121                                                  handle_simple_irq);
 122         }
 123
 124         /* Unmask all interrupt levels */
 125         sysreg_write(SR, (sysreg_read(SR)
 126                           & ~(SR_I3M | SR_I2M | SR_I1M | SR_I0M)));
 127
 128         return;
 129
 130 fail:
 131         panic("Interrupt controller initialization failed!\n");
 132 }
 133