arch/arm64/kernel/smp.c

   1 /*
   2  * SMP initialisation and IPI support
   3  * Based on arch/arm/kernel/smp.c
   4  *
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/sched.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/cache.h>
  26 #include <linux/profile.h>
  27 #include <linux/errno.h>
  28 #include <linux/mm.h>
  29 #include <linux/err.h>
  30 #include <linux/cpu.h>
  31 #include <linux/smp.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/irq.h>
  34 #include <linux/percpu.h>
  35 #include <linux/clockchips.h>
  36 #include <linux/completion.h>
  37 #include <linux/of.h>
  38
  39 #include <asm/atomic.h>
  40 #include <asm/cacheflush.h>
  41 #include <asm/cputype.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/pgalloc.h>
  45 #include <asm/processor.h>
  46 #include <asm/smp_plat.h>
  47 #include <asm/sections.h>
  48 #include <asm/tlbflush.h>
  49 #include <asm/ptrace.h>
  50
  51 /*
  52  * as from 2.5, kernels no longer have an init_tasks structure
  53  * so we need some other way of telling a new secondary core
  54  * where to place its SVC stack
  55  */
  56 struct secondary_data secondary_data;
  57 volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
  58
  59 enum ipi_msg_type {
  60         IPI_RESCHEDULE,
  61         IPI_CALL_FUNC,
  62         IPI_CALL_FUNC_SINGLE,
  63         IPI_CPU_STOP,
  64 };
  65
  66 static DEFINE_RAW_SPINLOCK(boot_lock);
  67
  68 /*
  69  * Write secondary_holding_pen_release in a way that is guaranteed to be
  70  * visible to all observers, irrespective of whether they're taking part
  71  * in coherency or not.  This is necessary for the hotplug code to work
  72  * reliably.
  73  */
  74 static void __cpuinit write_pen_release(u64 val)
  75 {
  76         void *start = (void *)&secondary_holding_pen_release;
  77         unsigned long size = sizeof(secondary_holding_pen_release);
  78
  79         secondary_holding_pen_release = val;
  80         __flush_dcache_area(start, size);
  81 }
  82
  83 /*
  84  * Boot a secondary CPU, and assign it the specified idle task.
  85  * This also gives us the initial stack to use for this CPU.
  86  */
  87 static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  88 {
  89         unsigned long timeout;
  90
  91         /*
  92          * Set synchronisation state between this boot processor
  93          * and the secondary one
  94          */
  95         raw_spin_lock(&boot_lock);
  96
  97         /*
  98          * Update the pen release flag.
  99          */
 100         write_pen_release(cpu_logical_map(cpu));
 101
 102         /*
 103          * Send an event, causing the secondaries to read pen_release.
 104          */
 105         sev();
 106
 107         timeout = jiffies + (1 * HZ);
 108         while (time_before(jiffies, timeout)) {
 109                 if (secondary_holding_pen_release == INVALID_HWID)
 110                         break;
 111                 udelay(10);
 112         }
 113
 114         /*
 115          * Now the secondary core is starting up let it run its
 116          * calibrations, then wait for it to finish
 117          */
 118         raw_spin_unlock(&boot_lock);
 119
 120         return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
 121 }
 122
 123 static DECLARE_COMPLETION(cpu_running);
 124
 125 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 126 {
 127         int ret;
 128
 129         /*
 130          * We need to tell the secondary core where to find its stack and the
 131          * page tables.
 132          */
 133         secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
 134         __flush_dcache_area(&secondary_data, sizeof(secondary_data));
 135
 136         /*
 137          * Now bring the CPU into our world.
 138          */
 139         ret = boot_secondary(cpu, idle);
 140         if (ret == 0) {
 141                 /*
 142                  * CPU was successfully started, wait for it to come online or
 143                  * time out.
 144                  */
 145                 wait_for_completion_timeout(&cpu_running,
 146                                             msecs_to_jiffies(1000));
 147
 148                 if (!cpu_online(cpu)) {
 149                         pr_crit("CPU%u: failed to come online\n", cpu);
 150                         ret = -EIO;
 151                 }
 152         } else {
 153                 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
 154         }
 155
 156         secondary_data.stack = NULL;
 157
 158         return ret;
 159 }
 160
 161 /*
 162  * This is the secondary CPU boot entry.  We're using this CPUs
 163  * idle thread stack, but a set of temporary page tables.
 164  */
 165 asmlinkage void __cpuinit secondary_start_kernel(void)
 166 {
 167         struct mm_struct *mm = &init_mm;
 168         unsigned int cpu = smp_processor_id();
 169
 170         printk("CPU%u: Booted secondary processor\n", cpu);
 171
 172         /*
 173          * All kernel threads share the same mm context; grab a
 174          * reference and switch to it.
 175          */
 176         atomic_inc(&mm->mm_count);
 177         current->active_mm = mm;
 178         cpumask_set_cpu(cpu, mm_cpumask(mm));
 179
 180         /*
 181          * TTBR0 is only used for the identity mapping at this stage. Make it
 182          * point to zero page to avoid speculatively fetching new entries.
 183          */
 184         cpu_set_reserved_ttbr0();
 185         flush_tlb_all();
 186
 187         preempt_disable();
 188         trace_hardirqs_off();
 189
 190         /*
 191          * Let the primary processor know we're out of the
 192          * pen, then head off into the C entry point
 193          */
 194         write_pen_release(INVALID_HWID);
 195
 196         /*
 197          * Synchronise with the boot thread.
 198          */
 199         raw_spin_lock(&boot_lock);
 200         raw_spin_unlock(&boot_lock);
 201
 202         /*
 203          * Enable local interrupts.
 204          */
 205         notify_cpu_starting(cpu);
 206         local_irq_enable();
 207         local_fiq_enable();
 208
 209         /*
 210          * OK, now it's safe to let the boot CPU continue.  Wait for
 211          * the CPU migration code to notice that the CPU is online
 212          * before we continue.
 213          */
 214         set_cpu_online(cpu, true);
 215         complete(&cpu_running);
 216
 217         /*
 218          * OK, it's off to the idle thread for us
 219          */
 220         cpu_startup_entry(CPUHP_ONLINE);
 221 }
 222
 223 void __init smp_cpus_done(unsigned int max_cpus)
 224 {
 225         unsigned long bogosum = loops_per_jiffy * num_online_cpus();
 226
 227         pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
 228                 num_online_cpus(), bogosum / (500000/HZ),
 229                 (bogosum / (5000/HZ)) % 100);
 230 }
 231
 232 void __init smp_prepare_boot_cpu(void)
 233 {
 234 }
 235
 236 static void (*smp_cross_call)(const struct cpumask *, unsigned int);
 237
 238 static const struct smp_enable_ops *enable_ops[] __initconst = {
 239         &smp_spin_table_ops,
 240         &smp_psci_ops,
 241         NULL,
 242 };
 243
 244 static const struct smp_enable_ops *smp_enable_ops[NR_CPUS];
 245
 246 static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name)
 247 {
 248         const struct smp_enable_ops **ops = enable_ops;
 249
 250         while (*ops) {
 251                 if (!strcmp(name, (*ops)->name))
 252                         return *ops;
 253
 254                 ops++;
 255         }
 256
 257         return NULL;
 258 }
 259
 260 /*
 261  * Enumerate the possible CPU set from the device tree and build the
 262  * cpu logical map array containing MPIDR values related to logical
 263  * cpus. Assumes that cpu_logical_map(0) has already been initialized.
 264  */
 265 void __init smp_init_cpus(void)
 266 {
 267         const char *enable_method;
 268         struct device_node *dn = NULL;
 269         int i, cpu = 1;
 270         bool bootcpu_valid = false;
 271
 272         while ((dn = of_find_node_by_type(dn, "cpu"))) {
 273                 const u32 *cell;
 274                 u64 hwid;
 275
 276                 /*
 277                  * A cpu node with missing "reg" property is
 278                  * considered invalid to build a cpu_logical_map
 279                  * entry.
 280                  */
 281                 cell = of_get_property(dn, "reg", NULL);
 282                 if (!cell) {
 283                         pr_err("%s: missing reg property\n", dn->full_name);
 284                         goto next;
 285                 }
 286                 hwid = of_read_number(cell, of_n_addr_cells(dn));
 287
 288                 /*
 289                  * Non affinity bits must be set to 0 in the DT
 290                  */
 291                 if (hwid & ~MPIDR_HWID_BITMASK) {
 292                         pr_err("%s: invalid reg property\n", dn->full_name);
 293                         goto next;
 294                 }
 295
 296                 /*
 297                  * Duplicate MPIDRs are a recipe for disaster. Scan
 298                  * all initialized entries and check for
 299                  * duplicates. If any is found just ignore the cpu.
 300                  * cpu_logical_map was initialized to INVALID_HWID to
 301                  * avoid matching valid MPIDR values.
 302                  */
 303                 for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
 304                         if (cpu_logical_map(i) == hwid) {
 305                                 pr_err("%s: duplicate cpu reg properties in the DT\n",
 306                                         dn->full_name);
 307                                 goto next;
 308                         }
 309                 }
 310
 311                 /*
 312                  * The numbering scheme requires that the boot CPU
 313                  * must be assigned logical id 0. Record it so that
 314                  * the logical map built from DT is validated and can
 315                  * be used.
 316                  */
 317                 if (hwid == cpu_logical_map(0)) {
 318                         if (bootcpu_valid) {
 319                                 pr_err("%s: duplicate boot cpu reg property in DT\n",
 320                                         dn->full_name);
 321                                 goto next;
 322                         }
 323
 324                         bootcpu_valid = true;
 325
 326                         /*
 327                          * cpu_logical_map has already been
 328                          * initialized and the boot cpu doesn't need
 329                          * the enable-method so continue without
 330                          * incrementing cpu.
 331                          */
 332                         continue;
 333                 }
 334
 335                 if (cpu >= NR_CPUS)
 336                         goto next;
 337
 338                 /*
 339                  * We currently support only the "spin-table" enable-method.
 340                  */
 341                 enable_method = of_get_property(dn, "enable-method", NULL);
 342                 if (!enable_method) {
 343                         pr_err("%s: missing enable-method property\n",
 344                                 dn->full_name);
 345                         goto next;
 346                 }
 347
 348                 smp_enable_ops[cpu] = smp_get_enable_ops(enable_method);
 349
 350                 if (!smp_enable_ops[cpu]) {
 351                         pr_err("%s: invalid enable-method property: %s\n",
 352                                dn->full_name, enable_method);
 353                         goto next;
 354                 }
 355
 356                 if (smp_enable_ops[cpu]->init_cpu(dn, cpu))
 357                         goto next;
 358
 359                 pr_debug("cpu logical map 0x%llx\n", hwid);
 360                 cpu_logical_map(cpu) = hwid;
 361 next:
 362                 cpu++;
 363         }
 364
 365         /* sanity check */
 366         if (cpu > NR_CPUS)
 367                 pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
 368                            cpu, NR_CPUS);
 369
 370         if (!bootcpu_valid) {
 371                 pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
 372                 return;
 373         }
 374
 375         /*
 376          * All the cpus that made it to the cpu_logical_map have been
 377          * validated so set them as possible cpus.
 378          */
 379         for (i = 0; i < NR_CPUS; i++)
 380                 if (cpu_logical_map(i) != INVALID_HWID)
 381                         set_cpu_possible(i, true);
 382 }
 383
 384 void __init smp_prepare_cpus(unsigned int max_cpus)
 385 {
 386         int cpu, err;
 387         unsigned int ncores = num_possible_cpus();
 388
 389         /*
 390          * are we trying to boot more cores than exist?
 391          */
 392         if (max_cpus > ncores)
 393                 max_cpus = ncores;
 394
 395         /* Don't bother if we're effectively UP */
 396         if (max_cpus <= 1)
 397                 return;
 398
 399         /*
 400          * Initialise the present map (which describes the set of CPUs
 401          * actually populated at the present time) and release the
 402          * secondaries from the bootloader.
 403          *
 404          * Make sure we online at most (max_cpus - 1) additional CPUs.
 405          */
 406         max_cpus--;
 407         for_each_possible_cpu(cpu) {
 408                 if (max_cpus == 0)
 409                         break;
 410
 411                 if (cpu == smp_processor_id())
 412                         continue;
 413
 414                 if (!smp_enable_ops[cpu])
 415                         continue;
 416
 417                 err = smp_enable_ops[cpu]->prepare_cpu(cpu);
 418                 if (err)
 419                         continue;
 420
 421                 set_cpu_present(cpu, true);
 422                 max_cpus--;
 423         }
 424 }
 425
 426
 427 void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
 428 {
 429         smp_cross_call = fn;
 430 }
 431
 432 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 433 {
 434         smp_cross_call(mask, IPI_CALL_FUNC);
 435 }
 436
 437 void arch_send_call_function_single_ipi(int cpu)
 438 {
 439         smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
 440 }
 441
 442 static const char *ipi_types[NR_IPI] = {
 443 #define S(x,s)  [x - IPI_RESCHEDULE] = s
 444         S(IPI_RESCHEDULE, "Rescheduling interrupts"),
 445         S(IPI_CALL_FUNC, "Function call interrupts"),
 446         S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
 447         S(IPI_CPU_STOP, "CPU stop interrupts"),
 448 };
 449
 450 void show_ipi_list(struct seq_file *p, int prec)
 451 {
 452         unsigned int cpu, i;
 453
 454         for (i = 0; i < NR_IPI; i++) {
 455                 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE,
 456                            prec >= 4 ? " " : "");
 457                 for_each_present_cpu(cpu)
 458                         seq_printf(p, "%10u ",
 459                                    __get_irq_stat(cpu, ipi_irqs[i]));
 460                 seq_printf(p, "      %s\n", ipi_types[i]);
 461         }
 462 }
 463
 464 u64 smp_irq_stat_cpu(unsigned int cpu)
 465 {
 466         u64 sum = 0;
 467         int i;
 468
 469         for (i = 0; i < NR_IPI; i++)
 470                 sum += __get_irq_stat(cpu, ipi_irqs[i]);
 471
 472         return sum;
 473 }
 474
 475 static DEFINE_RAW_SPINLOCK(stop_lock);
 476
 477 /*
 478  * ipi_cpu_stop - handle IPI from smp_send_stop()
 479  */
 480 static void ipi_cpu_stop(unsigned int cpu)
 481 {
 482         if (system_state == SYSTEM_BOOTING ||
 483             system_state == SYSTEM_RUNNING) {
 484                 raw_spin_lock(&stop_lock);
 485                 pr_crit("CPU%u: stopping\n", cpu);
 486                 dump_stack();
 487                 raw_spin_unlock(&stop_lock);
 488         }
 489
 490         set_cpu_online(cpu, false);
 491
 492         local_fiq_disable();
 493         local_irq_disable();
 494
 495         while (1)
 496                 cpu_relax();
 497 }
 498
 499 /*
 500  * Main handler for inter-processor interrupts
 501  */
 502 void handle_IPI(int ipinr, struct pt_regs *regs)
 503 {
 504         unsigned int cpu = smp_processor_id();
 505         struct pt_regs *old_regs = set_irq_regs(regs);
 506
 507         if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI)
 508                 __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]);
 509
 510         switch (ipinr) {
 511         case IPI_RESCHEDULE:
 512                 scheduler_ipi();
 513                 break;
 514
 515         case IPI_CALL_FUNC:
 516                 irq_enter();
 517                 generic_smp_call_function_interrupt();
 518                 irq_exit();
 519                 break;
 520
 521         case IPI_CALL_FUNC_SINGLE:
 522                 irq_enter();
 523                 generic_smp_call_function_single_interrupt();
 524                 irq_exit();
 525                 break;
 526
 527         case IPI_CPU_STOP:
 528                 irq_enter();
 529                 ipi_cpu_stop(cpu);
 530                 irq_exit();
 531                 break;
 532
 533         default:
 534                 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
 535                 break;
 536         }
 537         set_irq_regs(old_regs);
 538 }
 539
 540 void smp_send_reschedule(int cpu)
 541 {
 542         smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 543 }
 544
 545 void smp_send_stop(void)
 546 {
 547         unsigned long timeout;
 548
 549         if (num_online_cpus() > 1) {
 550                 cpumask_t mask;
 551
 552                 cpumask_copy(&mask, cpu_online_mask);
 553                 cpu_clear(smp_processor_id(), mask);
 554
 555                 smp_cross_call(&mask, IPI_CPU_STOP);
 556         }
 557
 558         /* Wait up to one second for other CPUs to stop */
 559         timeout = USEC_PER_SEC;
 560         while (num_online_cpus() > 1 && timeout--)
 561                 udelay(1);
 562
 563         if (num_online_cpus() > 1)
 564                 pr_warning("SMP: failed to stop secondary CPUs\n");
 565 }
 566
 567 /*
 568  * not supported here
 569  */
 570 int setup_profiling_timer(unsigned int multiplier)
 571 {
 572         return -EINVAL;
 573 }