arch/arm/plat-samsung/gpio-config.c

   1 /* linux/arch/arm/plat-s3c/gpio-config.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008-2010 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C series GPIO configuration core
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/gpio.h>
  18 #include <linux/io.h>
  19
  20 #include <plat/gpio-core.h>
  21 #include <plat/gpio-cfg.h>
  22 #include <plat/gpio-cfg-helpers.h>
  23
  24 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
  25 {
  26         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
  27         unsigned long flags;
  28         int offset;
  29         int ret;
  30
  31         if (!chip)
  32                 return -EINVAL;
  33
  34         offset = pin - chip->chip.base;
  35
  36         s3c_gpio_lock(chip, flags);
  37         ret = s3c_gpio_do_setcfg(chip, offset, config);
  38         s3c_gpio_unlock(chip, flags);
  39
  40         return ret;
  41 }
  42 EXPORT_SYMBOL(s3c_gpio_cfgpin);
  43
  44 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
  45                           unsigned int cfg)
  46 {
  47         int ret;
  48
  49         for (; nr > 0; nr--, start++) {
  50                 ret = s3c_gpio_cfgpin(start, cfg);
  51                 if (ret != 0)
  52                         return ret;
  53         }
  54
  55         return 0;
  56 }
  57 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
  58
  59 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
  60                           unsigned int cfg, s3c_gpio_pull_t pull)
  61 {
  62         int ret;
  63
  64         for (; nr > 0; nr--, start++) {
  65                 s3c_gpio_setpull(start, pull);
  66                 ret = s3c_gpio_cfgpin(start, cfg);
  67                 if (ret != 0)
  68                         return ret;
  69         }
  70
  71         return 0;
  72 }
  73 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
  74
  75 unsigned s3c_gpio_getcfg(unsigned int pin)
  76 {
  77         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
  78         unsigned long flags;
  79         unsigned ret = 0;
  80         int offset;
  81
  82         if (chip) {
  83                 offset = pin - chip->chip.base;
  84
  85                 s3c_gpio_lock(chip, flags);
  86                 ret = s3c_gpio_do_getcfg(chip, offset);
  87                 s3c_gpio_unlock(chip, flags);
  88         }
  89
  90         return ret;
  91 }
  92 EXPORT_SYMBOL(s3c_gpio_getcfg);
  93
  94
  95 int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
  96 {
  97         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
  98         unsigned long flags;
  99         int offset, ret;
 100
 101         if (!chip)
 102                 return -EINVAL;
 103
 104         offset = pin - chip->chip.base;
 105
 106         s3c_gpio_lock(chip, flags);
 107         ret = s3c_gpio_do_setpull(chip, offset, pull);
 108         s3c_gpio_unlock(chip, flags);
 109
 110         return ret;
 111 }
 112 EXPORT_SYMBOL(s3c_gpio_setpull);
 113
 114 s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
 115 {
 116         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
 117         unsigned long flags;
 118         int offset;
 119         u32 pup = 0;
 120
 121         if (chip) {
 122                 offset = pin - chip->chip.base;
 123
 124                 s3c_gpio_lock(chip, flags);
 125                 pup = s3c_gpio_do_getpull(chip, offset);
 126                 s3c_gpio_unlock(chip, flags);
 127         }
 128
 129         return (__force s3c_gpio_pull_t)pup;
 130 }
 131 EXPORT_SYMBOL(s3c_gpio_getpull);
 132
 133 #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
 134 int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
 135                               unsigned int off, unsigned int cfg)
 136 {
 137         void __iomem *reg = chip->base;
 138         unsigned int shift = off;
 139         u32 con;
 140
 141         if (s3c_gpio_is_cfg_special(cfg)) {
 142                 cfg &= 0xf;
 143
 144                 /* Map output to 0, and SFN2 to 1 */
 145                 cfg -= 1;
 146                 if (cfg > 1)
 147                         return -EINVAL;
 148
 149                 cfg <<= shift;
 150         }
 151
 152         con = __raw_readl(reg);
 153         con &= ~(0x1 << shift);
 154         con |= cfg;
 155         __raw_writel(con, reg);
 156
 157         return 0;
 158 }
 159
 160 unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
 161                                    unsigned int off)
 162 {
 163         u32 con;
 164
 165         con = __raw_readl(chip->base);
 166         con >>= off;
 167         con &= 1;
 168         con++;
 169
 170         return S3C_GPIO_SFN(con);
 171 }
 172
 173 int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
 174                             unsigned int off, unsigned int cfg)
 175 {
 176         void __iomem *reg = chip->base;
 177         unsigned int shift = off * 2;
 178         u32 con;
 179
 180         if (s3c_gpio_is_cfg_special(cfg)) {
 181                 cfg &= 0xf;
 182                 if (cfg > 3)
 183                         return -EINVAL;
 184
 185                 cfg <<= shift;
 186         }
 187
 188         con = __raw_readl(reg);
 189         con &= ~(0x3 << shift);
 190         con |= cfg;
 191         __raw_writel(con, reg);
 192
 193         return 0;
 194 }
 195
 196 unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
 197                                      unsigned int off)
 198 {
 199         u32 con;
 200
 201         con = __raw_readl(chip->base);
 202         con >>= off * 2;
 203         con &= 3;
 204
 205         /* this conversion works for IN and OUT as well as special mode */
 206         return S3C_GPIO_SPECIAL(con);
 207 }
 208 #endif
 209
 210 #ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
 211 int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
 212                                  unsigned int off, unsigned int cfg)
 213 {
 214         void __iomem *reg = chip->base;
 215         unsigned int shift = (off & 7) * 4;
 216         u32 con;
 217
 218         if (off < 8 && chip->chip.ngpio > 8)
 219                 reg -= 4;
 220
 221         if (s3c_gpio_is_cfg_special(cfg)) {
 222                 cfg &= 0xf;
 223                 cfg <<= shift;
 224         }
 225
 226         con = __raw_readl(reg);
 227         con &= ~(0xf << shift);
 228         con |= cfg;
 229         __raw_writel(con, reg);
 230
 231         return 0;
 232 }
 233
 234 unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
 235                                       unsigned int off)
 236 {
 237         void __iomem *reg = chip->base;
 238         unsigned int shift = (off & 7) * 4;
 239         u32 con;
 240
 241         if (off < 8 && chip->chip.ngpio > 8)
 242                 reg -= 4;
 243
 244         con = __raw_readl(reg);
 245         con >>= shift;
 246         con &= 0xf;
 247
 248         /* this conversion works for IN and OUT as well as special mode */
 249         return S3C_GPIO_SPECIAL(con);
 250 }
 251
 252 #endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
 253
 254 #ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
 255 int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
 256                             unsigned int off, s3c_gpio_pull_t pull)
 257 {
 258         void __iomem *reg = chip->base + 0x08;
 259         int shift = off * 2;
 260         u32 pup;
 261
 262         pup = __raw_readl(reg);
 263         pup &= ~(3 << shift);
 264         pup |= pull << shift;
 265         __raw_writel(pup, reg);
 266
 267         return 0;
 268 }
 269
 270 s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
 271                                         unsigned int off)
 272 {
 273         void __iomem *reg = chip->base + 0x08;
 274         int shift = off * 2;
 275         u32 pup = __raw_readl(reg);
 276
 277         pup >>= shift;
 278         pup &= 0x3;
 279         return (__force s3c_gpio_pull_t)pup;
 280 }
 281 #endif
 282
 283 #ifdef CONFIG_S3C_GPIO_PULL_UP
 284 int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
 285                          unsigned int off, s3c_gpio_pull_t pull)
 286 {
 287         void __iomem *reg = chip->base + 0x08;
 288         u32 pup = __raw_readl(reg);
 289
 290         pup = __raw_readl(reg);
 291
 292         if (pup == S3C_GPIO_PULL_UP)
 293                 pup &= ~(1 << off);
 294         else if (pup == S3C_GPIO_PULL_NONE)
 295                 pup |= (1 << off);
 296         else
 297                 return -EINVAL;
 298
 299         __raw_writel(pup, reg);
 300         return 0;
 301 }
 302
 303 s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
 304                                      unsigned int off)
 305 {
 306         void __iomem *reg = chip->base + 0x08;
 307         u32 pup = __raw_readl(reg);
 308
 309         pup &= (1 << off);
 310         return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
 311 }
 312 #endif /* CONFIG_S3C_GPIO_PULL_UP */
 313
 314 #ifdef CONFIG_S5P_GPIO_DRVSTR
 315 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
 316 {
 317         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
 318         unsigned int off;
 319         void __iomem *reg;
 320         int shift;
 321         u32 drvstr;
 322
 323         if (!chip)
 324                 return -EINVAL;
 325
 326         off = pin - chip->chip.base;
 327         shift = off * 2;
 328         reg = chip->base + 0x0C;
 329
 330         drvstr = __raw_readl(reg);
 331         drvstr = drvstr >> shift;
 332         drvstr &= 0x3;
 333
 334         return (__force s5p_gpio_drvstr_t)drvstr;
 335 }
 336 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
 337
 338 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
 339 {
 340         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
 341         unsigned int off;
 342         void __iomem *reg;
 343         int shift;
 344         u32 tmp;
 345
 346         if (!chip)
 347                 return -EINVAL;
 348
 349         off = pin - chip->chip.base;
 350         shift = off * 2;
 351         reg = chip->base + 0x0C;
 352
 353         tmp = __raw_readl(reg);
 354         tmp &= ~(0x3 << shift);
 355         tmp |= drvstr << shift;
 356
 357         __raw_writel(tmp, reg);
 358
 359         return 0;
 360 }
 361 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
 362 #endif  /* CONFIG_S5P_GPIO_DRVSTR */