projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / plat-samsung / devs.c
1 /* linux/arch/arm/plat-samsung/devs.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Base SAMSUNG platform device definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/amba/pl330.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/timer.h>
19 #include <linux/init.h>
20 #include <linux/serial_core.h>
21 #include <linux/platform_device.h>
22 #include <linux/io.h>
23 #include <linux/slab.h>
24 #include <linux/string.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/fb.h>
27 #include <linux/gfp.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/onenand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mmc/host.h>
32 #include <linux/ioport.h>
33 #include <linux/platform_data/s3c-hsudc.h>
34 #include <linux/platform_data/s3c-hsotg.h>
35
36 #include <media/s5p_hdmi.h>
37
38 #include <asm/irq.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/irq.h>
42
43 #include <mach/hardware.h>
44 #include <mach/dma.h>
45 #include <mach/irqs.h>
46 #include <mach/map.h>
47
48 #include <plat/cpu.h>
49 #include <plat/devs.h>
50 #include <plat/adc.h>
51 #include <linux/platform_data/ata-samsung_cf.h>
52 #include <linux/platform_data/usb-ehci-s5p.h>
53 #include <plat/fb.h>
54 #include <plat/fb-s3c2410.h>
55 #include <plat/hdmi.h>
56 #include <linux/platform_data/hwmon-s3c.h>
57 #include <linux/platform_data/i2c-s3c2410.h>
58 #include <plat/keypad.h>
59 #include <linux/platform_data/mmc-s3cmci.h>
60 #include <linux/platform_data/mtd-nand-s3c2410.h>
61 #include <plat/sdhci.h>
62 #include <linux/platform_data/touchscreen-s3c2410.h>
63 #include <linux/platform_data/usb-s3c2410_udc.h>
64 #include <linux/platform_data/usb-ohci-s3c2410.h>
65 #include <plat/usb-phy.h>
66 #include <plat/regs-serial.h>
67 #include <plat/regs-spi.h>
68 #include <linux/platform_data/spi-s3c64xx.h>
69
70 static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
71
72 /* AC97 */
73 #ifdef CONFIG_CPU_S3C2440
74 static struct resource s3c_ac97_resource[] = {
75 [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
76 [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
77 [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
78 [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
79 [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
80 };
81
82 struct platform_device s3c_device_ac97 = {
83 .name = "samsung-ac97",
84 .id = -1,
85 .num_resources = ARRAY_SIZE(s3c_ac97_resource),
86 .resource = s3c_ac97_resource,
87 .dev = {
88 .dma_mask = &samsung_device_dma_mask,
89 .coherent_dma_mask = DMA_BIT_MASK(32),
90 }
91 };
92 #endif /* CONFIG_CPU_S3C2440 */
93
94 /* ADC */
95
96 #ifdef CONFIG_PLAT_S3C24XX
97 static struct resource s3c_adc_resource[] = {
98 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
99 [1] = DEFINE_RES_IRQ(IRQ_TC),
100 [2] = DEFINE_RES_IRQ(IRQ_ADC),
101 };
102
103 struct platform_device s3c_device_adc = {
104 .name = "s3c24xx-adc",
105 .id = -1,
106 .num_resources = ARRAY_SIZE(s3c_adc_resource),
107 .resource = s3c_adc_resource,
108 };
109 #endif /* CONFIG_PLAT_S3C24XX */
110
111 #if defined(CONFIG_SAMSUNG_DEV_ADC)
112 static struct resource s3c_adc_resource[] = {
113 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
114 [1] = DEFINE_RES_IRQ(IRQ_TC),
115 [2] = DEFINE_RES_IRQ(IRQ_ADC),
116 };
117
118 struct platform_device s3c_device_adc = {
119 .name = "samsung-adc",
120 .id = -1,
121 .num_resources = ARRAY_SIZE(s3c_adc_resource),
122 .resource = s3c_adc_resource,
123 };
124 #endif /* CONFIG_SAMSUNG_DEV_ADC */
125
126 /* Camif Controller */
127
128 #ifdef CONFIG_CPU_S3C2440
129 static struct resource s3c_camif_resource[] = {
130 [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
131 [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
132 [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
133 };
134
135 struct platform_device s3c_device_camif = {
136 .name = "s3c2440-camif",
137 .id = -1,
138 .num_resources = ARRAY_SIZE(s3c_camif_resource),
139 .resource = s3c_camif_resource,
140 .dev = {
141 .dma_mask = &samsung_device_dma_mask,
142 .coherent_dma_mask = DMA_BIT_MASK(32),
143 }
144 };
145 #endif /* CONFIG_CPU_S3C2440 */
146
147 /* ASOC DMA */
148
149 #ifdef CONFIG_PLAT_S5P
150 static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0);
151
152 struct platform_device samsung_asoc_idma = {
153 .name = "samsung-idma",
154 .id = -1,
155 .num_resources = 1,
156 .resource = &samsung_asoc_idma_resource,
157 .dev = {
158 .dma_mask = &samsung_device_dma_mask,
159 .coherent_dma_mask = DMA_BIT_MASK(32),
160 }
161 };
162 #endif
163
164 /* FB */
165
166 #ifdef CONFIG_S3C_DEV_FB
167 static struct resource s3c_fb_resource[] = {
168 [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
169 [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
170 [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
171 [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
172 };
173
174 struct platform_device s3c_device_fb = {
175 .name = "s3c-fb",
176 .id = -1,
177 .num_resources = ARRAY_SIZE(s3c_fb_resource),
178 .resource = s3c_fb_resource,
179 .dev = {
180 .dma_mask = &samsung_device_dma_mask,
181 .coherent_dma_mask = DMA_BIT_MASK(32),
182 },
183 };
184
185 void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
186 {
187 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
188 &s3c_device_fb);
189 }
190 #endif /* CONFIG_S3C_DEV_FB */
191
192 /* FIMC */
193
194 #ifdef CONFIG_S5P_DEV_FIMC0
195 static struct resource s5p_fimc0_resource[] = {
196 [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
197 [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
198 };
199
200 struct platform_device s5p_device_fimc0 = {
201 .name = "s5p-fimc",
202 .id = 0,
203 .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
204 .resource = s5p_fimc0_resource,
205 .dev = {
206 .dma_mask = &samsung_device_dma_mask,
207 .coherent_dma_mask = DMA_BIT_MASK(32),
208 },
209 };
210
211 struct platform_device s5p_device_fimc_md = {
212 .name = "s5p-fimc-md",
213 .id = -1,
214 };
215 #endif /* CONFIG_S5P_DEV_FIMC0 */
216
217 #ifdef CONFIG_S5P_DEV_FIMC1
218 static struct resource s5p_fimc1_resource[] = {
219 [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
220 [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
221 };
222
223 struct platform_device s5p_device_fimc1 = {
224 .name = "s5p-fimc",
225 .id = 1,
226 .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
227 .resource = s5p_fimc1_resource,
228 .dev = {
229 .dma_mask = &samsung_device_dma_mask,
230 .coherent_dma_mask = DMA_BIT_MASK(32),
231 },
232 };
233 #endif /* CONFIG_S5P_DEV_FIMC1 */
234
235 #ifdef CONFIG_S5P_DEV_FIMC2
236 static struct resource s5p_fimc2_resource[] = {
237 [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
238 [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
239 };
240
241 struct platform_device s5p_device_fimc2 = {
242 .name = "s5p-fimc",
243 .id = 2,
244 .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
245 .resource = s5p_fimc2_resource,
246 .dev = {
247 .dma_mask = &samsung_device_dma_mask,
248 .coherent_dma_mask = DMA_BIT_MASK(32),
249 },
250 };
251 #endif /* CONFIG_S5P_DEV_FIMC2 */
252
253 #ifdef CONFIG_S5P_DEV_FIMC3
254 static struct resource s5p_fimc3_resource[] = {
255 [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
256 [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
257 };
258
259 struct platform_device s5p_device_fimc3 = {
260 .name = "s5p-fimc",
261 .id = 3,
262 .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
263 .resource = s5p_fimc3_resource,
264 .dev = {
265 .dma_mask = &samsung_device_dma_mask,
266 .coherent_dma_mask = DMA_BIT_MASK(32),
267 },
268 };
269 #endif /* CONFIG_S5P_DEV_FIMC3 */
270
271 /* G2D */
272
273 #ifdef CONFIG_S5P_DEV_G2D
274 static struct resource s5p_g2d_resource[] = {
275 [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
276 [1] = DEFINE_RES_IRQ(IRQ_2D),
277 };
278
279 struct platform_device s5p_device_g2d = {
280 .name = "s5p-g2d",
281 .id = 0,
282 .num_resources = ARRAY_SIZE(s5p_g2d_resource),
283 .resource = s5p_g2d_resource,
284 .dev = {
285 .dma_mask = &samsung_device_dma_mask,
286 .coherent_dma_mask = DMA_BIT_MASK(32),
287 },
288 };
289 #endif /* CONFIG_S5P_DEV_G2D */
290
291 #ifdef CONFIG_S5P_DEV_JPEG
292 static struct resource s5p_jpeg_resource[] = {
293 [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
294 [1] = DEFINE_RES_IRQ(IRQ_JPEG),
295 };
296
297 struct platform_device s5p_device_jpeg = {
298 .name = "s5p-jpeg",
299 .id = 0,
300 .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
301 .resource = s5p_jpeg_resource,
302 .dev = {
303 .dma_mask = &samsung_device_dma_mask,
304 .coherent_dma_mask = DMA_BIT_MASK(32),
305 },
306 };
307 #endif /* CONFIG_S5P_DEV_JPEG */
308
309 /* FIMD0 */
310
311 #ifdef CONFIG_S5P_DEV_FIMD0
312 static struct resource s5p_fimd0_resource[] = {
313 [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
314 [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
315 [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
316 [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
317 };
318
319 struct platform_device s5p_device_fimd0 = {
320 .name = "s5p-fb",
321 .id = 0,
322 .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
323 .resource = s5p_fimd0_resource,
324 .dev = {
325 .dma_mask = &samsung_device_dma_mask,
326 .coherent_dma_mask = DMA_BIT_MASK(32),
327 },
328 };
329
330 void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
331 {
332 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
333 &s5p_device_fimd0);
334 }
335 #endif /* CONFIG_S5P_DEV_FIMD0 */
336
337 /* HWMON */
338
339 #ifdef CONFIG_S3C_DEV_HWMON
340 struct platform_device s3c_device_hwmon = {
341 .name = "s3c-hwmon",
342 .id = -1,
343 .dev.parent = &s3c_device_adc.dev,
344 };
345
346 void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
347 {
348 s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
349 &s3c_device_hwmon);
350 }
351 #endif /* CONFIG_S3C_DEV_HWMON */
352
353 /* HSMMC */
354
355 #ifdef CONFIG_S3C_DEV_HSMMC
356 static struct resource s3c_hsmmc_resource[] = {
357 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
358 [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
359 };
360
361 struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
362 .max_width = 4,
363 .host_caps = (MMC_CAP_4_BIT_DATA |
364 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
365 };
366
367 struct platform_device s3c_device_hsmmc0 = {
368 .name = "s3c-sdhci",
369 .id = 0,
370 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
371 .resource = s3c_hsmmc_resource,
372 .dev = {
373 .dma_mask = &samsung_device_dma_mask,
374 .coherent_dma_mask = DMA_BIT_MASK(32),
375 .platform_data = &s3c_hsmmc0_def_platdata,
376 },
377 };
378
379 void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
380 {
381 s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
382 }
383 #endif /* CONFIG_S3C_DEV_HSMMC */
384
385 #ifdef CONFIG_S3C_DEV_HSMMC1
386 static struct resource s3c_hsmmc1_resource[] = {
387 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
388 [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
389 };
390
391 struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
392 .max_width = 4,
393 .host_caps = (MMC_CAP_4_BIT_DATA |
394 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
395 };
396
397 struct platform_device s3c_device_hsmmc1 = {
398 .name = "s3c-sdhci",
399 .id = 1,
400 .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
401 .resource = s3c_hsmmc1_resource,
402 .dev = {
403 .dma_mask = &samsung_device_dma_mask,
404 .coherent_dma_mask = DMA_BIT_MASK(32),
405 .platform_data = &s3c_hsmmc1_def_platdata,
406 },
407 };
408
409 void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
410 {
411 s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
412 }
413 #endif /* CONFIG_S3C_DEV_HSMMC1 */
414
415 /* HSMMC2 */
416
417 #ifdef CONFIG_S3C_DEV_HSMMC2
418 static struct resource s3c_hsmmc2_resource[] = {
419 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
420 [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
421 };
422
423 struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
424 .max_width = 4,
425 .host_caps = (MMC_CAP_4_BIT_DATA |
426 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
427 };
428
429 struct platform_device s3c_device_hsmmc2 = {
430 .name = "s3c-sdhci",
431 .id = 2,
432 .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
433 .resource = s3c_hsmmc2_resource,
434 .dev = {
435 .dma_mask = &samsung_device_dma_mask,
436 .coherent_dma_mask = DMA_BIT_MASK(32),
437 .platform_data = &s3c_hsmmc2_def_platdata,
438 },
439 };
440
441 void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
442 {
443 s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
444 }
445 #endif /* CONFIG_S3C_DEV_HSMMC2 */
446
447 #ifdef CONFIG_S3C_DEV_HSMMC3
448 static struct resource s3c_hsmmc3_resource[] = {
449 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
450 [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
451 };
452
453 struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
454 .max_width = 4,
455 .host_caps = (MMC_CAP_4_BIT_DATA |
456 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
457 };
458
459 struct platform_device s3c_device_hsmmc3 = {
460 .name = "s3c-sdhci",
461 .id = 3,
462 .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
463 .resource = s3c_hsmmc3_resource,
464 .dev = {
465 .dma_mask = &samsung_device_dma_mask,
466 .coherent_dma_mask = DMA_BIT_MASK(32),
467 .platform_data = &s3c_hsmmc3_def_platdata,
468 },
469 };
470
471 void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
472 {
473 s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
474 }
475 #endif /* CONFIG_S3C_DEV_HSMMC3 */
476
477 /* I2C */
478
479 static struct resource s3c_i2c0_resource[] = {
480 [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
481 [1] = DEFINE_RES_IRQ(IRQ_IIC),
482 };
483
484 struct platform_device s3c_device_i2c0 = {
485 .name = "s3c2410-i2c",
486 .id = 0,
487 .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
488 .resource = s3c_i2c0_resource,
489 };
490
491 struct s3c2410_platform_i2c default_i2c_data __initdata = {
492 .flags = 0,
493 .slave_addr = 0x10,
494 .frequency = 100*1000,
495 .sda_delay = 100,
496 };
497
498 void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
499 {
500 struct s3c2410_platform_i2c *npd;
501
502 if (!pd) {
503 pd = &default_i2c_data;
504 pd->bus_num = 0;
505 }
506
507 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
508 &s3c_device_i2c0);
509
510 if (!npd->cfg_gpio)
511 npd->cfg_gpio = s3c_i2c0_cfg_gpio;
512 }
513
514 #ifdef CONFIG_S3C_DEV_I2C1
515 static struct resource s3c_i2c1_resource[] = {
516 [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
517 [1] = DEFINE_RES_IRQ(IRQ_IIC1),
518 };
519
520 struct platform_device s3c_device_i2c1 = {
521 .name = "s3c2410-i2c",
522 .id = 1,
523 .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
524 .resource = s3c_i2c1_resource,
525 };
526
527 void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
528 {
529 struct s3c2410_platform_i2c *npd;
530
531 if (!pd) {
532 pd = &default_i2c_data;
533 pd->bus_num = 1;
534 }
535
536 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
537 &s3c_device_i2c1);
538
539 if (!npd->cfg_gpio)
540 npd->cfg_gpio = s3c_i2c1_cfg_gpio;
541 }
542 #endif /* CONFIG_S3C_DEV_I2C1 */
543
544 #ifdef CONFIG_S3C_DEV_I2C2
545 static struct resource s3c_i2c2_resource[] = {
546 [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
547 [1] = DEFINE_RES_IRQ(IRQ_IIC2),
548 };
549
550 struct platform_device s3c_device_i2c2 = {
551 .name = "s3c2410-i2c",
552 .id = 2,
553 .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
554 .resource = s3c_i2c2_resource,
555 };
556
557 void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
558 {
559 struct s3c2410_platform_i2c *npd;
560
561 if (!pd) {
562 pd = &default_i2c_data;
563 pd->bus_num = 2;
564 }
565
566 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
567 &s3c_device_i2c2);
568
569 if (!npd->cfg_gpio)
570 npd->cfg_gpio = s3c_i2c2_cfg_gpio;
571 }
572 #endif /* CONFIG_S3C_DEV_I2C2 */
573
574 #ifdef CONFIG_S3C_DEV_I2C3
575 static struct resource s3c_i2c3_resource[] = {
576 [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
577 [1] = DEFINE_RES_IRQ(IRQ_IIC3),
578 };
579
580 struct platform_device s3c_device_i2c3 = {
581 .name = "s3c2440-i2c",
582 .id = 3,
583 .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
584 .resource = s3c_i2c3_resource,
585 };
586
587 void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
588 {
589 struct s3c2410_platform_i2c *npd;
590
591 if (!pd) {
592 pd = &default_i2c_data;
593 pd->bus_num = 3;
594 }
595
596 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
597 &s3c_device_i2c3);
598
599 if (!npd->cfg_gpio)
600 npd->cfg_gpio = s3c_i2c3_cfg_gpio;
601 }
602 #endif /*CONFIG_S3C_DEV_I2C3 */
603
604 #ifdef CONFIG_S3C_DEV_I2C4
605 static struct resource s3c_i2c4_resource[] = {
606 [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
607 [1] = DEFINE_RES_IRQ(IRQ_IIC4),
608 };
609
610 struct platform_device s3c_device_i2c4 = {
611 .name = "s3c2440-i2c",
612 .id = 4,
613 .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
614 .resource = s3c_i2c4_resource,
615 };
616
617 void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
618 {
619 struct s3c2410_platform_i2c *npd;
620
621 if (!pd) {
622 pd = &default_i2c_data;
623 pd->bus_num = 4;
624 }
625
626 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
627 &s3c_device_i2c4);
628
629 if (!npd->cfg_gpio)
630 npd->cfg_gpio = s3c_i2c4_cfg_gpio;
631 }
632 #endif /*CONFIG_S3C_DEV_I2C4 */
633
634 #ifdef CONFIG_S3C_DEV_I2C5
635 static struct resource s3c_i2c5_resource[] = {
636 [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
637 [1] = DEFINE_RES_IRQ(IRQ_IIC5),
638 };
639
640 struct platform_device s3c_device_i2c5 = {
641 .name = "s3c2440-i2c",
642 .id = 5,
643 .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
644 .resource = s3c_i2c5_resource,
645 };
646
647 void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
648 {
649 struct s3c2410_platform_i2c *npd;
650
651 if (!pd) {
652 pd = &default_i2c_data;
653 pd->bus_num = 5;
654 }
655
656 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
657 &s3c_device_i2c5);
658
659 if (!npd->cfg_gpio)
660 npd->cfg_gpio = s3c_i2c5_cfg_gpio;
661 }
662 #endif /*CONFIG_S3C_DEV_I2C5 */
663
664 #ifdef CONFIG_S3C_DEV_I2C6
665 static struct resource s3c_i2c6_resource[] = {
666 [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
667 [1] = DEFINE_RES_IRQ(IRQ_IIC6),
668 };
669
670 struct platform_device s3c_device_i2c6 = {
671 .name = "s3c2440-i2c",
672 .id = 6,
673 .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
674 .resource = s3c_i2c6_resource,
675 };
676
677 void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
678 {
679 struct s3c2410_platform_i2c *npd;
680
681 if (!pd) {
682 pd = &default_i2c_data;
683 pd->bus_num = 6;
684 }
685
686 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
687 &s3c_device_i2c6);
688
689 if (!npd->cfg_gpio)
690 npd->cfg_gpio = s3c_i2c6_cfg_gpio;
691 }
692 #endif /* CONFIG_S3C_DEV_I2C6 */
693
694 #ifdef CONFIG_S3C_DEV_I2C7
695 static struct resource s3c_i2c7_resource[] = {
696 [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
697 [1] = DEFINE_RES_IRQ(IRQ_IIC7),
698 };
699
700 struct platform_device s3c_device_i2c7 = {
701 .name = "s3c2440-i2c",
702 .id = 7,
703 .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
704 .resource = s3c_i2c7_resource,
705 };
706
707 void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
708 {
709 struct s3c2410_platform_i2c *npd;
710
711 if (!pd) {
712 pd = &default_i2c_data;
713 pd->bus_num = 7;
714 }
715
716 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
717 &s3c_device_i2c7);
718
719 if (!npd->cfg_gpio)
720 npd->cfg_gpio = s3c_i2c7_cfg_gpio;
721 }
722 #endif /* CONFIG_S3C_DEV_I2C7 */
723
724 /* I2C HDMIPHY */
725
726 #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
727 static struct resource s5p_i2c_resource[] = {
728 [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
729 [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
730 };
731
732 struct platform_device s5p_device_i2c_hdmiphy = {
733 .name = "s3c2440-hdmiphy-i2c",
734 .id = -1,
735 .num_resources = ARRAY_SIZE(s5p_i2c_resource),
736 .resource = s5p_i2c_resource,
737 };
738
739 void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
740 {
741 struct s3c2410_platform_i2c *npd;
742
743 if (!pd) {
744 pd = &default_i2c_data;
745
746 if (soc_is_exynos4210() ||
747 soc_is_exynos4212() || soc_is_exynos4412())
748 pd->bus_num = 8;
749 else if (soc_is_s5pv210())
750 pd->bus_num = 3;
751 else
752 pd->bus_num = 0;
753 }
754
755 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
756 &s5p_device_i2c_hdmiphy);
757 }
758
759 static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
760
761 void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
762 struct i2c_board_info *mhl_info, int mhl_bus)
763 {
764 struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
765
766 if (soc_is_exynos4210() ||
767 soc_is_exynos4212() || soc_is_exynos4412())
768 pd->hdmiphy_bus = 8;
769 else if (soc_is_s5pv210())
770 pd->hdmiphy_bus = 3;
771 else
772 pd->hdmiphy_bus = 0;
773
774 pd->hdmiphy_info = hdmiphy_info;
775 pd->mhl_info = mhl_info;
776 pd->mhl_bus = mhl_bus;
777
778 s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
779 &s5p_device_hdmi);
780 }
781
782 #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
783
784 /* I2S */
785
786 #ifdef CONFIG_PLAT_S3C24XX
787 static struct resource s3c_iis_resource[] = {
788 [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
789 };
790
791 struct platform_device s3c_device_iis = {
792 .name = "s3c24xx-iis",
793 .id = -1,
794 .num_resources = ARRAY_SIZE(s3c_iis_resource),
795 .resource = s3c_iis_resource,
796 .dev = {
797 .dma_mask = &samsung_device_dma_mask,
798 .coherent_dma_mask = DMA_BIT_MASK(32),
799 }
800 };
801 #endif /* CONFIG_PLAT_S3C24XX */
802
803 /* IDE CFCON */
804
805 #ifdef CONFIG_SAMSUNG_DEV_IDE
806 static struct resource s3c_cfcon_resource[] = {
807 [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
808 [1] = DEFINE_RES_IRQ(IRQ_CFCON),
809 };
810
811 struct platform_device s3c_device_cfcon = {
812 .id = 0,
813 .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
814 .resource = s3c_cfcon_resource,
815 };
816
817 void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
818 {
819 s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
820 &s3c_device_cfcon);
821 }
822 #endif /* CONFIG_SAMSUNG_DEV_IDE */
823
824 /* KEYPAD */
825
826 #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
827 static struct resource samsung_keypad_resources[] = {
828 [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
829 [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
830 };
831
832 struct platform_device samsung_device_keypad = {
833 .name = "samsung-keypad",
834 .id = -1,
835 .num_resources = ARRAY_SIZE(samsung_keypad_resources),
836 .resource = samsung_keypad_resources,
837 };
838
839 void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
840 {
841 struct samsung_keypad_platdata *npd;
842
843 npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
844 &samsung_device_keypad);
845
846 if (!npd->cfg_gpio)
847 npd->cfg_gpio = samsung_keypad_cfg_gpio;
848 }
849 #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
850
851 /* LCD Controller */
852
853 #ifdef CONFIG_PLAT_S3C24XX
854 static struct resource s3c_lcd_resource[] = {
855 [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
856 [1] = DEFINE_RES_IRQ(IRQ_LCD),
857 };
858
859 struct platform_device s3c_device_lcd = {
860 .name = "s3c2410-lcd",
861 .id = -1,
862 .num_resources = ARRAY_SIZE(s3c_lcd_resource),
863 .resource = s3c_lcd_resource,
864 .dev = {
865 .dma_mask = &samsung_device_dma_mask,
866 .coherent_dma_mask = DMA_BIT_MASK(32),
867 }
868 };
869
870 void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
871 {
872 struct s3c2410fb_mach_info *npd;
873
874 npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
875 if (npd) {
876 npd->displays = kmemdup(pd->displays,
877 sizeof(struct s3c2410fb_display) * npd->num_displays,
878 GFP_KERNEL);
879 if (!npd->displays)
880 printk(KERN_ERR "no memory for LCD display data\n");
881 } else {
882 printk(KERN_ERR "no memory for LCD platform data\n");
883 }
884 }
885 #endif /* CONFIG_PLAT_S3C24XX */
886
887 /* MIPI CSIS */
888
889 #ifdef CONFIG_S5P_DEV_CSIS0
890 static struct resource s5p_mipi_csis0_resource[] = {
891 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
892 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
893 };
894
895 struct platform_device s5p_device_mipi_csis0 = {
896 .name = "s5p-mipi-csis",
897 .id = 0,
898 .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
899 .resource = s5p_mipi_csis0_resource,
900 };
901 #endif /* CONFIG_S5P_DEV_CSIS0 */
902
903 #ifdef CONFIG_S5P_DEV_CSIS1
904 static struct resource s5p_mipi_csis1_resource[] = {
905 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
906 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
907 };
908
909 struct platform_device s5p_device_mipi_csis1 = {
910 .name = "s5p-mipi-csis",
911 .id = 1,
912 .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
913 .resource = s5p_mipi_csis1_resource,
914 };
915 #endif
916
917 /* NAND */
918
919 #ifdef CONFIG_S3C_DEV_NAND
920 static struct resource s3c_nand_resource[] = {
921 [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
922 };
923
924 struct platform_device s3c_device_nand = {
925 .name = "s3c2410-nand",
926 .id = -1,
927 .num_resources = ARRAY_SIZE(s3c_nand_resource),
928 .resource = s3c_nand_resource,
929 };
930
931 /*
932 * s3c_nand_copy_set() - copy nand set data
933 * @set: The new structure, directly copied from the old.
934 *
935 * Copy all the fields from the NAND set field from what is probably __initdata
936 * to new kernel memory. The code returns 0 if the copy happened correctly or
937 * an error code for the calling function to display.
938 *
939 * Note, we currently do not try and look to see if we've already copied the
940 * data in a previous set.
941 */
942 static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
943 {
944 void *ptr;
945 int size;
946
947 size = sizeof(struct mtd_partition) * set->nr_partitions;
948 if (size) {
949 ptr = kmemdup(set->partitions, size, GFP_KERNEL);
950 set->partitions = ptr;
951
952 if (!ptr)
953 return -ENOMEM;
954 }
955
956 if (set->nr_map && set->nr_chips) {
957 size = sizeof(int) * set->nr_chips;
958 ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
959 set->nr_map = ptr;
960
961 if (!ptr)
962 return -ENOMEM;
963 }
964
965 if (set->ecc_layout) {
966 ptr = kmemdup(set->ecc_layout,
967 sizeof(struct nand_ecclayout), GFP_KERNEL);
968 set->ecc_layout = ptr;
969
970 if (!ptr)
971 return -ENOMEM;
972 }
973
974 return 0;
975 }
976
977 void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
978 {
979 struct s3c2410_platform_nand *npd;
980 int size;
981 int ret;
982
983 /* note, if we get a failure in allocation, we simply drop out of the
984 * function. If there is so little memory available at initialisation
985 * time then there is little chance the system is going to run.
986 */
987
988 npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
989 &s3c_device_nand);
990 if (!npd)
991 return;
992
993 /* now see if we need to copy any of the nand set data */
994
995 size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
996 if (size) {
997 struct s3c2410_nand_set *from = npd->sets;
998 struct s3c2410_nand_set *to;
999 int i;
1000
1001 to = kmemdup(from, size, GFP_KERNEL);
1002 npd->sets = to; /* set, even if we failed */
1003
1004 if (!to) {
1005 printk(KERN_ERR "%s: no memory for sets\n", __func__);
1006 return;
1007 }
1008
1009 for (i = 0; i < npd->nr_sets; i++) {
1010 ret = s3c_nand_copy_set(to);
1011 if (ret) {
1012 printk(KERN_ERR "%s: failed to copy set %d\n",
1013 __func__, i);
1014 return;
1015 }
1016 to++;
1017 }
1018 }
1019 }
1020 #endif /* CONFIG_S3C_DEV_NAND */
1021
1022 /* ONENAND */
1023
1024 #ifdef CONFIG_S3C_DEV_ONENAND
1025 static struct resource s3c_onenand_resources[] = {
1026 [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
1027 [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
1028 [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
1029 };
1030
1031 struct platform_device s3c_device_onenand = {
1032 .name = "samsung-onenand",
1033 .id = 0,
1034 .num_resources = ARRAY_SIZE(s3c_onenand_resources),
1035 .resource = s3c_onenand_resources,
1036 };
1037 #endif /* CONFIG_S3C_DEV_ONENAND */
1038
1039 #ifdef CONFIG_S3C64XX_DEV_ONENAND1
1040 static struct resource s3c64xx_onenand1_resources[] = {
1041 [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
1042 [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
1043 [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
1044 };
1045
1046 struct platform_device s3c64xx_device_onenand1 = {
1047 .name = "samsung-onenand",
1048 .id = 1,
1049 .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
1050 .resource = s3c64xx_onenand1_resources,
1051 };
1052
1053 void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
1054 {
1055 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
1056 &s3c64xx_device_onenand1);
1057 }
1058 #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
1059
1060 #ifdef CONFIG_S5P_DEV_ONENAND
1061 static struct resource s5p_onenand_resources[] = {
1062 [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
1063 [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
1064 [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
1065 };
1066
1067 struct platform_device s5p_device_onenand = {
1068 .name = "s5pc110-onenand",
1069 .id = -1,
1070 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
1071 .resource = s5p_onenand_resources,
1072 };
1073 #endif /* CONFIG_S5P_DEV_ONENAND */
1074
1075 /* PMU */
1076
1077 #if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
1078 static struct resource s5p_pmu_resource[] = {
1079 DEFINE_RES_IRQ(IRQ_PMU)
1080 };
1081
1082 static struct platform_device s5p_device_pmu = {
1083 .name = "arm-pmu",
1084 .id = -1,
1085 .num_resources = ARRAY_SIZE(s5p_pmu_resource),
1086 .resource = s5p_pmu_resource,
1087 };
1088
1089 static int __init s5p_pmu_init(void)
1090 {
1091 platform_device_register(&s5p_device_pmu);
1092 return 0;
1093 }
1094 arch_initcall(s5p_pmu_init);
1095 #endif /* CONFIG_PLAT_S5P */
1096
1097 /* PWM Timer */
1098
1099 #ifdef CONFIG_SAMSUNG_DEV_PWM
1100
1101 #define TIMER_RESOURCE_SIZE (1)
1102
1103 #define TIMER_RESOURCE(_tmr, _irq) \
1104 (struct resource [TIMER_RESOURCE_SIZE]) { \
1105 [0] = { \
1106 .start = _irq, \
1107 .end = _irq, \
1108 .flags = IORESOURCE_IRQ \
1109 } \
1110 }
1111
1112 #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
1113 .name = "s3c24xx-pwm", \
1114 .id = _tmr_no, \
1115 .num_resources = TIMER_RESOURCE_SIZE, \
1116 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
1117
1118 /*
1119 * since we already have an static mapping for the timer,
1120 * we do not bother setting any IO resource for the base.
1121 */
1122
1123 struct platform_device s3c_device_timer[] = {
1124 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
1125 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
1126 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
1127 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
1128 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
1129 };
1130 #endif /* CONFIG_SAMSUNG_DEV_PWM */
1131
1132 /* RTC */
1133
1134 #ifdef CONFIG_PLAT_S3C24XX
1135 static struct resource s3c_rtc_resource[] = {
1136 [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
1137 [1] = DEFINE_RES_IRQ(IRQ_RTC),
1138 [2] = DEFINE_RES_IRQ(IRQ_TICK),
1139 };
1140
1141 struct platform_device s3c_device_rtc = {
1142 .name = "s3c2410-rtc",
1143 .id = -1,
1144 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1145 .resource = s3c_rtc_resource,
1146 };
1147 #endif /* CONFIG_PLAT_S3C24XX */
1148
1149 #ifdef CONFIG_S3C_DEV_RTC
1150 static struct resource s3c_rtc_resource[] = {
1151 [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
1152 [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
1153 [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
1154 };
1155
1156 struct platform_device s3c_device_rtc = {
1157 .name = "s3c64xx-rtc",
1158 .id = -1,
1159 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1160 .resource = s3c_rtc_resource,
1161 };
1162 #endif /* CONFIG_S3C_DEV_RTC */
1163
1164 /* SDI */
1165
1166 #ifdef CONFIG_PLAT_S3C24XX
1167 static struct resource s3c_sdi_resource[] = {
1168 [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
1169 [1] = DEFINE_RES_IRQ(IRQ_SDI),
1170 };
1171
1172 struct platform_device s3c_device_sdi = {
1173 .name = "s3c2410-sdi",
1174 .id = -1,
1175 .num_resources = ARRAY_SIZE(s3c_sdi_resource),
1176 .resource = s3c_sdi_resource,
1177 };
1178
1179 void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
1180 {
1181 s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
1182 &s3c_device_sdi);
1183 }
1184 #endif /* CONFIG_PLAT_S3C24XX */
1185
1186 /* SPI */
1187
1188 #ifdef CONFIG_PLAT_S3C24XX
1189 static struct resource s3c_spi0_resource[] = {
1190 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
1191 [1] = DEFINE_RES_IRQ(IRQ_SPI0),
1192 };
1193
1194 struct platform_device s3c_device_spi0 = {
1195 .name = "s3c2410-spi",
1196 .id = 0,
1197 .num_resources = ARRAY_SIZE(s3c_spi0_resource),
1198 .resource = s3c_spi0_resource,
1199 .dev = {
1200 .dma_mask = &samsung_device_dma_mask,
1201 .coherent_dma_mask = DMA_BIT_MASK(32),
1202 }
1203 };
1204
1205 static struct resource s3c_spi1_resource[] = {
1206 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
1207 [1] = DEFINE_RES_IRQ(IRQ_SPI1),
1208 };
1209
1210 struct platform_device s3c_device_spi1 = {
1211 .name = "s3c2410-spi",
1212 .id = 1,
1213 .num_resources = ARRAY_SIZE(s3c_spi1_resource),
1214 .resource = s3c_spi1_resource,
1215 .dev = {
1216 .dma_mask = &samsung_device_dma_mask,
1217 .coherent_dma_mask = DMA_BIT_MASK(32),
1218 }
1219 };
1220 #endif /* CONFIG_PLAT_S3C24XX */
1221
1222 /* Touchscreen */
1223
1224 #ifdef CONFIG_PLAT_S3C24XX
1225 static struct resource s3c_ts_resource[] = {
1226 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
1227 [1] = DEFINE_RES_IRQ(IRQ_TC),
1228 };
1229
1230 struct platform_device s3c_device_ts = {
1231 .name = "s3c2410-ts",
1232 .id = -1,
1233 .dev.parent = &s3c_device_adc.dev,
1234 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1235 .resource = s3c_ts_resource,
1236 };
1237
1238 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
1239 {
1240 s3c_set_platdata(hard_s3c2410ts_info,
1241 sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
1242 }
1243 #endif /* CONFIG_PLAT_S3C24XX */
1244
1245 #ifdef CONFIG_SAMSUNG_DEV_TS
1246 static struct resource s3c_ts_resource[] = {
1247 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
1248 [1] = DEFINE_RES_IRQ(IRQ_TC),
1249 };
1250
1251 static struct s3c2410_ts_mach_info default_ts_data __initdata = {
1252 .delay = 10000,
1253 .presc = 49,
1254 .oversampling_shift = 2,
1255 };
1256
1257 struct platform_device s3c_device_ts = {
1258 .name = "s3c64xx-ts",
1259 .id = -1,
1260 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1261 .resource = s3c_ts_resource,
1262 };
1263
1264 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
1265 {
1266 if (!pd)
1267 pd = &default_ts_data;
1268
1269 s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
1270 &s3c_device_ts);
1271 }
1272 #endif /* CONFIG_SAMSUNG_DEV_TS */
1273
1274 /* TV */
1275
1276 #ifdef CONFIG_S5P_DEV_TV
1277
1278 static struct resource s5p_hdmi_resources[] = {
1279 [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
1280 [1] = DEFINE_RES_IRQ(IRQ_HDMI),
1281 };
1282
1283 struct platform_device s5p_device_hdmi = {
1284 .name = "s5p-hdmi",
1285 .id = -1,
1286 .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
1287 .resource = s5p_hdmi_resources,
1288 };
1289
1290 static struct resource s5p_sdo_resources[] = {
1291 [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
1292 [1] = DEFINE_RES_IRQ(IRQ_SDO),
1293 };
1294
1295 struct platform_device s5p_device_sdo = {
1296 .name = "s5p-sdo",
1297 .id = -1,
1298 .num_resources = ARRAY_SIZE(s5p_sdo_resources),
1299 .resource = s5p_sdo_resources,
1300 };
1301
1302 static struct resource s5p_mixer_resources[] = {
1303 [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
1304 [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
1305 [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
1306 };
1307
1308 struct platform_device s5p_device_mixer = {
1309 .name = "s5p-mixer",
1310 .id = -1,
1311 .num_resources = ARRAY_SIZE(s5p_mixer_resources),
1312 .resource = s5p_mixer_resources,
1313 .dev = {
1314 .dma_mask = &samsung_device_dma_mask,
1315 .coherent_dma_mask = DMA_BIT_MASK(32),
1316 }
1317 };
1318 #endif /* CONFIG_S5P_DEV_TV */
1319
1320 /* USB */
1321
1322 #ifdef CONFIG_S3C_DEV_USB_HOST
1323 static struct resource s3c_usb_resource[] = {
1324 [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
1325 [1] = DEFINE_RES_IRQ(IRQ_USBH),
1326 };
1327
1328 struct platform_device s3c_device_ohci = {
1329 .name = "s3c2410-ohci",
1330 .id = -1,
1331 .num_resources = ARRAY_SIZE(s3c_usb_resource),
1332 .resource = s3c_usb_resource,
1333 .dev = {
1334 .dma_mask = &samsung_device_dma_mask,
1335 .coherent_dma_mask = DMA_BIT_MASK(32),
1336 }
1337 };
1338
1339 /*
1340 * s3c_ohci_set_platdata - initialise OHCI device platform data
1341 * @info: The platform data.
1342 *
1343 * This call copies the @info passed in and sets the device .platform_data
1344 * field to that copy. The @info is copied so that the original can be marked
1345 * __initdata.
1346 */
1347
1348 void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
1349 {
1350 s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
1351 &s3c_device_ohci);
1352 }
1353 #endif /* CONFIG_S3C_DEV_USB_HOST */
1354
1355 /* USB Device (Gadget) */
1356
1357 #ifdef CONFIG_PLAT_S3C24XX
1358 static struct resource s3c_usbgadget_resource[] = {
1359 [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
1360 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1361 };
1362
1363 struct platform_device s3c_device_usbgadget = {
1364 .name = "s3c2410-usbgadget",
1365 .id = -1,
1366 .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
1367 .resource = s3c_usbgadget_resource,
1368 };
1369
1370 void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
1371 {
1372 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
1373 }
1374 #endif /* CONFIG_PLAT_S3C24XX */
1375
1376 /* USB EHCI Host Controller */
1377
1378 #ifdef CONFIG_S5P_DEV_USB_EHCI
1379 static struct resource s5p_ehci_resource[] = {
1380 [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
1381 [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
1382 };
1383
1384 struct platform_device s5p_device_ehci = {
1385 .name = "s5p-ehci",
1386 .id = -1,
1387 .num_resources = ARRAY_SIZE(s5p_ehci_resource),
1388 .resource = s5p_ehci_resource,
1389 .dev = {
1390 .dma_mask = &samsung_device_dma_mask,
1391 .coherent_dma_mask = DMA_BIT_MASK(32),
1392 }
1393 };
1394
1395 void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
1396 {
1397 struct s5p_ehci_platdata *npd;
1398
1399 npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
1400 &s5p_device_ehci);
1401
1402 if (!npd->phy_init)
1403 npd->phy_init = s5p_usb_phy_init;
1404 if (!npd->phy_exit)
1405 npd->phy_exit = s5p_usb_phy_exit;
1406 }
1407 #endif /* CONFIG_S5P_DEV_USB_EHCI */
1408
1409 /* USB HSOTG */
1410
1411 #ifdef CONFIG_S3C_DEV_USB_HSOTG
1412 static struct resource s3c_usb_hsotg_resources[] = {
1413 [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
1414 [1] = DEFINE_RES_IRQ(IRQ_OTG),
1415 };
1416
1417 struct platform_device s3c_device_usb_hsotg = {
1418 .name = "s3c-hsotg",
1419 .id = -1,
1420 .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
1421 .resource = s3c_usb_hsotg_resources,
1422 .dev = {
1423 .dma_mask = &samsung_device_dma_mask,
1424 .coherent_dma_mask = DMA_BIT_MASK(32),
1425 },
1426 };
1427
1428 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
1429 {
1430 struct s3c_hsotg_plat *npd;
1431
1432 npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
1433 &s3c_device_usb_hsotg);
1434
1435 if (!npd->phy_init)
1436 npd->phy_init = s5p_usb_phy_init;
1437 if (!npd->phy_exit)
1438 npd->phy_exit = s5p_usb_phy_exit;
1439 }
1440 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
1441
1442 /* USB High Spped 2.0 Device (Gadget) */
1443
1444 #ifdef CONFIG_PLAT_S3C24XX
1445 static struct resource s3c_hsudc_resource[] = {
1446 [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
1447 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1448 };
1449
1450 struct platform_device s3c_device_usb_hsudc = {
1451 .name = "s3c-hsudc",
1452 .id = -1,
1453 .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
1454 .resource = s3c_hsudc_resource,
1455 .dev = {
1456 .dma_mask = &samsung_device_dma_mask,
1457 .coherent_dma_mask = DMA_BIT_MASK(32),
1458 },
1459 };
1460
1461 void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
1462 {
1463 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
1464 }
1465 #endif /* CONFIG_PLAT_S3C24XX */
1466
1467 /* WDT */
1468
1469 #ifdef CONFIG_S3C_DEV_WDT
1470 static struct resource s3c_wdt_resource[] = {
1471 [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
1472 [1] = DEFINE_RES_IRQ(IRQ_WDT),
1473 };
1474
1475 struct platform_device s3c_device_wdt = {
1476 .name = "s3c2410-wdt",
1477 .id = -1,
1478 .num_resources = ARRAY_SIZE(s3c_wdt_resource),
1479 .resource = s3c_wdt_resource,
1480 };
1481 #endif /* CONFIG_S3C_DEV_WDT */
1482
1483 #ifdef CONFIG_S3C64XX_DEV_SPI0
1484 static struct resource s3c64xx_spi0_resource[] = {
1485 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1486 [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
1487 [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
1488 [3] = DEFINE_RES_IRQ(IRQ_SPI0),
1489 };
1490
1491 struct platform_device s3c64xx_device_spi0 = {
1492 .name = "s3c6410-spi",
1493 .id = 0,
1494 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1495 .resource = s3c64xx_spi0_resource,
1496 .dev = {
1497 .dma_mask = &samsung_device_dma_mask,
1498 .coherent_dma_mask = DMA_BIT_MASK(32),
1499 },
1500 };
1501
1502 void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1503 int num_cs)
1504 {
1505 struct s3c64xx_spi_info pd;
1506
1507 /* Reject invalid configuration */
1508 if (!num_cs || src_clk_nr < 0) {
1509 pr_err("%s: Invalid SPI configuration\n", __func__);
1510 return;
1511 }
1512
1513 pd.num_cs = num_cs;
1514 pd.src_clk_nr = src_clk_nr;
1515 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
1516 #ifdef CONFIG_PL330_DMA
1517 pd.filter = pl330_filter;
1518 #endif
1519
1520 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
1521 }
1522 #endif /* CONFIG_S3C64XX_DEV_SPI0 */
1523
1524 #ifdef CONFIG_S3C64XX_DEV_SPI1
1525 static struct resource s3c64xx_spi1_resource[] = {
1526 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1527 [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
1528 [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
1529 [3] = DEFINE_RES_IRQ(IRQ_SPI1),
1530 };
1531
1532 struct platform_device s3c64xx_device_spi1 = {
1533 .name = "s3c6410-spi",
1534 .id = 1,
1535 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1536 .resource = s3c64xx_spi1_resource,
1537 .dev = {
1538 .dma_mask = &samsung_device_dma_mask,
1539 .coherent_dma_mask = DMA_BIT_MASK(32),
1540 },
1541 };
1542
1543 void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1544 int num_cs)
1545 {
1546 struct s3c64xx_spi_info pd;
1547
1548 /* Reject invalid configuration */
1549 if (!num_cs || src_clk_nr < 0) {
1550 pr_err("%s: Invalid SPI configuration\n", __func__);
1551 return;
1552 }
1553
1554 pd.num_cs = num_cs;
1555 pd.src_clk_nr = src_clk_nr;
1556 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
1557 #ifdef CONFIG_PL330_DMA
1558 pd.filter = pl330_filter;
1559 #endif
1560
1561 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
1562 }
1563 #endif /* CONFIG_S3C64XX_DEV_SPI1 */
1564
1565 #ifdef CONFIG_S3C64XX_DEV_SPI2
1566 static struct resource s3c64xx_spi2_resource[] = {
1567 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
1568 [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
1569 [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
1570 [3] = DEFINE_RES_IRQ(IRQ_SPI2),
1571 };
1572
1573 struct platform_device s3c64xx_device_spi2 = {
1574 .name = "s3c6410-spi",
1575 .id = 2,
1576 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1577 .resource = s3c64xx_spi2_resource,
1578 .dev = {
1579 .dma_mask = &samsung_device_dma_mask,
1580 .coherent_dma_mask = DMA_BIT_MASK(32),
1581 },
1582 };
1583
1584 void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1585 int num_cs)
1586 {
1587 struct s3c64xx_spi_info pd;
1588
1589 /* Reject invalid configuration */
1590 if (!num_cs || src_clk_nr < 0) {
1591 pr_err("%s: Invalid SPI configuration\n", __func__);
1592 return;
1593 }
1594
1595 pd.num_cs = num_cs;
1596 pd.src_clk_nr = src_clk_nr;
1597 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
1598 #ifdef CONFIG_PL330_DMA
1599 pd.filter = pl330_filter;
1600 #endif
1601
1602 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
1603 }
1604 #endif /* CONFIG_S3C64XX_DEV_SPI2 */
kernel source for telekom puls (alcatel/mediatek)