arch/arm/mm/proc-v7-3level.S

   1 /*
   2  * arch/arm/mm/proc-v7-3level.S
   3  *
   4  * Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  * Copyright (C) 2011 ARM Ltd.
   6  * Author: Catalin Marinas <catalin.marinas@arm.com>
   7  *   based on arch/arm/mm/proc-v7-2level.S
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22
  23 #define TTB_IRGN_NC     (0 << 8)
  24 #define TTB_IRGN_WBWA   (1 << 8)
  25 #define TTB_IRGN_WT     (2 << 8)
  26 #define TTB_IRGN_WB     (3 << 8)
  27 #define TTB_RGN_NC      (0 << 10)
  28 #define TTB_RGN_OC_WBWA (1 << 10)
  29 #define TTB_RGN_OC_WT   (2 << 10)
  30 #define TTB_RGN_OC_WB   (3 << 10)
  31 #define TTB_S           (3 << 12)
  32 #define TTB_EAE         (1 << 31)
  33
  34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
  35 #define TTB_FLAGS_UP    (TTB_IRGN_WB|TTB_RGN_OC_WB)
  36 #define PMD_FLAGS_UP    (PMD_SECT_WB)
  37
  38 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
  39 #define TTB_FLAGS_SMP   (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
  40 #define PMD_FLAGS_SMP   (PMD_SECT_WBWA|PMD_SECT_S)
  41
  42 /*
  43  * cpu_v7_switch_mm(pgd_phys, tsk)
  44  *
  45  * Set the translation table base pointer to be pgd_phys (physical address of
  46  * the new TTB).
  47  */
  48 ENTRY(cpu_v7_switch_mm)
  49 #ifdef CONFIG_MMU
  50         mmid    r1, r1                          @ get mm->context.id
  51         asid    r3, r1
  52         mov     r3, r3, lsl #(48 - 32)          @ ASID
  53         mcrr    p15, 0, r0, r3, c2              @ set TTB 0
  54         isb
  55 #endif
  56         mov     pc, lr
  57 ENDPROC(cpu_v7_switch_mm)
  58
  59 #ifdef __ARMEB__
  60 #define rl r3
  61 #define rh r2
  62 #else
  63 #define rl r2
  64 #define rh r3
  65 #endif
  66
  67 /*
  68  * cpu_v7_set_pte_ext(ptep, pte)
  69  *
  70  * Set a level 2 translation table entry.
  71  * - ptep - pointer to level 3 translation table entry
  72  * - pte - PTE value to store (64-bit in r2 and r3)
  73  */
  74 ENTRY(cpu_v7_set_pte_ext)
  75 #ifdef CONFIG_MMU
  76         tst     rl, #L_PTE_VALID
  77         beq     1f
  78         tst     rh, #1 << (57 - 32)             @ L_PTE_NONE
  79         bicne   rl, #L_PTE_VALID
  80         bne     1f
  81
  82         eor     ip, rh, #1 << (55 - 32) @ toggle L_PTE_DIRTY in temp reg to
  83                                         @ test for !L_PTE_DIRTY || L_PTE_RDONLY
  84         tst     ip, #1 << (55 - 32) | 1 << (58 - 32)
  85         orrne   rl, #PTE_AP2
  86         biceq   rl, #PTE_AP2
  87
  88 1:      strd    r2, r3, [r0]
  89         ALT_SMP(W(nop))
  90 #ifdef CONFIG_ARM_ERRATA_824069
  91         ALT_UP (mcr     p15, 0, r0, c7, c14, 1)         @ flush_pte
  92 #else
  93         ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
  94 #endif
  95 #endif
  96         mov     pc, lr
  97 ENDPROC(cpu_v7_set_pte_ext)
  98
  99         /*
 100          * Memory region attributes for LPAE (defined in pgtable-3level.h):
 101          *
 102          *   n = AttrIndx[2:0]
 103          *
 104          *                      n       MAIR
 105          *   UNCACHED           000     00000000
 106          *   BUFFERABLE         001     01000100
 107          *   DEV_WC             001     01000100
 108          *   WRITETHROUGH       010     10101010
 109          *   WRITEBACK          011     11101110
 110          *   DEV_CACHED         011     11101110
 111          *   DEV_SHARED         100     00000100
 112          *   DEV_NONSHARED      100     00000100
 113          *   unused             101
 114          *   unused             110
 115          *   WRITEALLOC         111     11111111
 116          */
 117 .equ    PRRR,   0xeeaa4400                      @ MAIR0
 118 .equ    NMRR,   0xff000004                      @ MAIR1
 119
 120         /*
 121          * Macro for setting up the TTBRx and TTBCR registers.
 122          * - \ttbr1 updated.
 123          */
 124         .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
 125         ldr     \tmp, =swapper_pg_dir           @ swapper_pg_dir virtual address
 126         cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET? (branch below)
 127         mrc     p15, 0, \tmp, c2, c0, 2         @ TTB control register
 128         orr     \tmp, \tmp, #TTB_EAE
 129         ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP)
 130         ALT_UP(orr      \tmp, \tmp, #TTB_FLAGS_UP)
 131         ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP << 16)
 132         ALT_UP(orr      \tmp, \tmp, #TTB_FLAGS_UP << 16)
 133         /*
 134          * TTBR0/TTBR1 split (PAGE_OFFSET):
 135          *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
 136          *   0x80000000: T0SZ = 0, T1SZ = 1
 137          *   0xc0000000: T0SZ = 0, T1SZ = 2
 138          *
 139          * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
 140          * booting secondary CPUs would end up using TTBR1 for the identity
 141          * mapping set up in TTBR0.
 142          */
 143         bhi     9001f                           @ PHYS_OFFSET > PAGE_OFFSET?
 144         orr     \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
 145 #if defined CONFIG_VMSPLIT_2G
 146         /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
 147         add     \ttbr1, \ttbr1, #1 << 4         @ skip two L1 entries
 148 #elif defined CONFIG_VMSPLIT_3G
 149         /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
 150         add     \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd
 151 #endif
 152         /* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
 153 9001:   mcr     p15, 0, \tmp, c2, c0, 2         @ TTB control register
 154         mcrr    p15, 1, \ttbr1, \zero, c2       @ load TTBR1
 155         .endm
 156
 157         __CPUINIT
 158
 159         /*
 160          *   AT
 161          *  TFR   EV X F   IHD LR    S
 162          * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
 163          * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
 164          *   11    0 110    1  0011 1100 .111 1101 < we want
 165          */
 166         .align  2
 167         .type   v7_crval, #object
 168 v7_crval:
 169         crval   clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
 170
 171         .previous