arch/arm/mm/proc-v7-2level.S

   1 /*
   2  * arch/arm/mm/proc-v7-2level.S
   3  *
   4  * Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define TTB_S           (1 << 1)
  12 #define TTB_RGN_NC      (0 << 3)
  13 #define TTB_RGN_OC_WBWA (1 << 3)
  14 #define TTB_RGN_OC_WT   (2 << 3)
  15 #define TTB_RGN_OC_WB   (3 << 3)
  16 #define TTB_NOS         (1 << 5)
  17 #define TTB_IRGN_NC     ((0 << 0) | (0 << 6))
  18 #define TTB_IRGN_WBWA   ((0 << 0) | (1 << 6))
  19 #define TTB_IRGN_WT     ((1 << 0) | (0 << 6))
  20 #define TTB_IRGN_WB     ((1 << 0) | (1 << 6))
  21
  22 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
  23 #define TTB_FLAGS_UP    TTB_IRGN_WB|TTB_RGN_OC_WB
  24 #define PMD_FLAGS_UP    PMD_SECT_WB
  25
  26 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
  27 #define TTB_FLAGS_SMP   TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
  28 #define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
  29
  30 /*
  31  *      cpu_v7_switch_mm(pgd_phys, tsk)
  32  *
  33  *      Set the translation table base pointer to be pgd_phys
  34  *
  35  *      - pgd_phys - physical address of new TTB
  36  *
  37  *      It is assumed that:
  38  *      - we are not using split page tables
  39  */
  40 ENTRY(cpu_v7_switch_mm)
  41 #ifdef CONFIG_MMU
  42         mov     r2, #0
  43         mmid    r1, r1                          @ get mm->context.id
  44         ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
  45         ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
  46 #ifdef CONFIG_ARM_ERRATA_430973
  47         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
  48 #endif
  49 #ifdef CONFIG_PID_IN_CONTEXTIDR
  50         mrc     p15, 0, r2, c13, c0, 1          @ read current context ID
  51         lsr     r2, r2, #8                      @ extract the PID
  52         bfi     r1, r2, #8, #24                 @ insert into new context ID
  53 #endif
  54 #ifdef CONFIG_ARM_ERRATA_754322
  55         dsb
  56 #endif
  57         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
  58         isb
  59         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
  60         isb
  61 #endif
  62         mov     pc, lr
  63 ENDPROC(cpu_v7_switch_mm)
  64
  65 /*
  66  *      cpu_v7_set_pte_ext(ptep, pte)
  67  *
  68  *      Set a level 2 translation table entry.
  69  *
  70  *      - ptep  - pointer to level 2 translation table entry
  71  *                (hardware version is stored at +2048 bytes)
  72  *      - pte   - PTE value to store
  73  *      - ext   - value for extended PTE bits
  74  */
  75 ENTRY(cpu_v7_set_pte_ext)
  76 #ifdef CONFIG_MMU
  77         str     r1, [r0]                        @ linux version
  78
  79         bic     r3, r1, #0x000003f0
  80         bic     r3, r3, #PTE_TYPE_MASK
  81         orr     r3, r3, r2
  82         orr     r3, r3, #PTE_EXT_AP0 | 2
  83
  84         tst     r1, #1 << 4
  85         orrne   r3, r3, #PTE_EXT_TEX(1)
  86
  87         eor     r1, r1, #L_PTE_DIRTY
  88         tst     r1, #L_PTE_RDONLY | L_PTE_DIRTY
  89         orrne   r3, r3, #PTE_EXT_APX
  90
  91         tst     r1, #L_PTE_USER
  92         orrne   r3, r3, #PTE_EXT_AP1
  93 #ifdef CONFIG_CPU_USE_DOMAINS
  94         @ allow kernel read/write access to read-only user pages
  95         tstne   r3, #PTE_EXT_APX
  96         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
  97 #endif
  98
  99         tst     r1, #L_PTE_XN
 100         orrne   r3, r3, #PTE_EXT_XN
 101
 102         tst     r1, #L_PTE_YOUNG
 103         tstne   r1, #L_PTE_VALID
 104 #ifndef CONFIG_CPU_USE_DOMAINS
 105         eorne   r1, r1, #L_PTE_NONE
 106         tstne   r1, #L_PTE_NONE
 107 #endif
 108         moveq   r3, #0
 109
 110  ARM(   str     r3, [r0, #2048]! )
 111  THUMB( add     r0, r0, #2048 )
 112  THUMB( str     r3, [r0] )
 113         ALT_SMP(mov     pc,lr)
 114         ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
 115 #endif
 116         mov     pc, lr
 117 ENDPROC(cpu_v7_set_pte_ext)
 118
 119         /*
 120          * Memory region attributes with SCTLR.TRE=1
 121          *
 122          *   n = TEX[0],C,B
 123          *   TR = PRRR[2n+1:2n]         - memory type
 124          *   IR = NMRR[2n+1:2n]         - inner cacheable property
 125          *   OR = NMRR[2n+17:2n+16]     - outer cacheable property
 126          *
 127          *                      n       TR      IR      OR
 128          *   UNCACHED           000     00
 129          *   BUFFERABLE         001     10      00      00
 130          *   WRITETHROUGH       010     10      10      10
 131          *   WRITEBACK          011     10      11      11
 132          *   reserved           110
 133          *   WRITEALLOC         111     10      01      01
 134          *   DEV_SHARED         100     01
 135          *   DEV_NONSHARED      100     01
 136          *   DEV_WC             001     10
 137          *   DEV_CACHED         011     10
 138          *
 139          * Other attributes:
 140          *
 141          *   DS0 = PRRR[16] = 0         - device shareable property
 142          *   DS1 = PRRR[17] = 1         - device shareable property
 143          *   NS0 = PRRR[18] = 0         - normal shareable property
 144          *   NS1 = PRRR[19] = 1         - normal shareable property
 145          *   NOS = PRRR[24+n] = 1       - not outer shareable
 146          */
 147 .equ    PRRR,   0xff0a81a8
 148 .equ    NMRR,   0x40e040e0
 149
 150         /*
 151          * Macro for setting up the TTBRx and TTBCR registers.
 152          * - \ttb0 and \ttb1 updated with the corresponding flags.
 153          */
 154         .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
 155         mcr     p15, 0, \zero, c2, c0, 2        @ TTB control register
 156         ALT_SMP(orr     \ttbr0, \ttbr0, #TTB_FLAGS_SMP)
 157         ALT_UP(orr      \ttbr0, \ttbr0, #TTB_FLAGS_UP)
 158         ALT_SMP(orr     \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
 159         ALT_UP(orr      \ttbr1, \ttbr1, #TTB_FLAGS_UP)
 160         mcr     p15, 0, \ttbr1, c2, c0, 1       @ load TTB1
 161         .endm
 162
 163         __CPUINIT
 164
 165         /*   AT
 166          *  TFR   EV X F   I D LR    S
 167          * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
 168          * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
 169          *   01    0 110       0011 1100 .111 1101 < we want
 170          */
 171         .align  2
 172         .type   v7_crval, #object
 173 v7_crval:
 174         crval   clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
 175
 176         .previous