arch/arm/mm/proc-v6.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v6.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *  Modified by Catalin Marinas for noMMU support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  This is the "shell" of the ARMv6 processor support.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/linkage.h>
  15 #include <asm/assembler.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/hwcap.h>
  18 #include <asm/pgtable-hwdef.h>
  19 #include <asm/pgtable.h>
  20
  21 #include "proc-macros.S"
  22
  23 #define D_CACHE_LINE_SIZE       32
  24
  25 #define TTB_C           (1 << 0)
  26 #define TTB_S           (1 << 1)
  27 #define TTB_IMP         (1 << 2)
  28 #define TTB_RGN_NC      (0 << 3)
  29 #define TTB_RGN_WBWA    (1 << 3)
  30 #define TTB_RGN_WT      (2 << 3)
  31 #define TTB_RGN_WB      (3 << 3)
  32
  33 #define TTB_FLAGS_UP    TTB_RGN_WBWA
  34 #define PMD_FLAGS_UP    PMD_SECT_WB
  35 #define TTB_FLAGS_SMP   TTB_RGN_WBWA|TTB_S
  36 #define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
  37
  38 ENTRY(cpu_v6_proc_init)
  39         mov     pc, lr
  40
  41 ENTRY(cpu_v6_proc_fin)
  42         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  43         bic     r0, r0, #0x1000                 @ ...i............
  44         bic     r0, r0, #0x0006                 @ .............ca.
  45         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  46         mov     pc, lr
  47
  48 /*
  49  *      cpu_v6_reset(loc)
  50  *
  51  *      Perform a soft reset of the system.  Put the CPU into the
  52  *      same state as it would be if it had been reset, and branch
  53  *      to what would be the reset vector.
  54  *
  55  *      - loc   - location to jump to for soft reset
  56  */
  57         .align  5
  58 ENTRY(cpu_v6_reset)
  59         mov     pc, r0
  60
  61 /*
  62  *      cpu_v6_do_idle()
  63  *
  64  *      Idle the processor (eg, wait for interrupt).
  65  *
  66  *      IRQs are already disabled.
  67  */
  68 ENTRY(cpu_v6_do_idle)
  69         mov     r1, #0
  70         mcr     p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
  71         mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
  72         mov     pc, lr
  73
  74 ENTRY(cpu_v6_dcache_clean_area)
  75 #ifndef TLB_CAN_READ_FROM_L1_CACHE
  76 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  77         add     r0, r0, #D_CACHE_LINE_SIZE
  78         subs    r1, r1, #D_CACHE_LINE_SIZE
  79         bhi     1b
  80 #endif
  81         mov     pc, lr
  82
  83 /*
  84  *      cpu_arm926_switch_mm(pgd_phys, tsk)
  85  *
  86  *      Set the translation table base pointer to be pgd_phys
  87  *
  88  *      - pgd_phys - physical address of new TTB
  89  *
  90  *      It is assumed that:
  91  *      - we are not using split page tables
  92  */
  93 ENTRY(cpu_v6_switch_mm)
  94 #ifdef CONFIG_MMU
  95         mov     r2, #0
  96         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
  97         ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
  98         ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
  99         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 100         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
 101         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
 102         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
 103 #endif
 104         mov     pc, lr
 105
 106 /*
 107  *      cpu_v6_set_pte_ext(ptep, pte, ext)
 108  *
 109  *      Set a level 2 translation table entry.
 110  *
 111  *      - ptep  - pointer to level 2 translation table entry
 112  *                (hardware version is stored at -1024 bytes)
 113  *      - pte   - PTE value to store
 114  *      - ext   - value for extended PTE bits
 115  */
 116         armv6_mt_table cpu_v6
 117
 118 ENTRY(cpu_v6_set_pte_ext)
 119 #ifdef CONFIG_MMU
 120         armv6_set_pte_ext cpu_v6
 121 #endif
 122         mov     pc, lr
 123
 124 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
 125 .globl  cpu_v6_suspend_size
 126 .equ    cpu_v6_suspend_size, 4 * 8
 127 #ifdef CONFIG_PM
 128 ENTRY(cpu_v6_do_suspend)
 129         stmfd   sp!, {r4 - r11, lr}
 130         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 131         mrc     p15, 0, r5, c13, c0, 1  @ Context ID
 132         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
 133         mrc     p15, 0, r7, c2, c0, 0   @ Translation table base 0
 134         mrc     p15, 0, r8, c2, c0, 1   @ Translation table base 1
 135         mrc     p15, 0, r9, c1, c0, 1   @ auxiliary control register
 136         mrc     p15, 0, r10, c1, c0, 2  @ co-processor access control
 137         mrc     p15, 0, r11, c1, c0, 0  @ control register
 138         stmia   r0, {r4 - r11}
 139         ldmfd   sp!, {r4- r11, pc}
 140 ENDPROC(cpu_v6_do_suspend)
 141
 142 ENTRY(cpu_v6_do_resume)
 143         mov     ip, #0
 144         mcr     p15, 0, ip, c7, c14, 0  @ clean+invalidate D cache
 145         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 146         mcr     p15, 0, ip, c7, c15, 0  @ clean+invalidate cache
 147         mcr     p15, 0, ip, c7, c10, 4  @ drain write buffer
 148         ldmia   r0, {r4 - r11}
 149         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 150         mcr     p15, 0, r5, c13, c0, 1  @ Context ID
 151         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 152         mcr     p15, 0, r7, c2, c0, 0   @ Translation table base 0
 153         mcr     p15, 0, r8, c2, c0, 1   @ Translation table base 1
 154         mcr     p15, 0, r9, c1, c0, 1   @ auxiliary control register
 155         mcr     p15, 0, r10, c1, c0, 2  @ co-processor access control
 156         mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
 157         mcr     p15, 0, ip, c7, c5, 4   @ ISB
 158         mov     r0, r11                 @ control register
 159         mov     r2, r7, lsr #14         @ get TTB0 base
 160         mov     r2, r2, lsl #14
 161         ldr     r3, cpu_resume_l1_flags
 162         b       cpu_resume_mmu
 163 ENDPROC(cpu_v6_do_resume)
 164 cpu_resume_l1_flags:
 165         ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
 166         ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
 167 #else
 168 #define cpu_v6_do_suspend 0
 169 #define cpu_v6_do_resume 0
 170 #endif
 171
 172
 173         .type   cpu_v6_name, #object
 174 cpu_v6_name:
 175         .asciz  "ARMv6-compatible processor"
 176         .size   cpu_v6_name, . - cpu_v6_name
 177
 178         .type   cpu_pj4_name, #object
 179 cpu_pj4_name:
 180         .asciz  "Marvell PJ4 processor"
 181         .size   cpu_pj4_name, . - cpu_pj4_name
 182
 183         .align
 184
 185         __CPUINIT
 186
 187 /*
 188  *      __v6_setup
 189  *
 190  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 191  *      on.  Return in r0 the new CP15 C1 control register setting.
 192  *
 193  *      We automatically detect if we have a Harvard cache, and use the
 194  *      Harvard cache control instructions insead of the unified cache
 195  *      control instructions.
 196  *
 197  *      This should be able to cover all ARMv6 cores.
 198  *
 199  *      It is assumed that:
 200  *      - cache type register is implemented
 201  */
 202 __v6_setup:
 203 #ifdef CONFIG_SMP
 204         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)  @ Enable SMP/nAMP mode
 205         ALT_UP(nop)
 206         orr     r0, r0, #0x20
 207         ALT_SMP(mcr     p15, 0, r0, c1, c0, 1)
 208         ALT_UP(nop)
 209 #endif
 210
 211         mov     r0, #0
 212         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
 213         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 214         mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
 215         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 216 #ifdef CONFIG_MMU
 217         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
 218         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
 219         ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
 220         ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
 221         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 222 #endif /* CONFIG_MMU */
 223         adr     r5, v6_crval
 224         ldmia   r5, {r5, r6}
 225 #ifdef CONFIG_CPU_ENDIAN_BE8
 226         orr     r6, r6, #1 << 25                @ big-endian page tables
 227 #endif
 228         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 229         bic     r0, r0, r5                      @ clear bits them
 230         orr     r0, r0, r6                      @ set them
 231         mov     pc, lr                          @ return to head.S:__ret
 232
 233         /*
 234          *         V X F   I D LR
 235          * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
 236          * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
 237          *         0 110       0011 1.00 .111 1101 < we want
 238          */
 239         .type   v6_crval, #object
 240 v6_crval:
 241         crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
 242
 243         __INITDATA
 244
 245         .type   v6_processor_functions, #object
 246 ENTRY(v6_processor_functions)
 247         .word   v6_early_abort
 248         .word   v6_pabort
 249         .word   cpu_v6_proc_init
 250         .word   cpu_v6_proc_fin
 251         .word   cpu_v6_reset
 252         .word   cpu_v6_do_idle
 253         .word   cpu_v6_dcache_clean_area
 254         .word   cpu_v6_switch_mm
 255         .word   cpu_v6_set_pte_ext
 256         .word   cpu_v6_suspend_size
 257         .word   cpu_v6_do_suspend
 258         .word   cpu_v6_do_resume
 259         .size   v6_processor_functions, . - v6_processor_functions
 260
 261         .section ".rodata"
 262
 263         .type   cpu_arch_name, #object
 264 cpu_arch_name:
 265         .asciz  "armv6"
 266         .size   cpu_arch_name, . - cpu_arch_name
 267
 268         .type   cpu_elf_name, #object
 269 cpu_elf_name:
 270         .asciz  "v6"
 271         .size   cpu_elf_name, . - cpu_elf_name
 272         .align
 273
 274         .section ".proc.info.init", #alloc, #execinstr
 275
 276         /*
 277          * Match any ARMv6 processor core.
 278          */
 279         .type   __v6_proc_info, #object
 280 __v6_proc_info:
 281         .long   0x0007b000
 282         .long   0x0007f000
 283         ALT_SMP(.long \
 284                 PMD_TYPE_SECT | \
 285                 PMD_SECT_AP_WRITE | \
 286                 PMD_SECT_AP_READ | \
 287                 PMD_FLAGS_SMP)
 288         ALT_UP(.long \
 289                 PMD_TYPE_SECT | \
 290                 PMD_SECT_AP_WRITE | \
 291                 PMD_SECT_AP_READ | \
 292                 PMD_FLAGS_UP)
 293         .long   PMD_TYPE_SECT | \
 294                 PMD_SECT_XN | \
 295                 PMD_SECT_AP_WRITE | \
 296                 PMD_SECT_AP_READ
 297         b       __v6_setup
 298         .long   cpu_arch_name
 299         .long   cpu_elf_name
 300         /* See also feat_v6_fixup() for HWCAP_TLS */
 301         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
 302         .long   cpu_v6_name
 303         .long   v6_processor_functions
 304         .long   v6wbi_tlb_fns
 305         .long   v6_user_fns
 306         .long   v6_cache_fns
 307         .size   __v6_proc_info, . - __v6_proc_info
 308
 309         .type   __pj4_v6_proc_info, #object
 310 __pj4_v6_proc_info:
 311         .long   0x560f5810
 312         .long   0xff0ffff0
 313         ALT_SMP(.long \
 314                 PMD_TYPE_SECT | \
 315                 PMD_SECT_AP_WRITE | \
 316                 PMD_SECT_AP_READ | \
 317                 PMD_FLAGS_SMP)
 318         ALT_UP(.long \
 319                 PMD_TYPE_SECT | \
 320                 PMD_SECT_AP_WRITE | \
 321                 PMD_SECT_AP_READ | \
 322                 PMD_FLAGS_UP)
 323         .long   PMD_TYPE_SECT | \
 324                 PMD_SECT_XN | \
 325                 PMD_SECT_AP_WRITE | \
 326                 PMD_SECT_AP_READ
 327         b       __v6_setup
 328         .long   cpu_arch_name
 329         .long   cpu_elf_name
 330         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
 331         .long   cpu_pj4_name
 332         .long   v6_processor_functions
 333         .long   v6wbi_tlb_fns
 334         .long   v6_user_fns
 335         .long   v6_cache_fns
 336         .size   __pj4_v6_proc_info, . - __pj4_v6_proc_info