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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / mmu.c
1 /*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
17 #include <linux/fs.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
20
21 #include <asm/cp15.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/setup.h>
26 #include <asm/smp_plat.h>
27 #include <asm/tlb.h>
28 #include <asm/highmem.h>
29 #include <asm/system_info.h>
30 #include <asm/traps.h>
31
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/pci.h>
35
36 #include "mm.h"
37 #include "tcm.h"
38
39 /*
40 * empty_zero_page is a special page that is used for
41 * zero-initialized data and COW.
42 */
43 struct page *empty_zero_page;
44 EXPORT_SYMBOL(empty_zero_page);
45
46 /*
47 * The pmd table for the upper-most set of pages.
48 */
49 pmd_t *top_pmd;
50
51 #define CPOLICY_UNCACHED 0
52 #define CPOLICY_BUFFERED 1
53 #define CPOLICY_WRITETHROUGH 2
54 #define CPOLICY_WRITEBACK 3
55 #define CPOLICY_WRITEALLOC 4
56
57 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
58 static unsigned int ecc_mask __initdata = 0;
59 pgprot_t pgprot_user;
60 pgprot_t pgprot_kernel;
61 pgprot_t pgprot_hyp_device;
62 pgprot_t pgprot_s2;
63 pgprot_t pgprot_s2_device;
64
65 EXPORT_SYMBOL(pgprot_user);
66 EXPORT_SYMBOL(pgprot_kernel);
67
68 struct cachepolicy {
69 const char policy[16];
70 unsigned int cr_mask;
71 pmdval_t pmd;
72 pteval_t pte;
73 pteval_t pte_s2;
74 };
75
76 #ifdef CONFIG_ARM_LPAE
77 #define s2_policy(policy) policy
78 #else
79 #define s2_policy(policy) 0
80 #endif
81
82 static struct cachepolicy cache_policies[] __initdata = {
83 {
84 .policy = "uncached",
85 .cr_mask = CR_W|CR_C,
86 .pmd = PMD_SECT_UNCACHED,
87 .pte = L_PTE_MT_UNCACHED,
88 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
89 }, {
90 .policy = "buffered",
91 .cr_mask = CR_C,
92 .pmd = PMD_SECT_BUFFERED,
93 .pte = L_PTE_MT_BUFFERABLE,
94 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
95 }, {
96 .policy = "writethrough",
97 .cr_mask = 0,
98 .pmd = PMD_SECT_WT,
99 .pte = L_PTE_MT_WRITETHROUGH,
100 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
101 }, {
102 .policy = "writeback",
103 .cr_mask = 0,
104 .pmd = PMD_SECT_WB,
105 .pte = L_PTE_MT_WRITEBACK,
106 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
107 }, {
108 .policy = "writealloc",
109 .cr_mask = 0,
110 .pmd = PMD_SECT_WBWA,
111 .pte = L_PTE_MT_WRITEALLOC,
112 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
113 }
114 };
115
116 #ifdef CONFIG_CPU_CP15
117 /*
118 * These are useful for identifying cache coherency
119 * problems by allowing the cache or the cache and
120 * writebuffer to be turned off. (Note: the write
121 * buffer should not be on and the cache off).
122 */
123 static int __init early_cachepolicy(char *p)
124 {
125 int i;
126
127 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
128 int len = strlen(cache_policies[i].policy);
129
130 if (memcmp(p, cache_policies[i].policy, len) == 0) {
131 cachepolicy = i;
132 cr_alignment &= ~cache_policies[i].cr_mask;
133 cr_no_alignment &= ~cache_policies[i].cr_mask;
134 break;
135 }
136 }
137 if (i == ARRAY_SIZE(cache_policies))
138 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
139 /*
140 * This restriction is partly to do with the way we boot; it is
141 * unpredictable to have memory mapped using two different sets of
142 * memory attributes (shared, type, and cache attribs). We can not
143 * change these attributes once the initial assembly has setup the
144 * page tables.
145 */
146 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
147 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
148 cachepolicy = CPOLICY_WRITEBACK;
149 }
150 flush_cache_all();
151 set_cr(cr_alignment);
152 return 0;
153 }
154 early_param("cachepolicy", early_cachepolicy);
155
156 static int __init early_nocache(char *__unused)
157 {
158 char *p = "buffered";
159 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
160 early_cachepolicy(p);
161 return 0;
162 }
163 early_param("nocache", early_nocache);
164
165 static int __init early_nowrite(char *__unused)
166 {
167 char *p = "uncached";
168 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
169 early_cachepolicy(p);
170 return 0;
171 }
172 early_param("nowb", early_nowrite);
173
174 #ifndef CONFIG_ARM_LPAE
175 static int __init early_ecc(char *p)
176 {
177 if (memcmp(p, "on", 2) == 0)
178 ecc_mask = PMD_PROTECTION;
179 else if (memcmp(p, "off", 3) == 0)
180 ecc_mask = 0;
181 return 0;
182 }
183 early_param("ecc", early_ecc);
184 #endif
185
186 static int __init noalign_setup(char *__unused)
187 {
188 cr_alignment &= ~CR_A;
189 cr_no_alignment &= ~CR_A;
190 set_cr(cr_alignment);
191 return 1;
192 }
193 __setup("noalign", noalign_setup);
194
195 #ifndef CONFIG_SMP
196 void adjust_cr(unsigned long mask, unsigned long set)
197 {
198 unsigned long flags;
199
200 mask &= ~CR_A;
201
202 set &= mask;
203
204 local_irq_save(flags);
205
206 cr_no_alignment = (cr_no_alignment & ~mask) | set;
207 cr_alignment = (cr_alignment & ~mask) | set;
208
209 set_cr((get_cr() & ~mask) | set);
210
211 local_irq_restore(flags);
212 }
213 #endif
214
215 #else /* ifdef CONFIG_CPU_CP15 */
216
217 static int __init early_cachepolicy(char *p)
218 {
219 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
220 }
221 early_param("cachepolicy", early_cachepolicy);
222
223 static int __init noalign_setup(char *__unused)
224 {
225 pr_warning("noalign kernel parameter not supported without cp15\n");
226 }
227 __setup("noalign", noalign_setup);
228
229 #endif /* ifdef CONFIG_CPU_CP15 / else */
230
231 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
232 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
233
234 static struct mem_type mem_types[] = {
235 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
236 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
237 L_PTE_SHARED,
238 .prot_l1 = PMD_TYPE_TABLE,
239 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
240 .domain = DOMAIN_IO,
241 },
242 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
243 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
244 .prot_l1 = PMD_TYPE_TABLE,
245 .prot_sect = PROT_SECT_DEVICE,
246 .domain = DOMAIN_IO,
247 },
248 [MT_DEVICE_CACHED] = { /* ioremap_cached */
249 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
250 .prot_l1 = PMD_TYPE_TABLE,
251 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
252 .domain = DOMAIN_IO,
253 },
254 [MT_DEVICE_WC] = { /* ioremap_wc */
255 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
256 .prot_l1 = PMD_TYPE_TABLE,
257 .prot_sect = PROT_SECT_DEVICE,
258 .domain = DOMAIN_IO,
259 },
260 [MT_UNCACHED] = {
261 .prot_pte = PROT_PTE_DEVICE,
262 .prot_l1 = PMD_TYPE_TABLE,
263 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
264 .domain = DOMAIN_IO,
265 },
266 [MT_CACHECLEAN] = {
267 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
268 .domain = DOMAIN_KERNEL,
269 },
270 #ifndef CONFIG_ARM_LPAE
271 [MT_MINICLEAN] = {
272 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
273 .domain = DOMAIN_KERNEL,
274 },
275 #endif
276 [MT_LOW_VECTORS] = {
277 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
278 L_PTE_RDONLY,
279 .prot_l1 = PMD_TYPE_TABLE,
280 .domain = DOMAIN_USER,
281 },
282 [MT_HIGH_VECTORS] = {
283 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
284 L_PTE_USER | L_PTE_RDONLY,
285 .prot_l1 = PMD_TYPE_TABLE,
286 .domain = DOMAIN_USER,
287 },
288 [MT_MEMORY] = {
289 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
290 .prot_l1 = PMD_TYPE_TABLE,
291 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
292 .domain = DOMAIN_KERNEL,
293 },
294 [MT_ROM] = {
295 .prot_sect = PMD_TYPE_SECT,
296 .domain = DOMAIN_KERNEL,
297 },
298 [MT_MEMORY_NONCACHED] = {
299 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
300 L_PTE_MT_BUFFERABLE,
301 .prot_l1 = PMD_TYPE_TABLE,
302 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
303 .domain = DOMAIN_KERNEL,
304 },
305 [MT_MEMORY_DTCM] = {
306 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
307 L_PTE_XN,
308 .prot_l1 = PMD_TYPE_TABLE,
309 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
310 .domain = DOMAIN_KERNEL,
311 },
312 [MT_MEMORY_ITCM] = {
313 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
314 .prot_l1 = PMD_TYPE_TABLE,
315 .domain = DOMAIN_KERNEL,
316 },
317 [MT_MEMORY_SO] = {
318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
319 L_PTE_MT_UNCACHED | L_PTE_XN,
320 .prot_l1 = PMD_TYPE_TABLE,
321 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
322 PMD_SECT_UNCACHED | PMD_SECT_XN,
323 .domain = DOMAIN_KERNEL,
324 },
325 [MT_MEMORY_DMA_READY] = {
326 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
327 .prot_l1 = PMD_TYPE_TABLE,
328 .domain = DOMAIN_KERNEL,
329 },
330 };
331
332 const struct mem_type *get_mem_type(unsigned int type)
333 {
334 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
335 }
336 EXPORT_SYMBOL(get_mem_type);
337
338 /*
339 * Adjust the PMD section entries according to the CPU in use.
340 */
341 static void __init build_mem_type_table(void)
342 {
343 struct cachepolicy *cp;
344 unsigned int cr = get_cr();
345 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
346 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
347 int cpu_arch = cpu_architecture();
348 int i;
349
350 if (cpu_arch < CPU_ARCH_ARMv6) {
351 #if defined(CONFIG_CPU_DCACHE_DISABLE)
352 if (cachepolicy > CPOLICY_BUFFERED)
353 cachepolicy = CPOLICY_BUFFERED;
354 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
355 if (cachepolicy > CPOLICY_WRITETHROUGH)
356 cachepolicy = CPOLICY_WRITETHROUGH;
357 #endif
358 }
359 if (cpu_arch < CPU_ARCH_ARMv5) {
360 if (cachepolicy >= CPOLICY_WRITEALLOC)
361 cachepolicy = CPOLICY_WRITEBACK;
362 ecc_mask = 0;
363 }
364 if (is_smp())
365 cachepolicy = CPOLICY_WRITEALLOC;
366
367 /*
368 * Strip out features not present on earlier architectures.
369 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
370 * without extended page tables don't have the 'Shared' bit.
371 */
372 if (cpu_arch < CPU_ARCH_ARMv5)
373 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
374 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
375 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
376 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
377 mem_types[i].prot_sect &= ~PMD_SECT_S;
378
379 /*
380 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
381 * "update-able on write" bit on ARM610). However, Xscale and
382 * Xscale3 require this bit to be cleared.
383 */
384 if (cpu_is_xscale() || cpu_is_xsc3()) {
385 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
386 mem_types[i].prot_sect &= ~PMD_BIT4;
387 mem_types[i].prot_l1 &= ~PMD_BIT4;
388 }
389 } else if (cpu_arch < CPU_ARCH_ARMv6) {
390 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
391 if (mem_types[i].prot_l1)
392 mem_types[i].prot_l1 |= PMD_BIT4;
393 if (mem_types[i].prot_sect)
394 mem_types[i].prot_sect |= PMD_BIT4;
395 }
396 }
397
398 /*
399 * Mark the device areas according to the CPU/architecture.
400 */
401 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
402 if (!cpu_is_xsc3()) {
403 /*
404 * Mark device regions on ARMv6+ as execute-never
405 * to prevent speculative instruction fetches.
406 */
407 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
408 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
409 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
410 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
411 }
412 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
413 /*
414 * For ARMv7 with TEX remapping,
415 * - shared device is SXCB=1100
416 * - nonshared device is SXCB=0100
417 * - write combine device mem is SXCB=0001
418 * (Uncached Normal memory)
419 */
420 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
421 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
422 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
423 } else if (cpu_is_xsc3()) {
424 /*
425 * For Xscale3,
426 * - shared device is TEXCB=00101
427 * - nonshared device is TEXCB=01000
428 * - write combine device mem is TEXCB=00100
429 * (Inner/Outer Uncacheable in xsc3 parlance)
430 */
431 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
432 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
433 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
434 } else {
435 /*
436 * For ARMv6 and ARMv7 without TEX remapping,
437 * - shared device is TEXCB=00001
438 * - nonshared device is TEXCB=01000
439 * - write combine device mem is TEXCB=00100
440 * (Uncached Normal in ARMv6 parlance).
441 */
442 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
443 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
444 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
445 }
446 } else {
447 /*
448 * On others, write combining is "Uncached/Buffered"
449 */
450 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
451 }
452
453 /*
454 * Now deal with the memory-type mappings
455 */
456 cp = &cache_policies[cachepolicy];
457 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
458 s2_pgprot = cp->pte_s2;
459 hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
460
461 /*
462 * ARMv6 and above have extended page tables.
463 */
464 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
465 #ifndef CONFIG_ARM_LPAE
466 /*
467 * Mark cache clean areas and XIP ROM read only
468 * from SVC mode and no access from userspace.
469 */
470 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
471 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
472 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
473 #endif
474
475 if (is_smp()) {
476 /*
477 * Mark memory with the "shared" attribute
478 * for SMP systems
479 */
480 user_pgprot |= L_PTE_SHARED;
481 kern_pgprot |= L_PTE_SHARED;
482 vecs_pgprot |= L_PTE_SHARED;
483 s2_pgprot |= L_PTE_SHARED;
484 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
485 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
486 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
487 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
488 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
489 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
490 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
491 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
492 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
493 }
494 }
495
496 /*
497 * Non-cacheable Normal - intended for memory areas that must
498 * not cause dirty cache line writebacks when used
499 */
500 if (cpu_arch >= CPU_ARCH_ARMv6) {
501 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
502 /* Non-cacheable Normal is XCB = 001 */
503 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
504 PMD_SECT_BUFFERED;
505 } else {
506 /* For both ARMv6 and non-TEX-remapping ARMv7 */
507 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
508 PMD_SECT_TEX(1);
509 }
510 } else {
511 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
512 }
513
514 #ifdef CONFIG_ARM_LPAE
515 /*
516 * Do not generate access flag faults for the kernel mappings.
517 */
518 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
519 mem_types[i].prot_pte |= PTE_EXT_AF;
520 if (mem_types[i].prot_sect)
521 mem_types[i].prot_sect |= PMD_SECT_AF;
522 }
523 kern_pgprot |= PTE_EXT_AF;
524 vecs_pgprot |= PTE_EXT_AF;
525 #endif
526
527 for (i = 0; i < 16; i++) {
528 pteval_t v = pgprot_val(protection_map[i]);
529 protection_map[i] = __pgprot(v | user_pgprot);
530 }
531
532 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
533 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
534
535 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
536 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
537 L_PTE_DIRTY | kern_pgprot);
538 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
539 pgprot_s2_device = __pgprot(s2_device_pgprot);
540 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
541
542 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
543 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
544 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
545 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
546 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
547 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
548 mem_types[MT_ROM].prot_sect |= cp->pmd;
549
550 switch (cp->pmd) {
551 case PMD_SECT_WT:
552 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
553 break;
554 case PMD_SECT_WB:
555 case PMD_SECT_WBWA:
556 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
557 break;
558 }
559 printk("Memory policy: ECC %sabled, Data cache %s\n",
560 ecc_mask ? "en" : "dis", cp->policy);
561
562 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
563 struct mem_type *t = &mem_types[i];
564 if (t->prot_l1)
565 t->prot_l1 |= PMD_DOMAIN(t->domain);
566 if (t->prot_sect)
567 t->prot_sect |= PMD_DOMAIN(t->domain);
568 }
569 }
570
571 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
572 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
573 unsigned long size, pgprot_t vma_prot)
574 {
575 if (!pfn_valid(pfn))
576 return pgprot_noncached(vma_prot);
577 else if (file->f_flags & O_SYNC)
578 return pgprot_writecombine(vma_prot);
579 return vma_prot;
580 }
581 EXPORT_SYMBOL(phys_mem_access_prot);
582 #endif
583
584 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
585
586 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
587 {
588 void *ptr = __va(memblock_alloc(sz, align));
589 memset(ptr, 0, sz);
590 return ptr;
591 }
592
593 static void __init *early_alloc(unsigned long sz)
594 {
595 return early_alloc_aligned(sz, sz);
596 }
597
598 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
599 {
600 if (pmd_none(*pmd)) {
601 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
602 __pmd_populate(pmd, __pa(pte), prot);
603 }
604 BUG_ON(pmd_bad(*pmd));
605 return pte_offset_kernel(pmd, addr);
606 }
607
608 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
609 unsigned long end, unsigned long pfn,
610 const struct mem_type *type)
611 {
612 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
613 do {
614 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
615 pfn++;
616 } while (pte++, addr += PAGE_SIZE, addr != end);
617 }
618
619 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
620 unsigned long end, phys_addr_t phys,
621 const struct mem_type *type)
622 {
623 pmd_t *p = pmd;
624
625 #ifndef CONFIG_ARM_LPAE
626 /*
627 * In classic MMU format, puds and pmds are folded in to
628 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
629 * group of L1 entries making up one logical pointer to
630 * an L2 table (2MB), where as PMDs refer to the individual
631 * L1 entries (1MB). Hence increment to get the correct
632 * offset for odd 1MB sections.
633 * (See arch/arm/include/asm/pgtable-2level.h)
634 */
635 if (addr & SECTION_SIZE)
636 pmd++;
637 #endif
638 do {
639 *pmd = __pmd(phys | type->prot_sect);
640 phys += SECTION_SIZE;
641 } while (pmd++, addr += SECTION_SIZE, addr != end);
642
643 flush_pmd_entry(p);
644 }
645
646 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
647 unsigned long end, phys_addr_t phys,
648 const struct mem_type *type)
649 {
650 pmd_t *pmd = pmd_offset(pud, addr);
651 unsigned long next;
652
653 do {
654 /*
655 * With LPAE, we must loop over to map
656 * all the pmds for the given range.
657 */
658 next = pmd_addr_end(addr, end);
659
660 /*
661 * Try a section mapping - addr, next and phys must all be
662 * aligned to a section boundary.
663 */
664 if (type->prot_sect &&
665 ((addr | next | phys) & ~SECTION_MASK) == 0) {
666 __map_init_section(pmd, addr, next, phys, type);
667 } else {
668 alloc_init_pte(pmd, addr, next,
669 __phys_to_pfn(phys), type);
670 }
671
672 phys += next - addr;
673
674 } while (pmd++, addr = next, addr != end);
675 }
676
677 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
678 unsigned long end, unsigned long phys, const struct mem_type *type)
679 {
680 pud_t *pud = pud_offset(pgd, addr);
681 unsigned long next;
682
683 do {
684 next = pud_addr_end(addr, end);
685 alloc_init_pmd(pud, addr, next, phys, type);
686 phys += next - addr;
687 } while (pud++, addr = next, addr != end);
688 }
689
690 #ifndef CONFIG_ARM_LPAE
691 static void __init create_36bit_mapping(struct map_desc *md,
692 const struct mem_type *type)
693 {
694 unsigned long addr, length, end;
695 phys_addr_t phys;
696 pgd_t *pgd;
697
698 addr = md->virtual;
699 phys = __pfn_to_phys(md->pfn);
700 length = PAGE_ALIGN(md->length);
701
702 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
703 printk(KERN_ERR "MM: CPU does not support supersection "
704 "mapping for 0x%08llx at 0x%08lx\n",
705 (long long)__pfn_to_phys((u64)md->pfn), addr);
706 return;
707 }
708
709 /* N.B. ARMv6 supersections are only defined to work with domain 0.
710 * Since domain assignments can in fact be arbitrary, the
711 * 'domain == 0' check below is required to insure that ARMv6
712 * supersections are only allocated for domain 0 regardless
713 * of the actual domain assignments in use.
714 */
715 if (type->domain) {
716 printk(KERN_ERR "MM: invalid domain in supersection "
717 "mapping for 0x%08llx at 0x%08lx\n",
718 (long long)__pfn_to_phys((u64)md->pfn), addr);
719 return;
720 }
721
722 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
723 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
724 " at 0x%08lx invalid alignment\n",
725 (long long)__pfn_to_phys((u64)md->pfn), addr);
726 return;
727 }
728
729 /*
730 * Shift bits [35:32] of address into bits [23:20] of PMD
731 * (See ARMv6 spec).
732 */
733 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
734
735 pgd = pgd_offset_k(addr);
736 end = addr + length;
737 do {
738 pud_t *pud = pud_offset(pgd, addr);
739 pmd_t *pmd = pmd_offset(pud, addr);
740 int i;
741
742 for (i = 0; i < 16; i++)
743 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
744
745 addr += SUPERSECTION_SIZE;
746 phys += SUPERSECTION_SIZE;
747 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
748 } while (addr != end);
749 }
750 #endif /* !CONFIG_ARM_LPAE */
751
752 /*
753 * Create the page directory entries and any necessary
754 * page tables for the mapping specified by `md'. We
755 * are able to cope here with varying sizes and address
756 * offsets, and we take full advantage of sections and
757 * supersections.
758 */
759 static void __init create_mapping(struct map_desc *md)
760 {
761 unsigned long addr, length, end;
762 phys_addr_t phys;
763 const struct mem_type *type;
764 pgd_t *pgd;
765
766 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
767 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
768 " at 0x%08lx in user region\n",
769 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
770 return;
771 }
772
773 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
774 md->virtual >= PAGE_OFFSET &&
775 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
776 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
777 " at 0x%08lx out of vmalloc space\n",
778 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
779 }
780
781 type = &mem_types[md->type];
782
783 #ifndef CONFIG_ARM_LPAE
784 /*
785 * Catch 36-bit addresses
786 */
787 if (md->pfn >= 0x100000) {
788 create_36bit_mapping(md, type);
789 return;
790 }
791 #endif
792
793 addr = md->virtual & PAGE_MASK;
794 phys = __pfn_to_phys(md->pfn);
795 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
796
797 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
798 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
799 "be mapped using pages, ignoring.\n",
800 (long long)__pfn_to_phys(md->pfn), addr);
801 return;
802 }
803
804 pgd = pgd_offset_k(addr);
805 end = addr + length;
806 do {
807 unsigned long next = pgd_addr_end(addr, end);
808
809 alloc_init_pud(pgd, addr, next, phys, type);
810
811 phys += next - addr;
812 addr = next;
813 } while (pgd++, addr != end);
814 }
815
816 /*
817 * Create the architecture specific mappings
818 */
819 void __init iotable_init(struct map_desc *io_desc, int nr)
820 {
821 struct map_desc *md;
822 struct vm_struct *vm;
823 struct static_vm *svm;
824
825 if (!nr)
826 return;
827
828 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
829
830 for (md = io_desc; nr; md++, nr--) {
831 create_mapping(md);
832
833 vm = &svm->vm;
834 vm->addr = (void *)(md->virtual & PAGE_MASK);
835 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
836 vm->phys_addr = __pfn_to_phys(md->pfn);
837 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
838 vm->flags |= VM_ARM_MTYPE(md->type);
839 vm->caller = iotable_init;
840 add_static_vm_early(svm++);
841 }
842 }
843
844 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
845 void *caller)
846 {
847 struct vm_struct *vm;
848 struct static_vm *svm;
849
850 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
851
852 vm = &svm->vm;
853 vm->addr = (void *)addr;
854 vm->size = size;
855 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
856 vm->caller = caller;
857 add_static_vm_early(svm);
858 }
859
860 #ifndef CONFIG_ARM_LPAE
861
862 /*
863 * The Linux PMD is made of two consecutive section entries covering 2MB
864 * (see definition in include/asm/pgtable-2level.h). However a call to
865 * create_mapping() may optimize static mappings by using individual
866 * 1MB section mappings. This leaves the actual PMD potentially half
867 * initialized if the top or bottom section entry isn't used, leaving it
868 * open to problems if a subsequent ioremap() or vmalloc() tries to use
869 * the virtual space left free by that unused section entry.
870 *
871 * Let's avoid the issue by inserting dummy vm entries covering the unused
872 * PMD halves once the static mappings are in place.
873 */
874
875 static void __init pmd_empty_section_gap(unsigned long addr)
876 {
877 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
878 }
879
880 static void __init fill_pmd_gaps(void)
881 {
882 struct static_vm *svm;
883 struct vm_struct *vm;
884 unsigned long addr, next = 0;
885 pmd_t *pmd;
886
887 list_for_each_entry(svm, &static_vmlist, list) {
888 vm = &svm->vm;
889 addr = (unsigned long)vm->addr;
890 if (addr < next)
891 continue;
892
893 /*
894 * Check if this vm starts on an odd section boundary.
895 * If so and the first section entry for this PMD is free
896 * then we block the corresponding virtual address.
897 */
898 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
899 pmd = pmd_off_k(addr);
900 if (pmd_none(*pmd))
901 pmd_empty_section_gap(addr & PMD_MASK);
902 }
903
904 /*
905 * Then check if this vm ends on an odd section boundary.
906 * If so and the second section entry for this PMD is empty
907 * then we block the corresponding virtual address.
908 */
909 addr += vm->size;
910 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
911 pmd = pmd_off_k(addr) + 1;
912 if (pmd_none(*pmd))
913 pmd_empty_section_gap(addr);
914 }
915
916 /* no need to look at any vm entry until we hit the next PMD */
917 next = (addr + PMD_SIZE - 1) & PMD_MASK;
918 }
919 }
920
921 #else
922 #define fill_pmd_gaps() do { } while (0)
923 #endif
924
925 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
926 static void __init pci_reserve_io(void)
927 {
928 struct static_vm *svm;
929
930 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
931 if (svm)
932 return;
933
934 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
935 }
936 #else
937 #define pci_reserve_io() do { } while (0)
938 #endif
939
940 #ifdef CONFIG_DEBUG_LL
941 void __init debug_ll_io_init(void)
942 {
943 struct map_desc map;
944
945 debug_ll_addr(&map.pfn, &map.virtual);
946 if (!map.pfn || !map.virtual)
947 return;
948 map.pfn = __phys_to_pfn(map.pfn);
949 map.virtual &= PAGE_MASK;
950 map.length = PAGE_SIZE;
951 map.type = MT_DEVICE;
952 create_mapping(&map);
953 }
954 #endif
955
956 static void * __initdata vmalloc_min =
957 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
958
959 /*
960 * vmalloc=size forces the vmalloc area to be exactly 'size'
961 * bytes. This can be used to increase (or decrease) the vmalloc
962 * area - the default is 240m.
963 */
964 static int __init early_vmalloc(char *arg)
965 {
966 unsigned long vmalloc_reserve = memparse(arg, NULL);
967
968 if (vmalloc_reserve < SZ_16M) {
969 vmalloc_reserve = SZ_16M;
970 printk(KERN_WARNING
971 "vmalloc area too small, limiting to %luMB\n",
972 vmalloc_reserve >> 20);
973 }
974
975 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
976 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
977 printk(KERN_WARNING
978 "vmalloc area is too big, limiting to %luMB\n",
979 vmalloc_reserve >> 20);
980 }
981
982 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
983 return 0;
984 }
985 early_param("vmalloc", early_vmalloc);
986
987 phys_addr_t arm_lowmem_limit __initdata = 0;
988
989 void __init sanity_check_meminfo(void)
990 {
991 int i, j, highmem = 0;
992
993 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
994 struct membank *bank = &meminfo.bank[j];
995 *bank = meminfo.bank[i];
996
997 if (bank->start > ULONG_MAX)
998 highmem = 1;
999
1000 #ifdef CONFIG_HIGHMEM
1001 if (__va(bank->start) >= vmalloc_min ||
1002 __va(bank->start) < (void *)PAGE_OFFSET)
1003 highmem = 1;
1004
1005 bank->highmem = highmem;
1006
1007 /*
1008 * Split those memory banks which are partially overlapping
1009 * the vmalloc area greatly simplifying things later.
1010 */
1011 if (!highmem && __va(bank->start) < vmalloc_min &&
1012 bank->size > vmalloc_min - __va(bank->start)) {
1013 if (meminfo.nr_banks >= NR_BANKS) {
1014 printk(KERN_CRIT "NR_BANKS too low, "
1015 "ignoring high memory\n");
1016 } else {
1017 memmove(bank + 1, bank,
1018 (meminfo.nr_banks - i) * sizeof(*bank));
1019 meminfo.nr_banks++;
1020 i++;
1021 bank[1].size -= vmalloc_min - __va(bank->start);
1022 bank[1].start = __pa(vmalloc_min - 1) + 1;
1023 bank[1].highmem = highmem = 1;
1024 j++;
1025 }
1026 bank->size = vmalloc_min - __va(bank->start);
1027 }
1028 #else
1029 bank->highmem = highmem;
1030
1031 /*
1032 * Highmem banks not allowed with !CONFIG_HIGHMEM.
1033 */
1034 if (highmem) {
1035 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1036 "(!CONFIG_HIGHMEM).\n",
1037 (unsigned long long)bank->start,
1038 (unsigned long long)bank->start + bank->size - 1);
1039 continue;
1040 }
1041
1042 /*
1043 * Check whether this memory bank would entirely overlap
1044 * the vmalloc area.
1045 */
1046 if (__va(bank->start) >= vmalloc_min ||
1047 __va(bank->start) < (void *)PAGE_OFFSET) {
1048 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1049 "(vmalloc region overlap).\n",
1050 (unsigned long long)bank->start,
1051 (unsigned long long)bank->start + bank->size - 1);
1052 continue;
1053 }
1054
1055 /*
1056 * Check whether this memory bank would partially overlap
1057 * the vmalloc area.
1058 */
1059 if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
1060 __va(bank->start + bank->size - 1) <= __va(bank->start)) {
1061 unsigned long newsize = vmalloc_min - __va(bank->start);
1062 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1063 "to -%.8llx (vmalloc region overlap).\n",
1064 (unsigned long long)bank->start,
1065 (unsigned long long)bank->start + bank->size - 1,
1066 (unsigned long long)bank->start + newsize - 1);
1067 bank->size = newsize;
1068 }
1069 #endif
1070 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
1071 arm_lowmem_limit = bank->start + bank->size;
1072
1073 j++;
1074 }
1075 #ifdef CONFIG_HIGHMEM
1076 if (highmem) {
1077 const char *reason = NULL;
1078
1079 if (cache_is_vipt_aliasing()) {
1080 /*
1081 * Interactions between kmap and other mappings
1082 * make highmem support with aliasing VIPT caches
1083 * rather difficult.
1084 */
1085 reason = "with VIPT aliasing cache";
1086 }
1087 if (reason) {
1088 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1089 reason);
1090 while (j > 0 && meminfo.bank[j - 1].highmem)
1091 j--;
1092 }
1093 }
1094 #endif
1095 meminfo.nr_banks = j;
1096 high_memory = __va(arm_lowmem_limit - 1) + 1;
1097 memblock_set_current_limit(arm_lowmem_limit);
1098 }
1099
1100 static inline void prepare_page_table(void)
1101 {
1102 unsigned long addr;
1103 phys_addr_t end;
1104
1105 /*
1106 * Clear out all the mappings below the kernel image.
1107 */
1108 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1109 pmd_clear(pmd_off_k(addr));
1110
1111 #ifdef CONFIG_XIP_KERNEL
1112 /* The XIP kernel is mapped in the module area -- skip over it */
1113 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1114 #endif
1115 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1116 pmd_clear(pmd_off_k(addr));
1117
1118 /*
1119 * Find the end of the first block of lowmem.
1120 */
1121 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1122 if (end >= arm_lowmem_limit)
1123 end = arm_lowmem_limit;
1124
1125 /*
1126 * Clear out all the kernel space mappings, except for the first
1127 * memory bank, up to the vmalloc region.
1128 */
1129 for (addr = __phys_to_virt(end);
1130 addr < VMALLOC_START; addr += PMD_SIZE)
1131 pmd_clear(pmd_off_k(addr));
1132 }
1133
1134 #ifdef CONFIG_ARM_LPAE
1135 /* the first page is reserved for pgd */
1136 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1137 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1138 #else
1139 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1140 #endif
1141
1142 /*
1143 * Reserve the special regions of memory
1144 */
1145 void __init arm_mm_memblock_reserve(void)
1146 {
1147 /*
1148 * Reserve the page tables. These are already in use,
1149 * and can only be in node 0.
1150 */
1151 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1152
1153 #ifdef CONFIG_SA1111
1154 /*
1155 * Because of the SA1111 DMA bug, we want to preserve our
1156 * precious DMA-able memory...
1157 */
1158 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1159 #endif
1160 }
1161
1162 /*
1163 * Set up the device mappings. Since we clear out the page tables for all
1164 * mappings above VMALLOC_START, we will remove any debug device mappings.
1165 * This means you have to be careful how you debug this function, or any
1166 * called function. This means you can't use any function or debugging
1167 * method which may touch any device, otherwise the kernel _will_ crash.
1168 */
1169 static void __init devicemaps_init(struct machine_desc *mdesc)
1170 {
1171 struct map_desc map;
1172 unsigned long addr;
1173 void *vectors;
1174
1175 /*
1176 * Allocate the vector page early.
1177 */
1178 vectors = early_alloc(PAGE_SIZE);
1179
1180 early_trap_init(vectors);
1181
1182 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1183 pmd_clear(pmd_off_k(addr));
1184
1185 /*
1186 * Map the kernel if it is XIP.
1187 * It is always first in the modulearea.
1188 */
1189 #ifdef CONFIG_XIP_KERNEL
1190 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1191 map.virtual = MODULES_VADDR;
1192 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1193 map.type = MT_ROM;
1194 create_mapping(&map);
1195 #endif
1196
1197 /*
1198 * Map the cache flushing regions.
1199 */
1200 #ifdef FLUSH_BASE
1201 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1202 map.virtual = FLUSH_BASE;
1203 map.length = SZ_1M;
1204 map.type = MT_CACHECLEAN;
1205 create_mapping(&map);
1206 #endif
1207 #ifdef FLUSH_BASE_MINICACHE
1208 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1209 map.virtual = FLUSH_BASE_MINICACHE;
1210 map.length = SZ_1M;
1211 map.type = MT_MINICLEAN;
1212 create_mapping(&map);
1213 #endif
1214
1215 /*
1216 * Create a mapping for the machine vectors at the high-vectors
1217 * location (0xffff0000). If we aren't using high-vectors, also
1218 * create a mapping at the low-vectors virtual address.
1219 */
1220 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1221 map.virtual = 0xffff0000;
1222 map.length = PAGE_SIZE;
1223 map.type = MT_HIGH_VECTORS;
1224 create_mapping(&map);
1225
1226 if (!vectors_high()) {
1227 map.virtual = 0;
1228 map.type = MT_LOW_VECTORS;
1229 create_mapping(&map);
1230 }
1231
1232 /*
1233 * Ask the machine support to map in the statically mapped devices.
1234 */
1235 if (mdesc->map_io)
1236 mdesc->map_io();
1237 fill_pmd_gaps();
1238
1239 /* Reserve fixed i/o space in VMALLOC region */
1240 pci_reserve_io();
1241
1242 /*
1243 * Finally flush the caches and tlb to ensure that we're in a
1244 * consistent state wrt the writebuffer. This also ensures that
1245 * any write-allocated cache lines in the vector page are written
1246 * back. After this point, we can start to touch devices again.
1247 */
1248 local_flush_tlb_all();
1249 flush_cache_all();
1250 }
1251
1252 static void __init kmap_init(void)
1253 {
1254 #ifdef CONFIG_HIGHMEM
1255 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1256 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1257 #endif
1258 }
1259
1260 static void __init map_lowmem(void)
1261 {
1262 struct memblock_region *reg;
1263
1264 /* Map all the lowmem memory banks. */
1265 for_each_memblock(memory, reg) {
1266 phys_addr_t start = reg->base;
1267 phys_addr_t end = start + reg->size;
1268 struct map_desc map;
1269
1270 if (end > arm_lowmem_limit)
1271 end = arm_lowmem_limit;
1272 if (start >= end)
1273 break;
1274
1275 map.pfn = __phys_to_pfn(start);
1276 map.virtual = __phys_to_virt(start);
1277 map.length = end - start;
1278 map.type = MT_MEMORY;
1279
1280 create_mapping(&map);
1281 }
1282 }
1283
1284 /*
1285 * paging_init() sets up the page tables, initialises the zone memory
1286 * maps, and sets up the zero page, bad page and bad page tables.
1287 */
1288 void __init paging_init(struct machine_desc *mdesc)
1289 {
1290 void *zero_page;
1291
1292 memblock_set_current_limit(arm_lowmem_limit);
1293
1294 build_mem_type_table();
1295 prepare_page_table();
1296 map_lowmem();
1297 dma_contiguous_remap();
1298 devicemaps_init(mdesc);
1299 kmap_init();
1300 tcm_init();
1301
1302 top_pmd = pmd_off_k(0xffff0000);
1303
1304 /* allocate the zero page. */
1305 zero_page = early_alloc(PAGE_SIZE);
1306
1307 bootmem_init();
1308
1309 empty_zero_page = virt_to_page(zero_page);
1310 __flush_dcache_page(NULL, empty_zero_page);
1311 }
kernel source for telekom puls (alcatel/mediatek)