arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 config CPU_32
   4         bool
   5         default y
   6
   7 # Select CPU types depending on the architecture selected.  This selects
   8 # which CPUs we support in the kernel image, and the compiler instruction
   9 # optimiser behaviour.
  10
  11 # ARM610
  12 config CPU_ARM610
  13         bool "Support ARM610 processor"
  14         depends on ARCH_RPC
  15         select CPU_32v3
  16         select CPU_CACHE_V3
  17         select CPU_CACHE_VIVT
  18         select CPU_CP15_MMU
  19         select CPU_COPY_V3 if MMU
  20         select CPU_TLB_V3 if MMU
  21         help
  22           The ARM610 is the successor to the ARM3 processor
  23           and was produced by VLSI Technology Inc.
  24
  25           Say Y if you want support for the ARM610 processor.
  26           Otherwise, say N.
  27
  28 # ARM7TDMI
  29 config CPU_ARM7TDMI
  30         bool "Support ARM7TDMI processor"
  31         depends on !MMU
  32         select CPU_32v4T
  33         select CPU_ABRT_LV4T
  34         select CPU_CACHE_V4
  35         help
  36           A 32-bit RISC microprocessor based on the ARM7 processor core
  37           which has no memory control unit and cache.
  38
  39           Say Y if you want support for the ARM7TDMI processor.
  40           Otherwise, say N.
  41
  42 # ARM710
  43 config CPU_ARM710
  44         bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  45         default y if ARCH_CLPS7500
  46         select CPU_32v3
  47         select CPU_CACHE_V3
  48         select CPU_CACHE_VIVT
  49         select CPU_CP15_MMU
  50         select CPU_COPY_V3 if MMU
  51         select CPU_TLB_V3 if MMU
  52         help
  53           A 32-bit RISC microprocessor based on the ARM7 processor core
  54           designed by Advanced RISC Machines Ltd. The ARM710 is the
  55           successor to the ARM610 processor. It was released in
  56           July 1994 by VLSI Technology Inc.
  57
  58           Say Y if you want support for the ARM710 processor.
  59           Otherwise, say N.
  60
  61 # ARM720T
  62 config CPU_ARM720T
  63         bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  64         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  65         select CPU_32v4T
  66         select CPU_ABRT_LV4T
  67         select CPU_CACHE_V4
  68         select CPU_CACHE_VIVT
  69         select CPU_CP15_MMU
  70         select CPU_COPY_V4WT if MMU
  71         select CPU_TLB_V4WT if MMU
  72         help
  73           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  74           MMU built around an ARM7TDMI core.
  75
  76           Say Y if you want support for the ARM720T processor.
  77           Otherwise, say N.
  78
  79 # ARM740T
  80 config CPU_ARM740T
  81         bool "Support ARM740T processor" if ARCH_INTEGRATOR
  82         depends on !MMU
  83         select CPU_32v4T
  84         select CPU_ABRT_LV4T
  85         select CPU_CACHE_V3     # although the core is v4t
  86         select CPU_CP15_MPU
  87         help
  88           A 32-bit RISC processor with 8KB cache or 4KB variants,
  89           write buffer and MPU(Protection Unit) built around
  90           an ARM7TDMI core.
  91
  92           Say Y if you want support for the ARM740T processor.
  93           Otherwise, say N.
  94
  95 # ARM9TDMI
  96 config CPU_ARM9TDMI
  97         bool "Support ARM9TDMI processor"
  98         depends on !MMU
  99         select CPU_32v4T
 100         select CPU_ABRT_NOMMU
 101         select CPU_CACHE_V4
 102         help
 103           A 32-bit RISC microprocessor based on the ARM9 processor core
 104           which has no memory control unit and cache.
 105
 106           Say Y if you want support for the ARM9TDMI processor.
 107           Otherwise, say N.
 108
 109 # ARM920T
 110 config CPU_ARM920T
 111         bool "Support ARM920T processor"
 112         depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
 113         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
 114         select CPU_32v4T
 115         select CPU_ABRT_EV4T
 116         select CPU_CACHE_V4WT
 117         select CPU_CACHE_VIVT
 118         select CPU_CP15_MMU
 119         select CPU_COPY_V4WB if MMU
 120         select CPU_TLB_V4WBI if MMU
 121         help
 122           The ARM920T is licensed to be produced by numerous vendors,
 123           and is used in the Maverick EP9312 and the Samsung S3C2410.
 124
 125           More information on the Maverick EP9312 at
 126           <http://linuxdevices.com/products/PD2382866068.html>.
 127
 128           Say Y if you want support for the ARM920T processor.
 129           Otherwise, say N.
 130
 131 # ARM922T
 132 config CPU_ARM922T
 133         bool "Support ARM922T processor" if ARCH_INTEGRATOR
 134         depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
 135         default y if ARCH_LH7A40X || ARCH_KS8695
 136         select CPU_32v4T
 137         select CPU_ABRT_EV4T
 138         select CPU_CACHE_V4WT
 139         select CPU_CACHE_VIVT
 140         select CPU_CP15_MMU
 141         select CPU_COPY_V4WB if MMU
 142         select CPU_TLB_V4WBI if MMU
 143         help
 144           The ARM922T is a version of the ARM920T, but with smaller
 145           instruction and data caches. It is used in Altera's
 146           Excalibur XA device family and Micrel's KS8695 Centaur.
 147
 148           Say Y if you want support for the ARM922T processor.
 149           Otherwise, say N.
 150
 151 # ARM925T
 152 config CPU_ARM925T
 153         bool "Support ARM925T processor" if ARCH_OMAP1
 154         depends on ARCH_OMAP15XX
 155         default y if ARCH_OMAP15XX
 156         select CPU_32v4T
 157         select CPU_ABRT_EV4T
 158         select CPU_CACHE_V4WT
 159         select CPU_CACHE_VIVT
 160         select CPU_CP15_MMU
 161         select CPU_COPY_V4WB if MMU
 162         select CPU_TLB_V4WBI if MMU
 163         help
 164           The ARM925T is a mix between the ARM920T and ARM926T, but with
 165           different instruction and data caches. It is used in TI's OMAP
 166           device family.
 167
 168           Say Y if you want support for the ARM925T processor.
 169           Otherwise, say N.
 170
 171 # ARM926T
 172 config CPU_ARM926T
 173         bool "Support ARM926T processor"
 174         depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
 175         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
 176         select CPU_32v5
 177         select CPU_ABRT_EV5TJ
 178         select CPU_CACHE_VIVT
 179         select CPU_CP15_MMU
 180         select CPU_COPY_V4WB if MMU
 181         select CPU_TLB_V4WBI if MMU
 182         help
 183           This is a variant of the ARM920.  It has slightly different
 184           instruction sequences for cache and TLB operations.  Curiously,
 185           there is no documentation on it at the ARM corporate website.
 186
 187           Say Y if you want support for the ARM926T processor.
 188           Otherwise, say N.
 189
 190 # ARM940T
 191 config CPU_ARM940T
 192         bool "Support ARM940T processor" if ARCH_INTEGRATOR
 193         depends on !MMU
 194         select CPU_32v4T
 195         select CPU_ABRT_NOMMU
 196         select CPU_CACHE_VIVT
 197         select CPU_CP15_MPU
 198         help
 199           ARM940T is a member of the ARM9TDMI family of general-
 200           purpose microprocessors with MPU and separate 4KB
 201           instruction and 4KB data cases, each with a 4-word line
 202           length.
 203
 204           Say Y if you want support for the ARM940T processor.
 205           Otherwise, say N.
 206
 207 # ARM946E-S
 208 config CPU_ARM946E
 209         bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
 210         depends on !MMU
 211         select CPU_32v5
 212         select CPU_ABRT_NOMMU
 213         select CPU_CACHE_VIVT
 214         select CPU_CP15_MPU
 215         help
 216           ARM946E-S is a member of the ARM9E-S family of high-
 217           performance, 32-bit system-on-chip processor solutions.
 218           The TCM and ARMv5TE 32-bit instruction set is supported.
 219
 220           Say Y if you want support for the ARM946E-S processor.
 221           Otherwise, say N.
 222
 223 # ARM1020 - needs validating
 224 config CPU_ARM1020
 225         bool "Support ARM1020T (rev 0) processor"
 226         depends on ARCH_INTEGRATOR
 227         select CPU_32v5
 228         select CPU_ABRT_EV4T
 229         select CPU_CACHE_V4WT
 230         select CPU_CACHE_VIVT
 231         select CPU_CP15_MMU
 232         select CPU_COPY_V4WB if MMU
 233         select CPU_TLB_V4WBI if MMU
 234         help
 235           The ARM1020 is the 32K cached version of the ARM10 processor,
 236           with an addition of a floating-point unit.
 237
 238           Say Y if you want support for the ARM1020 processor.
 239           Otherwise, say N.
 240
 241 # ARM1020E - needs validating
 242 config CPU_ARM1020E
 243         bool "Support ARM1020E processor"
 244         depends on ARCH_INTEGRATOR
 245         select CPU_32v5
 246         select CPU_ABRT_EV4T
 247         select CPU_CACHE_V4WT
 248         select CPU_CACHE_VIVT
 249         select CPU_CP15_MMU
 250         select CPU_COPY_V4WB if MMU
 251         select CPU_TLB_V4WBI if MMU
 252         depends on n
 253
 254 # ARM1022E
 255 config CPU_ARM1022
 256         bool "Support ARM1022E processor"
 257         depends on ARCH_INTEGRATOR
 258         select CPU_32v5
 259         select CPU_ABRT_EV4T
 260         select CPU_CACHE_VIVT
 261         select CPU_CP15_MMU
 262         select CPU_COPY_V4WB if MMU # can probably do better
 263         select CPU_TLB_V4WBI if MMU
 264         help
 265           The ARM1022E is an implementation of the ARMv5TE architecture
 266           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 267           embedded trace macrocell, and a floating-point unit.
 268
 269           Say Y if you want support for the ARM1022E processor.
 270           Otherwise, say N.
 271
 272 # ARM1026EJ-S
 273 config CPU_ARM1026
 274         bool "Support ARM1026EJ-S processor"
 275         depends on ARCH_INTEGRATOR
 276         select CPU_32v5
 277         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 278         select CPU_CACHE_VIVT
 279         select CPU_CP15_MMU
 280         select CPU_COPY_V4WB if MMU # can probably do better
 281         select CPU_TLB_V4WBI if MMU
 282         help
 283           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 284           based upon the ARM10 integer core.
 285
 286           Say Y if you want support for the ARM1026EJ-S processor.
 287           Otherwise, say N.
 288
 289 # SA110
 290 config CPU_SA110
 291         bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
 292         default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
 293         select CPU_32v3 if ARCH_RPC
 294         select CPU_32v4 if !ARCH_RPC
 295         select CPU_ABRT_EV4
 296         select CPU_CACHE_V4WB
 297         select CPU_CACHE_VIVT
 298         select CPU_CP15_MMU
 299         select CPU_COPY_V4WB if MMU
 300         select CPU_TLB_V4WB if MMU
 301         help
 302           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 303           is available at five speeds ranging from 100 MHz to 233 MHz.
 304           More information is available at
 305           <http://developer.intel.com/design/strong/sa110.htm>.
 306
 307           Say Y if you want support for the SA-110 processor.
 308           Otherwise, say N.
 309
 310 # SA1100
 311 config CPU_SA1100
 312         bool
 313         depends on ARCH_SA1100
 314         default y
 315         select CPU_32v4
 316         select CPU_ABRT_EV4
 317         select CPU_CACHE_V4WB
 318         select CPU_CACHE_VIVT
 319         select CPU_CP15_MMU
 320         select CPU_TLB_V4WB if MMU
 321
 322 # XScale
 323 config CPU_XSCALE
 324         bool
 325         depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
 326         default y
 327         select CPU_32v5
 328         select CPU_ABRT_EV5T
 329         select CPU_CACHE_VIVT
 330         select CPU_CP15_MMU
 331         select CPU_TLB_V4WBI if MMU
 332
 333 # XScale Core Version 3
 334 config CPU_XSC3
 335         bool
 336         depends on ARCH_IXP23XX || ARCH_IOP13XX
 337         default y
 338         select CPU_32v5
 339         select CPU_ABRT_EV5T
 340         select CPU_CACHE_VIVT
 341         select CPU_CP15_MMU
 342         select CPU_TLB_V4WBI if MMU
 343         select IO_36
 344
 345 # ARMv6
 346 config CPU_V6
 347         bool "Support ARM V6 processor"
 348         depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
 349         select CPU_32v6
 350         select CPU_ABRT_EV6
 351         select CPU_CACHE_V6
 352         select CPU_CACHE_VIPT
 353         select CPU_CP15_MMU
 354         select CPU_HAS_ASID
 355         select CPU_COPY_V6 if MMU
 356         select CPU_TLB_V6 if MMU
 357
 358 # ARMv6k
 359 config CPU_32v6K
 360         bool "Support ARM V6K processor extensions" if !SMP
 361         depends on CPU_V6
 362         default y if SMP
 363         help
 364           Say Y here if your ARMv6 processor supports the 'K' extension.
 365           This enables the kernel to use some instructions not present
 366           on previous processors, and as such a kernel build with this
 367           enabled will not boot on processors with do not support these
 368           instructions.
 369
 370 # ARMv7
 371 config CPU_V7
 372         bool "Support ARM V7 processor"
 373         depends on ARCH_INTEGRATOR
 374         select CPU_32v6K
 375         select CPU_32v7
 376         select CPU_ABRT_EV7
 377         select CPU_CACHE_V7
 378         select CPU_CACHE_VIPT
 379         select CPU_CP15_MMU
 380         select CPU_HAS_ASID
 381         select CPU_COPY_V6 if MMU
 382         select CPU_TLB_V7 if MMU
 383
 384 # Figure out what processor architecture version we should be using.
 385 # This defines the compiler instruction set which depends on the machine type.
 386 config CPU_32v3
 387         bool
 388         select TLS_REG_EMUL if SMP || !MMU
 389         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 390
 391 config CPU_32v4
 392         bool
 393         select TLS_REG_EMUL if SMP || !MMU
 394         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 395
 396 config CPU_32v4T
 397         bool
 398         select TLS_REG_EMUL if SMP || !MMU
 399         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 400
 401 config CPU_32v5
 402         bool
 403         select TLS_REG_EMUL if SMP || !MMU
 404         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 405
 406 config CPU_32v6
 407         bool
 408
 409 config CPU_32v7
 410         bool
 411
 412 # The abort model
 413 config CPU_ABRT_NOMMU
 414         bool
 415
 416 config CPU_ABRT_EV4
 417         bool
 418
 419 config CPU_ABRT_EV4T
 420         bool
 421
 422 config CPU_ABRT_LV4T
 423         bool
 424
 425 config CPU_ABRT_EV5T
 426         bool
 427
 428 config CPU_ABRT_EV5TJ
 429         bool
 430
 431 config CPU_ABRT_EV6
 432         bool
 433
 434 config CPU_ABRT_EV7
 435         bool
 436
 437 # The cache model
 438 config CPU_CACHE_V3
 439         bool
 440
 441 config CPU_CACHE_V4
 442         bool
 443
 444 config CPU_CACHE_V4WT
 445         bool
 446
 447 config CPU_CACHE_V4WB
 448         bool
 449
 450 config CPU_CACHE_V6
 451         bool
 452
 453 config CPU_CACHE_V7
 454         bool
 455
 456 config CPU_CACHE_VIVT
 457         bool
 458
 459 config CPU_CACHE_VIPT
 460         bool
 461
 462 if MMU
 463 # The copy-page model
 464 config CPU_COPY_V3
 465         bool
 466
 467 config CPU_COPY_V4WT
 468         bool
 469
 470 config CPU_COPY_V4WB
 471         bool
 472
 473 config CPU_COPY_V6
 474         bool
 475
 476 # This selects the TLB model
 477 config CPU_TLB_V3
 478         bool
 479         help
 480           ARM Architecture Version 3 TLB.
 481
 482 config CPU_TLB_V4WT
 483         bool
 484         help
 485           ARM Architecture Version 4 TLB with writethrough cache.
 486
 487 config CPU_TLB_V4WB
 488         bool
 489         help
 490           ARM Architecture Version 4 TLB with writeback cache.
 491
 492 config CPU_TLB_V4WBI
 493         bool
 494         help
 495           ARM Architecture Version 4 TLB with writeback cache and invalidate
 496           instruction cache entry.
 497
 498 config CPU_TLB_V6
 499         bool
 500
 501 config CPU_TLB_V7
 502         bool
 503
 504 endif
 505
 506 config CPU_HAS_ASID
 507         bool
 508         help
 509           This indicates whether the CPU has the ASID register; used to
 510           tag TLB and possibly cache entries.
 511
 512 config CPU_CP15
 513         bool
 514         help
 515           Processor has the CP15 register.
 516
 517 config CPU_CP15_MMU
 518         bool
 519         select CPU_CP15
 520         help
 521           Processor has the CP15 register, which has MMU related registers.
 522
 523 config CPU_CP15_MPU
 524         bool
 525         select CPU_CP15
 526         help
 527           Processor has the CP15 register, which has MPU related registers.
 528
 529 #
 530 # CPU supports 36-bit I/O
 531 #
 532 config IO_36
 533         bool
 534
 535 comment "Processor Features"
 536
 537 config ARM_THUMB
 538         bool "Support Thumb user binaries"
 539         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7
 540         default y
 541         help
 542           Say Y if you want to include kernel support for running user space
 543           Thumb binaries.
 544
 545           The Thumb instruction set is a compressed form of the standard ARM
 546           instruction set resulting in smaller binaries at the expense of
 547           slightly less efficient code.
 548
 549           If you don't know what this all is, saying Y is a safe choice.
 550
 551 config CPU_BIG_ENDIAN
 552         bool "Build big-endian kernel"
 553         depends on ARCH_SUPPORTS_BIG_ENDIAN
 554         help
 555           Say Y if you plan on running a kernel in big-endian mode.
 556           Note that your board must be properly built and your board
 557           port must properly enable any big-endian related features
 558           of your chipset/board/processor.
 559
 560 config CPU_HIGH_VECTOR
 561         depends on !MMU && CPU_CP15 && !CPU_ARM740T
 562         bool "Select the High exception vector"
 563         default n
 564         help
 565           Say Y here to select high exception vector(0xFFFF0000~).
 566           The exception vector can be vary depending on the platform
 567           design in nommu mode. If your platform needs to select
 568           high exception vector, say Y.
 569           Otherwise or if you are unsure, say N, and the low exception
 570           vector (0x00000000~) will be used.
 571
 572 config CPU_ICACHE_DISABLE
 573         bool "Disable I-Cache (I-bit)"
 574         depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 575         help
 576           Say Y here to disable the processor instruction cache. Unless
 577           you have a reason not to or are unsure, say N.
 578
 579 config CPU_DCACHE_DISABLE
 580         bool "Disable D-Cache (C-bit)"
 581         depends on CPU_CP15
 582         help
 583           Say Y here to disable the processor data cache. Unless
 584           you have a reason not to or are unsure, say N.
 585
 586 config CPU_DCACHE_SIZE
 587         hex
 588         depends on CPU_ARM740T || CPU_ARM946E
 589         default 0x00001000 if CPU_ARM740T
 590         default 0x00002000 # default size for ARM946E-S
 591         help
 592           Some cores are synthesizable to have various sized cache. For
 593           ARM946E-S case, it can vary from 0KB to 1MB.
 594           To support such cache operations, it is efficient to know the size
 595           before compile time.
 596           If your SoC is configured to have a different size, define the value
 597           here with proper conditions.
 598
 599 config CPU_DCACHE_WRITETHROUGH
 600         bool "Force write through D-cache"
 601         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
 602         default y if CPU_ARM925T
 603         help
 604           Say Y here to use the data cache in writethrough mode. Unless you
 605           specifically require this or are unsure, say N.
 606
 607 config CPU_CACHE_ROUND_ROBIN
 608         bool "Round robin I and D cache replacement algorithm"
 609         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 610         help
 611           Say Y here to use the predictable round-robin cache replacement
 612           policy.  Unless you specifically require this or are unsure, say N.
 613
 614 config CPU_L2CACHE_DISABLE
 615         bool "Disable level 2 cache"
 616         depends on CPU_V7
 617         help
 618           Say Y here to disable the level 2 cache.  If unsure, say N.
 619
 620 config CPU_BPREDICT_DISABLE
 621         bool "Disable branch prediction"
 622         depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
 623         help
 624           Say Y here to disable branch prediction.  If unsure, say N.
 625
 626 config TLS_REG_EMUL
 627         bool
 628         help
 629           An SMP system using a pre-ARMv6 processor (there are apparently
 630           a few prototypes like that in existence) and therefore access to
 631           that required register must be emulated.
 632
 633 config HAS_TLS_REG
 634         bool
 635         depends on !TLS_REG_EMUL
 636         default y if SMP || CPU_32v7
 637         help
 638           This selects support for the CP15 thread register.
 639           It is defined to be available on some ARMv6 processors (including
 640           all SMP capable ARMv6's) or later processors.  User space may
 641           assume directly accessing that register and always obtain the
 642           expected value only on ARMv7 and above.
 643
 644 config NEEDS_SYSCALL_FOR_CMPXCHG
 645         bool
 646         help
 647           SMP on a pre-ARMv6 processor?  Well OK then.
 648           Forget about fast user space cmpxchg support.
 649           It is just not possible.
 650
 651 config OUTER_CACHE
 652         bool
 653         default n
 654
 655 config CACHE_L2X0
 656         bool
 657         select OUTER_CACHE