arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 config CPU_32
   4         bool
   5         default y
   6
   7 # Select CPU types depending on the architecture selected.  This selects
   8 # which CPUs we support in the kernel image, and the compiler instruction
   9 # optimiser behaviour.
  10
  11 # ARM610
  12 config CPU_ARM610
  13         bool "Support ARM610 processor"
  14         depends on ARCH_RPC
  15         select CPU_32v3
  16         select CPU_CACHE_V3
  17         select CPU_CACHE_VIVT
  18         select CPU_CP15_MMU
  19         select CPU_COPY_V3 if MMU
  20         select CPU_TLB_V3 if MMU
  21         select CPU_PABRT_NOIFAR
  22         help
  23           The ARM610 is the successor to the ARM3 processor
  24           and was produced by VLSI Technology Inc.
  25
  26           Say Y if you want support for the ARM610 processor.
  27           Otherwise, say N.
  28
  29 # ARM7TDMI
  30 config CPU_ARM7TDMI
  31         bool "Support ARM7TDMI processor"
  32         depends on !MMU
  33         select CPU_32v4T
  34         select CPU_ABRT_LV4T
  35         select CPU_CACHE_V4
  36         help
  37           A 32-bit RISC microprocessor based on the ARM7 processor core
  38           which has no memory control unit and cache.
  39
  40           Say Y if you want support for the ARM7TDMI processor.
  41           Otherwise, say N.
  42
  43 # ARM710
  44 config CPU_ARM710
  45         bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  46         default y if ARCH_CLPS7500
  47         select CPU_32v3
  48         select CPU_CACHE_V3
  49         select CPU_CACHE_VIVT
  50         select CPU_CP15_MMU
  51         select CPU_COPY_V3 if MMU
  52         select CPU_TLB_V3 if MMU
  53         select CPU_PABRT_NOIFAR
  54         help
  55           A 32-bit RISC microprocessor based on the ARM7 processor core
  56           designed by Advanced RISC Machines Ltd. The ARM710 is the
  57           successor to the ARM610 processor. It was released in
  58           July 1994 by VLSI Technology Inc.
  59
  60           Say Y if you want support for the ARM710 processor.
  61           Otherwise, say N.
  62
  63 # ARM720T
  64 config CPU_ARM720T
  65         bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  66         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  67         select CPU_32v4T
  68         select CPU_ABRT_LV4T
  69         select CPU_PABRT_NOIFAR
  70         select CPU_CACHE_V4
  71         select CPU_CACHE_VIVT
  72         select CPU_CP15_MMU
  73         select CPU_COPY_V4WT if MMU
  74         select CPU_TLB_V4WT if MMU
  75         help
  76           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  77           MMU built around an ARM7TDMI core.
  78
  79           Say Y if you want support for the ARM720T processor.
  80           Otherwise, say N.
  81
  82 # ARM740T
  83 config CPU_ARM740T
  84         bool "Support ARM740T processor" if ARCH_INTEGRATOR
  85         depends on !MMU
  86         select CPU_32v4T
  87         select CPU_ABRT_LV4T
  88         select CPU_CACHE_V3     # although the core is v4t
  89         select CPU_CP15_MPU
  90         help
  91           A 32-bit RISC processor with 8KB cache or 4KB variants,
  92           write buffer and MPU(Protection Unit) built around
  93           an ARM7TDMI core.
  94
  95           Say Y if you want support for the ARM740T processor.
  96           Otherwise, say N.
  97
  98 # ARM9TDMI
  99 config CPU_ARM9TDMI
 100         bool "Support ARM9TDMI processor"
 101         depends on !MMU
 102         select CPU_32v4T
 103         select CPU_ABRT_NOMMU
 104         select CPU_CACHE_V4
 105         help
 106           A 32-bit RISC microprocessor based on the ARM9 processor core
 107           which has no memory control unit and cache.
 108
 109           Say Y if you want support for the ARM9TDMI processor.
 110           Otherwise, say N.
 111
 112 # ARM920T
 113 config CPU_ARM920T
 114         bool "Support ARM920T processor"
 115         depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
 116         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
 117         select CPU_32v4T
 118         select CPU_ABRT_EV4T
 119         select CPU_PABRT_NOIFAR
 120         select CPU_CACHE_V4WT
 121         select CPU_CACHE_VIVT
 122         select CPU_CP15_MMU
 123         select CPU_COPY_V4WB if MMU
 124         select CPU_TLB_V4WBI if MMU
 125         help
 126           The ARM920T is licensed to be produced by numerous vendors,
 127           and is used in the Maverick EP9312 and the Samsung S3C2410.
 128
 129           More information on the Maverick EP9312 at
 130           <http://linuxdevices.com/products/PD2382866068.html>.
 131
 132           Say Y if you want support for the ARM920T processor.
 133           Otherwise, say N.
 134
 135 # ARM922T
 136 config CPU_ARM922T
 137         bool "Support ARM922T processor" if ARCH_INTEGRATOR
 138         depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
 139         default y if ARCH_LH7A40X || ARCH_KS8695
 140         select CPU_32v4T
 141         select CPU_ABRT_EV4T
 142         select CPU_PABRT_NOIFAR
 143         select CPU_CACHE_V4WT
 144         select CPU_CACHE_VIVT
 145         select CPU_CP15_MMU
 146         select CPU_COPY_V4WB if MMU
 147         select CPU_TLB_V4WBI if MMU
 148         help
 149           The ARM922T is a version of the ARM920T, but with smaller
 150           instruction and data caches. It is used in Altera's
 151           Excalibur XA device family and Micrel's KS8695 Centaur.
 152
 153           Say Y if you want support for the ARM922T processor.
 154           Otherwise, say N.
 155
 156 # ARM925T
 157 config CPU_ARM925T
 158         bool "Support ARM925T processor" if ARCH_OMAP1
 159         depends on ARCH_OMAP15XX
 160         default y if ARCH_OMAP15XX
 161         select CPU_32v4T
 162         select CPU_ABRT_EV4T
 163         select CPU_PABRT_NOIFAR
 164         select CPU_CACHE_V4WT
 165         select CPU_CACHE_VIVT
 166         select CPU_CP15_MMU
 167         select CPU_COPY_V4WB if MMU
 168         select CPU_TLB_V4WBI if MMU
 169         help
 170           The ARM925T is a mix between the ARM920T and ARM926T, but with
 171           different instruction and data caches. It is used in TI's OMAP
 172           device family.
 173
 174           Say Y if you want support for the ARM925T processor.
 175           Otherwise, say N.
 176
 177 # ARM926T
 178 config CPU_ARM926T
 179         bool "Support ARM926T processor"
 180         depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
 181         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
 182         select CPU_32v5
 183         select CPU_ABRT_EV5TJ
 184         select CPU_PABRT_NOIFAR
 185         select CPU_CACHE_VIVT
 186         select CPU_CP15_MMU
 187         select CPU_COPY_V4WB if MMU
 188         select CPU_TLB_V4WBI if MMU
 189         help
 190           This is a variant of the ARM920.  It has slightly different
 191           instruction sequences for cache and TLB operations.  Curiously,
 192           there is no documentation on it at the ARM corporate website.
 193
 194           Say Y if you want support for the ARM926T processor.
 195           Otherwise, say N.
 196
 197 # ARM940T
 198 config CPU_ARM940T
 199         bool "Support ARM940T processor" if ARCH_INTEGRATOR
 200         depends on !MMU
 201         select CPU_32v4T
 202         select CPU_ABRT_NOMMU
 203         select CPU_CACHE_VIVT
 204         select CPU_CP15_MPU
 205         help
 206           ARM940T is a member of the ARM9TDMI family of general-
 207           purpose microprocessors with MPU and separate 4KB
 208           instruction and 4KB data cases, each with a 4-word line
 209           length.
 210
 211           Say Y if you want support for the ARM940T processor.
 212           Otherwise, say N.
 213
 214 # ARM946E-S
 215 config CPU_ARM946E
 216         bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
 217         depends on !MMU
 218         select CPU_32v5
 219         select CPU_ABRT_NOMMU
 220         select CPU_CACHE_VIVT
 221         select CPU_CP15_MPU
 222         help
 223           ARM946E-S is a member of the ARM9E-S family of high-
 224           performance, 32-bit system-on-chip processor solutions.
 225           The TCM and ARMv5TE 32-bit instruction set is supported.
 226
 227           Say Y if you want support for the ARM946E-S processor.
 228           Otherwise, say N.
 229
 230 # ARM1020 - needs validating
 231 config CPU_ARM1020
 232         bool "Support ARM1020T (rev 0) processor"
 233         depends on ARCH_INTEGRATOR
 234         select CPU_32v5
 235         select CPU_ABRT_EV4T
 236         select CPU_PABRT_NOIFAR
 237         select CPU_CACHE_V4WT
 238         select CPU_CACHE_VIVT
 239         select CPU_CP15_MMU
 240         select CPU_COPY_V4WB if MMU
 241         select CPU_TLB_V4WBI if MMU
 242         help
 243           The ARM1020 is the 32K cached version of the ARM10 processor,
 244           with an addition of a floating-point unit.
 245
 246           Say Y if you want support for the ARM1020 processor.
 247           Otherwise, say N.
 248
 249 # ARM1020E - needs validating
 250 config CPU_ARM1020E
 251         bool "Support ARM1020E processor"
 252         depends on ARCH_INTEGRATOR
 253         select CPU_32v5
 254         select CPU_ABRT_EV4T
 255         select CPU_PABRT_NOIFAR
 256         select CPU_CACHE_V4WT
 257         select CPU_CACHE_VIVT
 258         select CPU_CP15_MMU
 259         select CPU_COPY_V4WB if MMU
 260         select CPU_TLB_V4WBI if MMU
 261         depends on n
 262
 263 # ARM1022E
 264 config CPU_ARM1022
 265         bool "Support ARM1022E processor"
 266         depends on ARCH_INTEGRATOR
 267         select CPU_32v5
 268         select CPU_ABRT_EV4T
 269         select CPU_PABRT_NOIFAR
 270         select CPU_CACHE_VIVT
 271         select CPU_CP15_MMU
 272         select CPU_COPY_V4WB if MMU # can probably do better
 273         select CPU_TLB_V4WBI if MMU
 274         help
 275           The ARM1022E is an implementation of the ARMv5TE architecture
 276           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 277           embedded trace macrocell, and a floating-point unit.
 278
 279           Say Y if you want support for the ARM1022E processor.
 280           Otherwise, say N.
 281
 282 # ARM1026EJ-S
 283 config CPU_ARM1026
 284         bool "Support ARM1026EJ-S processor"
 285         depends on ARCH_INTEGRATOR
 286         select CPU_32v5
 287         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 288         select CPU_PABRT_NOIFAR
 289         select CPU_CACHE_VIVT
 290         select CPU_CP15_MMU
 291         select CPU_COPY_V4WB if MMU # can probably do better
 292         select CPU_TLB_V4WBI if MMU
 293         help
 294           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 295           based upon the ARM10 integer core.
 296
 297           Say Y if you want support for the ARM1026EJ-S processor.
 298           Otherwise, say N.
 299
 300 # SA110
 301 config CPU_SA110
 302         bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
 303         default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
 304         select CPU_32v3 if ARCH_RPC
 305         select CPU_32v4 if !ARCH_RPC
 306         select CPU_ABRT_EV4
 307         select CPU_PABRT_NOIFAR
 308         select CPU_CACHE_V4WB
 309         select CPU_CACHE_VIVT
 310         select CPU_CP15_MMU
 311         select CPU_COPY_V4WB if MMU
 312         select CPU_TLB_V4WB if MMU
 313         help
 314           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 315           is available at five speeds ranging from 100 MHz to 233 MHz.
 316           More information is available at
 317           <http://developer.intel.com/design/strong/sa110.htm>.
 318
 319           Say Y if you want support for the SA-110 processor.
 320           Otherwise, say N.
 321
 322 # SA1100
 323 config CPU_SA1100
 324         bool
 325         depends on ARCH_SA1100
 326         default y
 327         select CPU_32v4
 328         select CPU_ABRT_EV4
 329         select CPU_PABRT_NOIFAR
 330         select CPU_CACHE_V4WB
 331         select CPU_CACHE_VIVT
 332         select CPU_CP15_MMU
 333         select CPU_TLB_V4WB if MMU
 334
 335 # XScale
 336 config CPU_XSCALE
 337         bool
 338         depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
 339         default y
 340         select CPU_32v5
 341         select CPU_ABRT_EV5T
 342         select CPU_PABRT_NOIFAR
 343         select CPU_CACHE_VIVT
 344         select CPU_CP15_MMU
 345         select CPU_TLB_V4WBI if MMU
 346
 347 # XScale Core Version 3
 348 config CPU_XSC3
 349         bool
 350         depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
 351         default y
 352         select CPU_32v5
 353         select CPU_ABRT_EV5T
 354         select CPU_CACHE_VIVT
 355         select CPU_CP15_MMU
 356         select CPU_TLB_V4WBI if MMU
 357         select IO_36
 358
 359 # Feroceon
 360 config CPU_FEROCEON
 361         bool
 362         depends on ARCH_ORION
 363         default y
 364         select CPU_32v5
 365         select CPU_ABRT_EV5T
 366         select CPU_PABRT_NOIFAR
 367         select CPU_CACHE_VIVT
 368         select CPU_CP15_MMU
 369         select CPU_COPY_V4WB if MMU
 370         select CPU_TLB_V4WBI if MMU
 371
 372 config CPU_FEROCEON_OLD_ID
 373         bool "Accept early Feroceon cores with an ARM926 ID"
 374         depends on CPU_FEROCEON && !CPU_ARM926T
 375         default y
 376         help
 377           This enables the usage of some old Feroceon cores
 378           for which the CPU ID is equal to the ARM926 ID.
 379           Relevant for Feroceon-1850 and early Feroceon-2850.
 380
 381 # ARMv6
 382 config CPU_V6
 383         bool "Support ARM V6 processor"
 384         depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
 385         default y if ARCH_MX3
 386         default y if ARCH_MSM7X00A
 387         select CPU_32v6
 388         select CPU_ABRT_EV6
 389         select CPU_PABRT_NOIFAR
 390         select CPU_CACHE_V6
 391         select CPU_CACHE_VIPT
 392         select CPU_CP15_MMU
 393         select CPU_HAS_ASID if MMU
 394         select CPU_COPY_V6 if MMU
 395         select CPU_TLB_V6 if MMU
 396
 397 # ARMv6k
 398 config CPU_32v6K
 399         bool "Support ARM V6K processor extensions" if !SMP
 400         depends on CPU_V6
 401         default y if SMP && !ARCH_MX3
 402         help
 403           Say Y here if your ARMv6 processor supports the 'K' extension.
 404           This enables the kernel to use some instructions not present
 405           on previous processors, and as such a kernel build with this
 406           enabled will not boot on processors with do not support these
 407           instructions.
 408
 409 # ARMv7
 410 config CPU_V7
 411         bool "Support ARM V7 processor"
 412         depends on ARCH_INTEGRATOR
 413         select CPU_32v6K
 414         select CPU_32v7
 415         select CPU_ABRT_EV7
 416         select CPU_PABRT_IFAR
 417         select CPU_CACHE_V7
 418         select CPU_CACHE_VIPT
 419         select CPU_CP15_MMU
 420         select CPU_HAS_ASID if MMU
 421         select CPU_COPY_V6 if MMU
 422         select CPU_TLB_V7 if MMU
 423
 424 # Figure out what processor architecture version we should be using.
 425 # This defines the compiler instruction set which depends on the machine type.
 426 config CPU_32v3
 427         bool
 428         select TLS_REG_EMUL if SMP || !MMU
 429         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 430
 431 config CPU_32v4
 432         bool
 433         select TLS_REG_EMUL if SMP || !MMU
 434         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 435
 436 config CPU_32v4T
 437         bool
 438         select TLS_REG_EMUL if SMP || !MMU
 439         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 440
 441 config CPU_32v5
 442         bool
 443         select TLS_REG_EMUL if SMP || !MMU
 444         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 445
 446 config CPU_32v6
 447         bool
 448         select TLS_REG_EMUL if !CPU_32v6K && !MMU
 449
 450 config CPU_32v7
 451         bool
 452
 453 # The abort model
 454 config CPU_ABRT_NOMMU
 455         bool
 456
 457 config CPU_ABRT_EV4
 458         bool
 459
 460 config CPU_ABRT_EV4T
 461         bool
 462
 463 config CPU_ABRT_LV4T
 464         bool
 465
 466 config CPU_ABRT_EV5T
 467         bool
 468
 469 config CPU_ABRT_EV5TJ
 470         bool
 471
 472 config CPU_ABRT_EV6
 473         bool
 474
 475 config CPU_ABRT_EV7
 476         bool
 477
 478 config CPU_PABRT_IFAR
 479         bool
 480
 481 config CPU_PABRT_NOIFAR
 482         bool
 483
 484 # The cache model
 485 config CPU_CACHE_V3
 486         bool
 487
 488 config CPU_CACHE_V4
 489         bool
 490
 491 config CPU_CACHE_V4WT
 492         bool
 493
 494 config CPU_CACHE_V4WB
 495         bool
 496
 497 config CPU_CACHE_V6
 498         bool
 499
 500 config CPU_CACHE_V7
 501         bool
 502
 503 config CPU_CACHE_VIVT
 504         bool
 505
 506 config CPU_CACHE_VIPT
 507         bool
 508
 509 if MMU
 510 # The copy-page model
 511 config CPU_COPY_V3
 512         bool
 513
 514 config CPU_COPY_V4WT
 515         bool
 516
 517 config CPU_COPY_V4WB
 518         bool
 519
 520 config CPU_COPY_V6
 521         bool
 522
 523 # This selects the TLB model
 524 config CPU_TLB_V3
 525         bool
 526         help
 527           ARM Architecture Version 3 TLB.
 528
 529 config CPU_TLB_V4WT
 530         bool
 531         help
 532           ARM Architecture Version 4 TLB with writethrough cache.
 533
 534 config CPU_TLB_V4WB
 535         bool
 536         help
 537           ARM Architecture Version 4 TLB with writeback cache.
 538
 539 config CPU_TLB_V4WBI
 540         bool
 541         help
 542           ARM Architecture Version 4 TLB with writeback cache and invalidate
 543           instruction cache entry.
 544
 545 config CPU_TLB_V6
 546         bool
 547
 548 config CPU_TLB_V7
 549         bool
 550
 551 endif
 552
 553 config CPU_HAS_ASID
 554         bool
 555         help
 556           This indicates whether the CPU has the ASID register; used to
 557           tag TLB and possibly cache entries.
 558
 559 config CPU_CP15
 560         bool
 561         help
 562           Processor has the CP15 register.
 563
 564 config CPU_CP15_MMU
 565         bool
 566         select CPU_CP15
 567         help
 568           Processor has the CP15 register, which has MMU related registers.
 569
 570 config CPU_CP15_MPU
 571         bool
 572         select CPU_CP15
 573         help
 574           Processor has the CP15 register, which has MPU related registers.
 575
 576 #
 577 # CPU supports 36-bit I/O
 578 #
 579 config IO_36
 580         bool
 581
 582 comment "Processor Features"
 583
 584 config ARM_THUMB
 585         bool "Support Thumb user binaries"
 586         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
 587         default y
 588         help
 589           Say Y if you want to include kernel support for running user space
 590           Thumb binaries.
 591
 592           The Thumb instruction set is a compressed form of the standard ARM
 593           instruction set resulting in smaller binaries at the expense of
 594           slightly less efficient code.
 595
 596           If you don't know what this all is, saying Y is a safe choice.
 597
 598 config ARM_THUMBEE
 599         bool "Enable ThumbEE CPU extension"
 600         depends on CPU_V7
 601         help
 602           Say Y here if you have a CPU with the ThumbEE extension and code to
 603           make use of it. Say N for code that can run on CPUs without ThumbEE.
 604
 605 config CPU_BIG_ENDIAN
 606         bool "Build big-endian kernel"
 607         depends on ARCH_SUPPORTS_BIG_ENDIAN
 608         help
 609           Say Y if you plan on running a kernel in big-endian mode.
 610           Note that your board must be properly built and your board
 611           port must properly enable any big-endian related features
 612           of your chipset/board/processor.
 613
 614 config CPU_HIGH_VECTOR
 615         depends on !MMU && CPU_CP15 && !CPU_ARM740T
 616         bool "Select the High exception vector"
 617         default n
 618         help
 619           Say Y here to select high exception vector(0xFFFF0000~).
 620           The exception vector can be vary depending on the platform
 621           design in nommu mode. If your platform needs to select
 622           high exception vector, say Y.
 623           Otherwise or if you are unsure, say N, and the low exception
 624           vector (0x00000000~) will be used.
 625
 626 config CPU_ICACHE_DISABLE
 627         bool "Disable I-Cache (I-bit)"
 628         depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 629         help
 630           Say Y here to disable the processor instruction cache. Unless
 631           you have a reason not to or are unsure, say N.
 632
 633 config CPU_DCACHE_DISABLE
 634         bool "Disable D-Cache (C-bit)"
 635         depends on CPU_CP15
 636         help
 637           Say Y here to disable the processor data cache. Unless
 638           you have a reason not to or are unsure, say N.
 639
 640 config CPU_DCACHE_SIZE
 641         hex
 642         depends on CPU_ARM740T || CPU_ARM946E
 643         default 0x00001000 if CPU_ARM740T
 644         default 0x00002000 # default size for ARM946E-S
 645         help
 646           Some cores are synthesizable to have various sized cache. For
 647           ARM946E-S case, it can vary from 0KB to 1MB.
 648           To support such cache operations, it is efficient to know the size
 649           before compile time.
 650           If your SoC is configured to have a different size, define the value
 651           here with proper conditions.
 652
 653 config CPU_DCACHE_WRITETHROUGH
 654         bool "Force write through D-cache"
 655         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE
 656         default y if CPU_ARM925T
 657         help
 658           Say Y here to use the data cache in writethrough mode. Unless you
 659           specifically require this or are unsure, say N.
 660
 661 config CPU_CACHE_ROUND_ROBIN
 662         bool "Round robin I and D cache replacement algorithm"
 663         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 664         help
 665           Say Y here to use the predictable round-robin cache replacement
 666           policy.  Unless you specifically require this or are unsure, say N.
 667
 668 config CPU_BPREDICT_DISABLE
 669         bool "Disable branch prediction"
 670         depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
 671         help
 672           Say Y here to disable branch prediction.  If unsure, say N.
 673
 674 config TLS_REG_EMUL
 675         bool
 676         help
 677           An SMP system using a pre-ARMv6 processor (there are apparently
 678           a few prototypes like that in existence) and therefore access to
 679           that required register must be emulated.
 680
 681 config HAS_TLS_REG
 682         bool
 683         depends on !TLS_REG_EMUL
 684         default y if SMP || CPU_32v7
 685         help
 686           This selects support for the CP15 thread register.
 687           It is defined to be available on some ARMv6 processors (including
 688           all SMP capable ARMv6's) or later processors.  User space may
 689           assume directly accessing that register and always obtain the
 690           expected value only on ARMv7 and above.
 691
 692 config NEEDS_SYSCALL_FOR_CMPXCHG
 693         bool
 694         help
 695           SMP on a pre-ARMv6 processor?  Well OK then.
 696           Forget about fast user space cmpxchg support.
 697           It is just not possible.
 698
 699 config OUTER_CACHE
 700         bool
 701         default n
 702
 703 config CACHE_L2X0
 704         bool
 705         select OUTER_CACHE