arch/arm/mach-ux500/cpu.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/io.h>
  11 #include <linux/clk.h>
  12
  13 #include <asm/cacheflush.h>
  14 #include <asm/hardware/cache-l2x0.h>
  15 #include <asm/hardware/gic.h>
  16 #include <asm/mach/map.h>
  17 #include <asm/localtimer.h>
  18
  19 #include <plat/mtu.h>
  20 #include <mach/hardware.h>
  21 #include <mach/setup.h>
  22 #include <mach/devices.h>
  23
  24 #include "clock.h"
  25
  26 static struct map_desc ux500_io_desc[] __initdata = {
  27         __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K),
  28         __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K),
  29
  30         __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K),
  31         __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K),
  32         __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K),
  33         __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K),
  34         __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K),
  35
  36         __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K),
  37         __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K),
  38         __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K),
  39         __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K),
  40         __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K),
  41
  42         __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K),
  43         __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K),
  44
  45         __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
  46 };
  47
  48 static struct amba_device *ux500_amba_devs[] __initdata = {
  49         &ux500_pl031_device,
  50 };
  51
  52 void __init ux500_map_io(void)
  53 {
  54         iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
  55 }
  56
  57 void __init ux500_init_devices(void)
  58 {
  59         amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs));
  60 }
  61
  62 void __init ux500_init_irq(void)
  63 {
  64         gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
  65         gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
  66
  67         /*
  68          * Init clocks here so that they are available for system timer
  69          * initialization.
  70          */
  71         clk_init();
  72 }
  73
  74 #ifdef CONFIG_CACHE_L2X0
  75 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
  76 {
  77         /* wait for the operation to complete */
  78         while (readl(reg) & mask)
  79                 ;
  80 }
  81
  82 static inline void ux500_cache_sync(void)
  83 {
  84         void __iomem *base = __io_address(UX500_L2CC_BASE);
  85         writel(0, base + L2X0_CACHE_SYNC);
  86         ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
  87 }
  88
  89 /*
  90  * The L2 cache cannot be turned off in the non-secure world.
  91  * Dummy until a secure service is in place.
  92  */
  93 static void ux500_l2x0_disable(void)
  94 {
  95 }
  96
  97 /*
  98  * This is only called when doing a kexec, just after turning off the L2
  99  * and L1 cache, and it is surrounded by a spinlock in the generic version.
 100  * However, we're not really turning off the L2 cache right now and the
 101  * PL310 does not support exclusive accesses (used to implement the spinlock).
 102  * So, the invalidation needs to be done without the spinlock.
 103  */
 104 static void ux500_l2x0_inv_all(void)
 105 {
 106         void __iomem *l2x0_base = __io_address(UX500_L2CC_BASE);
 107         uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
 108
 109         /* invalidate all ways */
 110         writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
 111         ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
 112         ux500_cache_sync();
 113 }
 114
 115 static int ux500_l2x0_init(void)
 116 {
 117         void __iomem *l2x0_base;
 118
 119         l2x0_base = __io_address(UX500_L2CC_BASE);
 120
 121         /* 64KB way size, 8 way associativity, force WA */
 122         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 123
 124         /* Override invalidate function */
 125         outer_cache.disable = ux500_l2x0_disable;
 126         outer_cache.inv_all = ux500_l2x0_inv_all;
 127
 128         return 0;
 129 }
 130 early_initcall(ux500_l2x0_init);
 131 #endif
 132
 133 static void __init ux500_timer_init(void)
 134 {
 135 #ifdef CONFIG_LOCAL_TIMERS
 136         /* Setup the local timer base */
 137         twd_base = __io_address(UX500_TWD_BASE);
 138 #endif
 139         /* Setup the MTU base */
 140         if (cpu_is_u8500ed())
 141                 mtu_base = __io_address(U8500_MTU0_BASE_ED);
 142         else
 143                 mtu_base = __io_address(UX500_MTU0_BASE);
 144
 145         nmdk_timer_init();
 146 }
 147
 148 struct sys_timer ux500_timer = {
 149         .init   = ux500_timer_init,
 150 };