arch/arm/mach-shmobile/smp-r8a7779.c

   1 /*
   2  * SMP support for R-Mobile / SH-Mobile - r8a7779 portion
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/smp.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <linux/delay.h>
  26 #include <mach/common.h>
  27 #include <mach/r8a7779.h>
  28 #include <asm/cacheflush.h>
  29 #include <asm/smp_plat.h>
  30 #include <asm/smp_scu.h>
  31 #include <asm/smp_twd.h>
  32
  33 #define AVECR IOMEM(0xfe700040)
  34 #define R8A7779_SCU_BASE 0xf0000000
  35
  36 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
  37         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
  38         .chan_bit = 1, /* ARM1 */
  39         .isr_bit = 1, /* ARM1 */
  40 };
  41
  42 static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
  43         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
  44         .chan_bit = 2, /* ARM2 */
  45         .isr_bit = 2, /* ARM2 */
  46 };
  47
  48 static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
  49         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
  50         .chan_bit = 3, /* ARM3 */
  51         .isr_bit = 3, /* ARM3 */
  52 };
  53
  54 static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
  55         [1] = &r8a7779_ch_cpu1,
  56         [2] = &r8a7779_ch_cpu2,
  57         [3] = &r8a7779_ch_cpu3,
  58 };
  59
  60 #ifdef CONFIG_HAVE_ARM_TWD
  61 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
  62 void __init r8a7779_register_twd(void)
  63 {
  64         twd_local_timer_register(&twd_local_timer);
  65 }
  66 #endif
  67
  68 static int r8a7779_platform_cpu_kill(unsigned int cpu)
  69 {
  70         struct r8a7779_pm_ch *ch = NULL;
  71         int ret = -EIO;
  72
  73         cpu = cpu_logical_map(cpu);
  74
  75         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
  76                 ch = r8a7779_ch_cpu[cpu];
  77
  78         if (ch)
  79                 ret = r8a7779_sysc_power_down(ch);
  80
  81         return ret ? ret : 1;
  82 }
  83
  84 static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
  85 {
  86         struct r8a7779_pm_ch *ch = NULL;
  87         int ret = -EIO;
  88
  89         cpu = cpu_logical_map(cpu);
  90
  91         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
  92                 ch = r8a7779_ch_cpu[cpu];
  93
  94         if (ch)
  95                 ret = r8a7779_sysc_power_up(ch);
  96
  97         return ret;
  98 }
  99
 100 static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 101 {
 102         scu_enable(shmobile_scu_base);
 103
 104         /* Map the reset vector (in headsmp-scu.S) */
 105         __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
 106
 107         /* enable cache coherency on booting CPU */
 108         scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 109
 110         r8a7779_pm_init();
 111
 112         /* power off secondary CPUs */
 113         r8a7779_platform_cpu_kill(1);
 114         r8a7779_platform_cpu_kill(2);
 115         r8a7779_platform_cpu_kill(3);
 116 }
 117
 118 static void __init r8a7779_smp_init_cpus(void)
 119 {
 120         /* setup r8a7779 specific SCU base */
 121         shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
 122
 123         shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
 124 }
 125
 126 #ifdef CONFIG_HOTPLUG_CPU
 127 static int r8a7779_scu_psr_core_disabled(int cpu)
 128 {
 129         unsigned long mask = 3 << (cpu * 8);
 130
 131         if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
 132                 return 1;
 133
 134         return 0;
 135 }
 136
 137 static int r8a7779_cpu_kill(unsigned int cpu)
 138 {
 139         int k;
 140
 141         /* this function is running on another CPU than the offline target,
 142          * here we need wait for shutdown code in platform_cpu_die() to
 143          * finish before asking SoC-specific code to power off the CPU core.
 144          */
 145         for (k = 0; k < 1000; k++) {
 146                 if (r8a7779_scu_psr_core_disabled(cpu))
 147                         return r8a7779_platform_cpu_kill(cpu);
 148
 149                 mdelay(1);
 150         }
 151
 152         return 0;
 153 }
 154
 155 static void r8a7779_cpu_die(unsigned int cpu)
 156 {
 157         dsb();
 158         flush_cache_all();
 159
 160         /* disable cache coherency */
 161         scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
 162
 163         /* Endless loop until power off from r8a7779_cpu_kill() */
 164         while (1)
 165                 cpu_do_idle();
 166 }
 167
 168 static int r8a7779_cpu_disable(unsigned int cpu)
 169 {
 170         /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
 171         return cpu == 0 ? -EPERM : 0;
 172 }
 173 #endif /* CONFIG_HOTPLUG_CPU */
 174
 175 struct smp_operations r8a7779_smp_ops  __initdata = {
 176         .smp_init_cpus          = r8a7779_smp_init_cpus,
 177         .smp_prepare_cpus       = r8a7779_smp_prepare_cpus,
 178         .smp_boot_secondary     = r8a7779_boot_secondary,
 179 #ifdef CONFIG_HOTPLUG_CPU
 180         .cpu_kill               = r8a7779_cpu_kill,
 181         .cpu_die                = r8a7779_cpu_die,
 182         .cpu_disable            = r8a7779_cpu_disable,
 183 #endif
 184 };