arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/delay.h>
  26 #include <linux/input.h>
  27 #include <linux/io.h>
  28 #include <linux/serial_sci.h>
  29 #include <linux/sh_dma.h>
  30 #include <linux/sh_intc.h>
  31 #include <linux/sh_timer.h>
  32 #include <mach/hardware.h>
  33 #include <mach/sh7372.h>
  34 #include <asm/mach-types.h>
  35 #include <asm/mach/arch.h>
  36
  37 /* SCIFA0 */
  38 static struct plat_sci_port scif0_platform_data = {
  39         .mapbase        = 0xe6c40000,
  40         .flags          = UPF_BOOT_AUTOCONF,
  41         .scscr          = SCSCR_RE | SCSCR_TE,
  42         .scbrr_algo_id  = SCBRR_ALGO_4,
  43         .type           = PORT_SCIFA,
  44         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  45                             evt2irq(0x0c00), evt2irq(0x0c00) },
  46 };
  47
  48 static struct platform_device scif0_device = {
  49         .name           = "sh-sci",
  50         .id             = 0,
  51         .dev            = {
  52                 .platform_data  = &scif0_platform_data,
  53         },
  54 };
  55
  56 /* SCIFA1 */
  57 static struct plat_sci_port scif1_platform_data = {
  58         .mapbase        = 0xe6c50000,
  59         .flags          = UPF_BOOT_AUTOCONF,
  60         .scscr          = SCSCR_RE | SCSCR_TE,
  61         .scbrr_algo_id  = SCBRR_ALGO_4,
  62         .type           = PORT_SCIFA,
  63         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  64                             evt2irq(0x0c20), evt2irq(0x0c20) },
  65 };
  66
  67 static struct platform_device scif1_device = {
  68         .name           = "sh-sci",
  69         .id             = 1,
  70         .dev            = {
  71                 .platform_data  = &scif1_platform_data,
  72         },
  73 };
  74
  75 /* SCIFA2 */
  76 static struct plat_sci_port scif2_platform_data = {
  77         .mapbase        = 0xe6c60000,
  78         .flags          = UPF_BOOT_AUTOCONF,
  79         .scscr          = SCSCR_RE | SCSCR_TE,
  80         .scbrr_algo_id  = SCBRR_ALGO_4,
  81         .type           = PORT_SCIFA,
  82         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
  83                             evt2irq(0x0c40), evt2irq(0x0c40) },
  84 };
  85
  86 static struct platform_device scif2_device = {
  87         .name           = "sh-sci",
  88         .id             = 2,
  89         .dev            = {
  90                 .platform_data  = &scif2_platform_data,
  91         },
  92 };
  93
  94 /* SCIFA3 */
  95 static struct plat_sci_port scif3_platform_data = {
  96         .mapbase        = 0xe6c70000,
  97         .flags          = UPF_BOOT_AUTOCONF,
  98         .scscr          = SCSCR_RE | SCSCR_TE,
  99         .scbrr_algo_id  = SCBRR_ALGO_4,
 100         .type           = PORT_SCIFA,
 101         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 102                             evt2irq(0x0c60), evt2irq(0x0c60) },
 103 };
 104
 105 static struct platform_device scif3_device = {
 106         .name           = "sh-sci",
 107         .id             = 3,
 108         .dev            = {
 109                 .platform_data  = &scif3_platform_data,
 110         },
 111 };
 112
 113 /* SCIFA4 */
 114 static struct plat_sci_port scif4_platform_data = {
 115         .mapbase        = 0xe6c80000,
 116         .flags          = UPF_BOOT_AUTOCONF,
 117         .scscr          = SCSCR_RE | SCSCR_TE,
 118         .scbrr_algo_id  = SCBRR_ALGO_4,
 119         .type           = PORT_SCIFA,
 120         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 121                             evt2irq(0x0d20), evt2irq(0x0d20) },
 122 };
 123
 124 static struct platform_device scif4_device = {
 125         .name           = "sh-sci",
 126         .id             = 4,
 127         .dev            = {
 128                 .platform_data  = &scif4_platform_data,
 129         },
 130 };
 131
 132 /* SCIFA5 */
 133 static struct plat_sci_port scif5_platform_data = {
 134         .mapbase        = 0xe6cb0000,
 135         .flags          = UPF_BOOT_AUTOCONF,
 136         .scscr          = SCSCR_RE | SCSCR_TE,
 137         .scbrr_algo_id  = SCBRR_ALGO_4,
 138         .type           = PORT_SCIFA,
 139         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 140                             evt2irq(0x0d40), evt2irq(0x0d40) },
 141 };
 142
 143 static struct platform_device scif5_device = {
 144         .name           = "sh-sci",
 145         .id             = 5,
 146         .dev            = {
 147                 .platform_data  = &scif5_platform_data,
 148         },
 149 };
 150
 151 /* SCIFB */
 152 static struct plat_sci_port scif6_platform_data = {
 153         .mapbase        = 0xe6c30000,
 154         .flags          = UPF_BOOT_AUTOCONF,
 155         .scscr          = SCSCR_RE | SCSCR_TE,
 156         .scbrr_algo_id  = SCBRR_ALGO_4,
 157         .type           = PORT_SCIFB,
 158         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 159                             evt2irq(0x0d60), evt2irq(0x0d60) },
 160 };
 161
 162 static struct platform_device scif6_device = {
 163         .name           = "sh-sci",
 164         .id             = 6,
 165         .dev            = {
 166                 .platform_data  = &scif6_platform_data,
 167         },
 168 };
 169
 170 /* CMT */
 171 static struct sh_timer_config cmt10_platform_data = {
 172         .name = "CMT10",
 173         .channel_offset = 0x10,
 174         .timer_bit = 0,
 175         .clockevent_rating = 125,
 176         .clocksource_rating = 125,
 177 };
 178
 179 static struct resource cmt10_resources[] = {
 180         [0] = {
 181                 .name   = "CMT10",
 182                 .start  = 0xe6138010,
 183                 .end    = 0xe613801b,
 184                 .flags  = IORESOURCE_MEM,
 185         },
 186         [1] = {
 187                 .start  = evt2irq(0x0b00), /* CMT1_CMT10 */
 188                 .flags  = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct platform_device cmt10_device = {
 193         .name           = "sh_cmt",
 194         .id             = 10,
 195         .dev = {
 196                 .platform_data  = &cmt10_platform_data,
 197         },
 198         .resource       = cmt10_resources,
 199         .num_resources  = ARRAY_SIZE(cmt10_resources),
 200 };
 201
 202 /* TMU */
 203 static struct sh_timer_config tmu00_platform_data = {
 204         .name = "TMU00",
 205         .channel_offset = 0x4,
 206         .timer_bit = 0,
 207         .clockevent_rating = 200,
 208 };
 209
 210 static struct resource tmu00_resources[] = {
 211         [0] = {
 212                 .name   = "TMU00",
 213                 .start  = 0xfff60008,
 214                 .end    = 0xfff60013,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217         [1] = {
 218                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 219                 .flags  = IORESOURCE_IRQ,
 220         },
 221 };
 222
 223 static struct platform_device tmu00_device = {
 224         .name           = "sh_tmu",
 225         .id             = 0,
 226         .dev = {
 227                 .platform_data  = &tmu00_platform_data,
 228         },
 229         .resource       = tmu00_resources,
 230         .num_resources  = ARRAY_SIZE(tmu00_resources),
 231 };
 232
 233 static struct sh_timer_config tmu01_platform_data = {
 234         .name = "TMU01",
 235         .channel_offset = 0x10,
 236         .timer_bit = 1,
 237         .clocksource_rating = 200,
 238 };
 239
 240 static struct resource tmu01_resources[] = {
 241         [0] = {
 242                 .name   = "TMU01",
 243                 .start  = 0xfff60014,
 244                 .end    = 0xfff6001f,
 245                 .flags  = IORESOURCE_MEM,
 246         },
 247         [1] = {
 248                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 249                 .flags  = IORESOURCE_IRQ,
 250         },
 251 };
 252
 253 static struct platform_device tmu01_device = {
 254         .name           = "sh_tmu",
 255         .id             = 1,
 256         .dev = {
 257                 .platform_data  = &tmu01_platform_data,
 258         },
 259         .resource       = tmu01_resources,
 260         .num_resources  = ARRAY_SIZE(tmu01_resources),
 261 };
 262
 263 /* I2C */
 264 static struct resource iic0_resources[] = {
 265         [0] = {
 266                 .name   = "IIC0",
 267                 .start  = 0xFFF20000,
 268                 .end    = 0xFFF20425 - 1,
 269                 .flags  = IORESOURCE_MEM,
 270         },
 271         [1] = {
 272                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 273                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 274                 .flags  = IORESOURCE_IRQ,
 275         },
 276 };
 277
 278 static struct platform_device iic0_device = {
 279         .name           = "i2c-sh_mobile",
 280         .id             = 0, /* "i2c0" clock */
 281         .num_resources  = ARRAY_SIZE(iic0_resources),
 282         .resource       = iic0_resources,
 283 };
 284
 285 static struct resource iic1_resources[] = {
 286         [0] = {
 287                 .name   = "IIC1",
 288                 .start  = 0xE6C20000,
 289                 .end    = 0xE6C20425 - 1,
 290                 .flags  = IORESOURCE_MEM,
 291         },
 292         [1] = {
 293                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 294                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 295                 .flags  = IORESOURCE_IRQ,
 296         },
 297 };
 298
 299 static struct platform_device iic1_device = {
 300         .name           = "i2c-sh_mobile",
 301         .id             = 1, /* "i2c1" clock */
 302         .num_resources  = ARRAY_SIZE(iic1_resources),
 303         .resource       = iic1_resources,
 304 };
 305
 306 /* DMA */
 307 /* Transmit sizes and respective CHCR register values */
 308 enum {
 309         XMIT_SZ_8BIT            = 0,
 310         XMIT_SZ_16BIT           = 1,
 311         XMIT_SZ_32BIT           = 2,
 312         XMIT_SZ_64BIT           = 7,
 313         XMIT_SZ_128BIT          = 3,
 314         XMIT_SZ_256BIT          = 4,
 315         XMIT_SZ_512BIT          = 5,
 316 };
 317
 318 /* log2(size / 8) - used to calculate number of transfers */
 319 #define TS_SHIFT {                      \
 320         [XMIT_SZ_8BIT]          = 0,    \
 321         [XMIT_SZ_16BIT]         = 1,    \
 322         [XMIT_SZ_32BIT]         = 2,    \
 323         [XMIT_SZ_64BIT]         = 3,    \
 324         [XMIT_SZ_128BIT]        = 4,    \
 325         [XMIT_SZ_256BIT]        = 5,    \
 326         [XMIT_SZ_512BIT]        = 6,    \
 327 }
 328
 329 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
 330                          (((i) & 0xc) << (20 - 2)))
 331
 332 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 333         {
 334                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 335                 .addr           = 0xe6c40020,
 336                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 337                 .mid_rid        = 0x21,
 338         }, {
 339                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 340                 .addr           = 0xe6c40024,
 341                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 342                 .mid_rid        = 0x22,
 343         }, {
 344                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 345                 .addr           = 0xe6c50020,
 346                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 347                 .mid_rid        = 0x25,
 348         }, {
 349                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 350                 .addr           = 0xe6c50024,
 351                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 352                 .mid_rid        = 0x26,
 353         }, {
 354                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 355                 .addr           = 0xe6c60020,
 356                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 357                 .mid_rid        = 0x29,
 358         }, {
 359                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 360                 .addr           = 0xe6c60024,
 361                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 362                 .mid_rid        = 0x2a,
 363         }, {
 364                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 365                 .addr           = 0xe6c70020,
 366                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 367                 .mid_rid        = 0x2d,
 368         }, {
 369                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 370                 .addr           = 0xe6c70024,
 371                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 372                 .mid_rid        = 0x2e,
 373         }, {
 374                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 375                 .addr           = 0xe6c80020,
 376                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 377                 .mid_rid        = 0x39,
 378         }, {
 379                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 380                 .addr           = 0xe6c80024,
 381                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 382                 .mid_rid        = 0x3a,
 383         }, {
 384                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 385                 .addr           = 0xe6cb0020,
 386                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 387                 .mid_rid        = 0x35,
 388         }, {
 389                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 390                 .addr           = 0xe6cb0024,
 391                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 392                 .mid_rid        = 0x36,
 393         }, {
 394                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 395                 .addr           = 0xe6c30040,
 396                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 397                 .mid_rid        = 0x3d,
 398         }, {
 399                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 400                 .addr           = 0xe6c30060,
 401                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 402                 .mid_rid        = 0x3e,
 403         }, {
 404                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 405                 .addr           = 0xe6850030,
 406                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 407                 .mid_rid        = 0xc1,
 408         }, {
 409                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 410                 .addr           = 0xe6850030,
 411                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 412                 .mid_rid        = 0xc2,
 413         }, {
 414                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 415                 .addr           = 0xe6860030,
 416                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 417                 .mid_rid        = 0xc9,
 418         }, {
 419                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 420                 .addr           = 0xe6860030,
 421                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 422                 .mid_rid        = 0xca,
 423         }, {
 424                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 425                 .addr           = 0xe6870030,
 426                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 427                 .mid_rid        = 0xcd,
 428         }, {
 429                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 430                 .addr           = 0xe6870030,
 431                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 432                 .mid_rid        = 0xce,
 433         }, {
 434                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 435                 .addr           = 0xe6bd0034,
 436                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 437                 .mid_rid        = 0xd1,
 438         }, {
 439                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 440                 .addr           = 0xe6bd0034,
 441                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 442                 .mid_rid        = 0xd2,
 443         },
 444 };
 445
 446 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 447         {
 448                 .offset = 0,
 449                 .dmars = 0,
 450                 .dmars_bit = 0,
 451         }, {
 452                 .offset = 0x10,
 453                 .dmars = 0,
 454                 .dmars_bit = 8,
 455         }, {
 456                 .offset = 0x20,
 457                 .dmars = 4,
 458                 .dmars_bit = 0,
 459         }, {
 460                 .offset = 0x30,
 461                 .dmars = 4,
 462                 .dmars_bit = 8,
 463         }, {
 464                 .offset = 0x50,
 465                 .dmars = 8,
 466                 .dmars_bit = 0,
 467         }, {
 468                 .offset = 0x60,
 469                 .dmars = 8,
 470                 .dmars_bit = 8,
 471         }
 472 };
 473
 474 static const unsigned int ts_shift[] = TS_SHIFT;
 475
 476 static struct sh_dmae_pdata dma_platform_data = {
 477         .slave          = sh7372_dmae_slaves,
 478         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 479         .channel        = sh7372_dmae_channels,
 480         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 481         .ts_low_shift   = 3,
 482         .ts_low_mask    = 0x18,
 483         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 484         .ts_high_mask   = 0x00300000,
 485         .ts_shift       = ts_shift,
 486         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 487         .dmaor_init     = DMAOR_DME,
 488 };
 489
 490 /* Resource order important! */
 491 static struct resource sh7372_dmae0_resources[] = {
 492         {
 493                 /* Channel registers and DMAOR */
 494                 .start  = 0xfe008020,
 495                 .end    = 0xfe00808f,
 496                 .flags  = IORESOURCE_MEM,
 497         },
 498         {
 499                 /* DMARSx */
 500                 .start  = 0xfe009000,
 501                 .end    = 0xfe00900b,
 502                 .flags  = IORESOURCE_MEM,
 503         },
 504         {
 505                 /* DMA error IRQ */
 506                 .start  = evt2irq(0x20c0),
 507                 .end    = evt2irq(0x20c0),
 508                 .flags  = IORESOURCE_IRQ,
 509         },
 510         {
 511                 /* IRQ for channels 0-5 */
 512                 .start  = evt2irq(0x2000),
 513                 .end    = evt2irq(0x20a0),
 514                 .flags  = IORESOURCE_IRQ,
 515         },
 516 };
 517
 518 /* Resource order important! */
 519 static struct resource sh7372_dmae1_resources[] = {
 520         {
 521                 /* Channel registers and DMAOR */
 522                 .start  = 0xfe018020,
 523                 .end    = 0xfe01808f,
 524                 .flags  = IORESOURCE_MEM,
 525         },
 526         {
 527                 /* DMARSx */
 528                 .start  = 0xfe019000,
 529                 .end    = 0xfe01900b,
 530                 .flags  = IORESOURCE_MEM,
 531         },
 532         {
 533                 /* DMA error IRQ */
 534                 .start  = evt2irq(0x21c0),
 535                 .end    = evt2irq(0x21c0),
 536                 .flags  = IORESOURCE_IRQ,
 537         },
 538         {
 539                 /* IRQ for channels 0-5 */
 540                 .start  = evt2irq(0x2100),
 541                 .end    = evt2irq(0x21a0),
 542                 .flags  = IORESOURCE_IRQ,
 543         },
 544 };
 545
 546 /* Resource order important! */
 547 static struct resource sh7372_dmae2_resources[] = {
 548         {
 549                 /* Channel registers and DMAOR */
 550                 .start  = 0xfe028020,
 551                 .end    = 0xfe02808f,
 552                 .flags  = IORESOURCE_MEM,
 553         },
 554         {
 555                 /* DMARSx */
 556                 .start  = 0xfe029000,
 557                 .end    = 0xfe02900b,
 558                 .flags  = IORESOURCE_MEM,
 559         },
 560         {
 561                 /* DMA error IRQ */
 562                 .start  = evt2irq(0x22c0),
 563                 .end    = evt2irq(0x22c0),
 564                 .flags  = IORESOURCE_IRQ,
 565         },
 566         {
 567                 /* IRQ for channels 0-5 */
 568                 .start  = evt2irq(0x2200),
 569                 .end    = evt2irq(0x22a0),
 570                 .flags  = IORESOURCE_IRQ,
 571         },
 572 };
 573
 574 static struct platform_device dma0_device = {
 575         .name           = "sh-dma-engine",
 576         .id             = 0,
 577         .resource       = sh7372_dmae0_resources,
 578         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 579         .dev            = {
 580                 .platform_data  = &dma_platform_data,
 581         },
 582 };
 583
 584 static struct platform_device dma1_device = {
 585         .name           = "sh-dma-engine",
 586         .id             = 1,
 587         .resource       = sh7372_dmae1_resources,
 588         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 589         .dev            = {
 590                 .platform_data  = &dma_platform_data,
 591         },
 592 };
 593
 594 static struct platform_device dma2_device = {
 595         .name           = "sh-dma-engine",
 596         .id             = 2,
 597         .resource       = sh7372_dmae2_resources,
 598         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 599         .dev            = {
 600                 .platform_data  = &dma_platform_data,
 601         },
 602 };
 603
 604 static struct platform_device *sh7372_early_devices[] __initdata = {
 605         &scif0_device,
 606         &scif1_device,
 607         &scif2_device,
 608         &scif3_device,
 609         &scif4_device,
 610         &scif5_device,
 611         &scif6_device,
 612         &cmt10_device,
 613         &tmu00_device,
 614         &tmu01_device,
 615 };
 616
 617 static struct platform_device *sh7372_late_devices[] __initdata = {
 618         &iic0_device,
 619         &iic1_device,
 620         &dma0_device,
 621         &dma1_device,
 622         &dma2_device,
 623 };
 624
 625 void __init sh7372_add_standard_devices(void)
 626 {
 627         platform_add_devices(sh7372_early_devices,
 628                             ARRAY_SIZE(sh7372_early_devices));
 629
 630         platform_add_devices(sh7372_late_devices,
 631                             ARRAY_SIZE(sh7372_late_devices));
 632 }
 633
 634 void __init sh7372_add_early_devices(void)
 635 {
 636         early_platform_add_devices(sh7372_early_devices,
 637                                    ARRAY_SIZE(sh7372_early_devices));
 638 }