2 * sh7372 Power management support
4 * Copyright (C) 2011 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/suspend.h>
13 #include <linux/cpuidle.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/err.h>
17 #include <linux/slab.h>
18 #include <linux/pm_clock.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/bitrev.h>
23 #include <linux/console.h>
25 #include <asm/tlbflush.h>
26 #include <asm/suspend.h>
27 #include <mach/common.h>
28 #include <mach/sh7372.h>
31 #define DBGREG1 0xe6100020
32 #define DBGREG9 0xe6100040
35 #define SYSTBCR 0xe6150024
36 #define MSTPSR0 0xe6150030
37 #define MSTPSR1 0xe6150038
38 #define MSTPSR2 0xe6150040
39 #define MSTPSR3 0xe6150048
40 #define MSTPSR4 0xe615004c
41 #define PLLC01STPCR 0xe61500c8
44 #define SPDCR 0xe6180008
45 #define SWUCR 0xe6180014
46 #define SBAR 0xe6180020
47 #define WUPRMSK 0xe6180028
48 #define WUPSMSK 0xe618002c
49 #define WUPSMSK2 0xe6180048
50 #define PSTR 0xe6180080
51 #define WUPSFAC 0xe6180098
52 #define IRQCR 0xe618022c
53 #define IRQCR2 0xe6180238
54 #define IRQCR3 0xe6180244
55 #define IRQCR4 0xe6180248
56 #define PDNSEL 0xe6180254
59 #define ICR1A 0xe6900000
60 #define ICR2A 0xe6900004
61 #define ICR3A 0xe6900008
62 #define ICR4A 0xe690000c
63 #define INTMSK00A 0xe6900040
64 #define INTMSK10A 0xe6900044
65 #define INTMSK20A 0xe6900048
66 #define INTMSK30A 0xe690004c
69 #define SMFRAM 0xe6a70000
72 #define APARMBAREA 0xe6f10020
74 #define PSTR_RETRIES 100
75 #define PSTR_DELAY_US 10
79 static int pd_power_down(struct generic_pm_domain
*genpd
)
81 struct sh7372_pm_domain
*sh7372_pd
= to_sh7372_pd(genpd
);
82 unsigned int mask
= 1 << sh7372_pd
->bit_shift
;
84 if (sh7372_pd
->suspend
) {
85 int ret
= sh7372_pd
->suspend();
91 if (__raw_readl(PSTR
) & mask
) {
92 unsigned int retry_count
;
94 __raw_writel(mask
, SPDCR
);
96 for (retry_count
= PSTR_RETRIES
; retry_count
; retry_count
--) {
97 if (!(__raw_readl(SPDCR
) & mask
))
103 if (!sh7372_pd
->no_debug
)
104 pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
105 genpd
->name
, mask
, __raw_readl(PSTR
));
110 static int __pd_power_up(struct sh7372_pm_domain
*sh7372_pd
, bool do_resume
)
112 unsigned int mask
= 1 << sh7372_pd
->bit_shift
;
113 unsigned int retry_count
;
116 if (__raw_readl(PSTR
) & mask
)
119 __raw_writel(mask
, SWUCR
);
121 for (retry_count
= 2 * PSTR_RETRIES
; retry_count
; retry_count
--) {
122 if (!(__raw_readl(SWUCR
) & mask
))
124 if (retry_count
> PSTR_RETRIES
)
125 udelay(PSTR_DELAY_US
);
132 if (!sh7372_pd
->no_debug
)
133 pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
134 sh7372_pd
->genpd
.name
, mask
, __raw_readl(PSTR
));
137 if (ret
== 0 && sh7372_pd
->resume
&& do_resume
)
143 static int pd_power_up(struct generic_pm_domain
*genpd
)
145 return __pd_power_up(to_sh7372_pd(genpd
), true);
148 static int sh7372_a4r_suspend(void)
150 sh7372_intcs_suspend();
151 __raw_writel(0x300fffff, WUPRMSK
); /* avoid wakeup */
155 static bool pd_active_wakeup(struct device
*dev
)
157 bool (*active_wakeup
)(struct device
*dev
);
159 active_wakeup
= dev_gpd_data(dev
)->ops
.active_wakeup
;
160 return active_wakeup
? active_wakeup(dev
) : true;
163 static int sh7372_stop_dev(struct device
*dev
)
165 int (*stop
)(struct device
*dev
);
167 stop
= dev_gpd_data(dev
)->ops
.stop
;
173 return pm_clk_suspend(dev
);
176 static int sh7372_start_dev(struct device
*dev
)
178 int (*start
)(struct device
*dev
);
181 ret
= pm_clk_resume(dev
);
185 start
= dev_gpd_data(dev
)->ops
.start
;
192 void sh7372_init_pm_domain(struct sh7372_pm_domain
*sh7372_pd
)
194 struct generic_pm_domain
*genpd
= &sh7372_pd
->genpd
;
195 struct dev_power_governor
*gov
= sh7372_pd
->gov
;
197 pm_genpd_init(genpd
, gov
? : &simple_qos_governor
, false);
198 genpd
->dev_ops
.stop
= sh7372_stop_dev
;
199 genpd
->dev_ops
.start
= sh7372_start_dev
;
200 genpd
->dev_ops
.active_wakeup
= pd_active_wakeup
;
201 genpd
->dev_irq_safe
= true;
202 genpd
->power_off
= pd_power_down
;
203 genpd
->power_on
= pd_power_up
;
204 __pd_power_up(sh7372_pd
, false);
207 void sh7372_add_device_to_domain(struct sh7372_pm_domain
*sh7372_pd
,
208 struct platform_device
*pdev
)
210 struct device
*dev
= &pdev
->dev
;
212 pm_genpd_add_device(&sh7372_pd
->genpd
, dev
);
213 if (pm_clk_no_clocks(dev
))
214 pm_clk_add(dev
, NULL
);
217 void sh7372_pm_add_subdomain(struct sh7372_pm_domain
*sh7372_pd
,
218 struct sh7372_pm_domain
*sh7372_sd
)
220 pm_genpd_add_subdomain(&sh7372_pd
->genpd
, &sh7372_sd
->genpd
);
223 struct sh7372_pm_domain sh7372_a4lc
= {
224 .genpd
.name
= "A4LC",
228 struct sh7372_pm_domain sh7372_a4mp
= {
229 .genpd
.name
= "A4MP",
233 struct sh7372_pm_domain sh7372_d4
= {
238 struct sh7372_pm_domain sh7372_a4r
= {
241 .suspend
= sh7372_a4r_suspend
,
242 .resume
= sh7372_intcs_resume
,
245 struct sh7372_pm_domain sh7372_a3rv
= {
246 .genpd
.name
= "A3RV",
250 struct sh7372_pm_domain sh7372_a3ri
= {
251 .genpd
.name
= "A3RI",
255 static int sh7372_a4s_suspend(void)
258 * The A4S domain contains the CPU core and therefore it should
259 * only be turned off if the CPU is in use.
264 struct sh7372_pm_domain sh7372_a4s
= {
267 .gov
= &pm_domain_always_on_gov
,
269 .suspend
= sh7372_a4s_suspend
,
272 static int sh7372_a3sp_suspend(void)
275 * Serial consoles make use of SCIF hardware located in A3SP,
276 * keep such power domain on if "no_console_suspend" is set.
278 return console_suspend_enabled
? 0 : -EBUSY
;
281 struct sh7372_pm_domain sh7372_a3sp
= {
282 .genpd
.name
= "A3SP",
284 .gov
= &pm_domain_always_on_gov
,
286 .suspend
= sh7372_a3sp_suspend
,
289 struct sh7372_pm_domain sh7372_a3sg
= {
290 .genpd
.name
= "A3SG",
294 #else /* !CONFIG_PM */
296 static inline void sh7372_a3sp_init(void) {}
298 #endif /* !CONFIG_PM */
300 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
301 static int sh7372_do_idle_core_standby(unsigned long unused
)
303 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
307 static void sh7372_set_reset_vector(unsigned long address
)
309 /* set reset vector, translate 4k */
310 __raw_writel(address
, SBAR
);
311 __raw_writel(0, APARMBAREA
);
314 static void sh7372_enter_core_standby(void)
316 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc
));
318 /* enter sleep mode with SYSTBCR to 0x10 */
319 __raw_writel(0x10, SYSTBCR
);
320 cpu_suspend(0, sh7372_do_idle_core_standby
);
321 __raw_writel(0, SYSTBCR
);
323 /* disable reset vector translation */
324 __raw_writel(0, SBAR
);
328 #ifdef CONFIG_SUSPEND
329 static void sh7372_enter_sysc(int pllc0_on
, unsigned long sleep_mode
)
332 __raw_writel(0, PLLC01STPCR
);
334 __raw_writel(1 << 28, PLLC01STPCR
);
336 __raw_readl(WUPSFAC
); /* read wakeup int. factor before sleep */
337 cpu_suspend(sleep_mode
, sh7372_do_idle_sysc
);
338 __raw_readl(WUPSFAC
); /* read wakeup int. factor after wakeup */
340 /* disable reset vector translation */
341 __raw_writel(0, SBAR
);
344 static int sh7372_sysc_valid(unsigned long *mskp
, unsigned long *msk2p
)
346 unsigned long mstpsr0
, mstpsr1
, mstpsr2
, mstpsr3
, mstpsr4
;
347 unsigned long msk
, msk2
;
349 /* check active clocks to determine potential wakeup sources */
351 mstpsr0
= __raw_readl(MSTPSR0
);
352 if ((mstpsr0
& 0x00000003) != 0x00000003) {
353 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0
);
357 mstpsr1
= __raw_readl(MSTPSR1
);
358 if ((mstpsr1
& 0xff079b7f) != 0xff079b7f) {
359 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1
);
363 mstpsr2
= __raw_readl(MSTPSR2
);
364 if ((mstpsr2
& 0x000741ff) != 0x000741ff) {
365 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2
);
369 mstpsr3
= __raw_readl(MSTPSR3
);
370 if ((mstpsr3
& 0x1a60f010) != 0x1a60f010) {
371 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3
);
375 mstpsr4
= __raw_readl(MSTPSR4
);
376 if ((mstpsr4
& 0x00008cf0) != 0x00008cf0) {
377 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4
);
384 /* make bitmaps of limited number of wakeup sources */
386 if ((mstpsr2
& (1 << 23)) == 0) /* SPU2 */
389 if ((mstpsr2
& (1 << 12)) == 0) /* MFI_MFIM */
392 if ((mstpsr4
& (1 << 3)) == 0) /* KEYSC */
395 if ((mstpsr1
& (1 << 24)) == 0) /* CMT0 */
398 if ((mstpsr3
& (1 << 29)) == 0) /* CMT1 */
401 if ((mstpsr4
& (1 << 0)) == 0) /* CMT2 */
404 if ((mstpsr2
& (1 << 13)) == 0) /* MFI_MFIS */
413 static void sh7372_icr_to_irqcr(unsigned long icr
, u16
*irqcr1p
, u16
*irqcr2p
)
415 u16 tmp
, irqcr1
, irqcr2
;
421 /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
422 for (k
= 0; k
<= 7; k
++) {
423 tmp
= (icr
>> ((7 - k
) * 4)) & 0xf;
424 irqcr1
|= (tmp
& 0x03) << (k
* 2);
425 irqcr2
|= (tmp
>> 2) << (k
* 2);
432 static void sh7372_setup_sysc(unsigned long msk
, unsigned long msk2
)
434 u16 irqcrx_low
, irqcrx_high
, irqcry_low
, irqcry_high
;
437 /* read IRQ0A -> IRQ15A mask */
438 tmp
= bitrev8(__raw_readb(INTMSK00A
));
439 tmp
|= bitrev8(__raw_readb(INTMSK10A
)) << 8;
441 /* setup WUPSMSK from clocks and external IRQ mask */
442 msk
= (~msk
& 0xc030000f) | (tmp
<< 4);
443 __raw_writel(msk
, WUPSMSK
);
445 /* propage level/edge trigger for external IRQ 0->15 */
446 sh7372_icr_to_irqcr(__raw_readl(ICR1A
), &irqcrx_low
, &irqcry_low
);
447 sh7372_icr_to_irqcr(__raw_readl(ICR2A
), &irqcrx_high
, &irqcry_high
);
448 __raw_writel((irqcrx_high
<< 16) | irqcrx_low
, IRQCR
);
449 __raw_writel((irqcry_high
<< 16) | irqcry_low
, IRQCR2
);
451 /* read IRQ16A -> IRQ31A mask */
452 tmp
= bitrev8(__raw_readb(INTMSK20A
));
453 tmp
|= bitrev8(__raw_readb(INTMSK30A
)) << 8;
455 /* setup WUPSMSK2 from clocks and external IRQ mask */
456 msk2
= (~msk2
& 0x00030000) | tmp
;
457 __raw_writel(msk2
, WUPSMSK2
);
459 /* propage level/edge trigger for external IRQ 16->31 */
460 sh7372_icr_to_irqcr(__raw_readl(ICR3A
), &irqcrx_low
, &irqcry_low
);
461 sh7372_icr_to_irqcr(__raw_readl(ICR4A
), &irqcrx_high
, &irqcry_high
);
462 __raw_writel((irqcrx_high
<< 16) | irqcrx_low
, IRQCR3
);
463 __raw_writel((irqcry_high
<< 16) | irqcry_low
, IRQCR4
);
466 static void sh7372_enter_a3sm_common(int pllc0_on
)
468 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc
));
469 sh7372_enter_sysc(pllc0_on
, 1 << 12);
472 static void sh7372_enter_a4s_common(int pllc0_on
)
474 sh7372_intca_suspend();
475 memcpy((void *)SMFRAM
, sh7372_resume_core_standby_sysc
, 0x100);
476 sh7372_set_reset_vector(SMFRAM
);
477 sh7372_enter_sysc(pllc0_on
, 1 << 10);
478 sh7372_intca_resume();
483 #ifdef CONFIG_CPU_IDLE
485 static void sh7372_cpuidle_setup(struct cpuidle_driver
*drv
)
487 struct cpuidle_state
*state
= &drv
->states
[drv
->state_count
];
489 snprintf(state
->name
, CPUIDLE_NAME_LEN
, "C2");
490 strncpy(state
->desc
, "Core Standby Mode", CPUIDLE_DESC_LEN
);
491 state
->exit_latency
= 10;
492 state
->target_residency
= 20 + 10;
493 state
->flags
= CPUIDLE_FLAG_TIME_VALID
;
494 shmobile_cpuidle_modes
[drv
->state_count
] = sh7372_enter_core_standby
;
499 static void sh7372_cpuidle_init(void)
501 shmobile_cpuidle_setup
= sh7372_cpuidle_setup
;
504 static void sh7372_cpuidle_init(void) {}
507 #ifdef CONFIG_SUSPEND
509 static int sh7372_enter_suspend(suspend_state_t suspend_state
)
511 unsigned long msk
, msk2
;
513 /* check active clocks to determine potential wakeup sources */
514 if (sh7372_sysc_valid(&msk
, &msk2
)) {
515 /* convert INTC mask and sense to SYSC mask and sense */
516 sh7372_setup_sysc(msk
, msk2
);
518 if (!console_suspend_enabled
&&
519 sh7372_a4s
.genpd
.status
== GPD_STATE_POWER_OFF
) {
520 /* enter A4S sleep with PLLC0 off */
521 pr_debug("entering A4S\n");
522 sh7372_enter_a4s_common(0);
524 /* enter A3SM sleep with PLLC0 off */
525 pr_debug("entering A3SM\n");
526 sh7372_enter_a3sm_common(0);
529 /* default to Core Standby that supports all wakeup sources */
530 pr_debug("entering Core Standby\n");
531 sh7372_enter_core_standby();
537 * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
539 * @pm_event: Event being handled.
542 static int sh7372_pm_notifier_fn(struct notifier_block
*notifier
,
543 unsigned long pm_event
, void *unused
)
546 case PM_SUSPEND_PREPARE
:
548 * This is necessary, because the A4R domain has to be "on"
549 * when suspend_device_irqs() and resume_device_irqs() are
550 * executed during system suspend and resume, respectively, so
551 * that those functions don't crash while accessing the INTCS.
553 pm_genpd_poweron(&sh7372_a4r
.genpd
);
555 case PM_POST_SUSPEND
:
556 pm_genpd_poweroff_unused();
563 static void sh7372_suspend_init(void)
565 shmobile_suspend_ops
.enter
= sh7372_enter_suspend
;
566 pm_notifier(sh7372_pm_notifier_fn
, 0);
569 static void sh7372_suspend_init(void) {}
572 void __init
sh7372_pm_init(void)
574 /* enable DBG hardware block to kick SYSC */
575 __raw_writel(0x0000a500, DBGREG9
);
576 __raw_writel(0x0000a501, DBGREG9
);
577 __raw_writel(0x00000000, DBGREG1
);
579 /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
580 __raw_writel(0, PDNSEL
);
582 sh7372_suspend_init();
583 sh7372_cpuidle_init();