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Merge branch 'i2c-embedded/for-next' of git://git.pengutronix.de/git/wsa/linux
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/i2c-omap.h>
18
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
22
23 #include "omap_hwmod_common_data.h"
24
25 #include "control.h"
26 #include "cm33xx.h"
27 #include "prm33xx.h"
28 #include "prm-regbits-33xx.h"
29 #include "i2c.h"
30 #include "mmc.h"
31
32 /*
33 * IP blocks
34 */
35
36 /*
37 * 'emif_fw' class
38 * instance(s): emif_fw
39 */
40 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
41 .name = "emif_fw",
42 };
43
44 /* emif_fw */
45 static struct omap_hwmod am33xx_emif_fw_hwmod = {
46 .name = "emif_fw",
47 .class = &am33xx_emif_fw_hwmod_class,
48 .clkdm_name = "l4fw_clkdm",
49 .main_clk = "l4fw_gclk",
50 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
51 .prcm = {
52 .omap4 = {
53 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
54 .modulemode = MODULEMODE_SWCTRL,
55 },
56 },
57 };
58
59 /*
60 * 'emif' class
61 * instance(s): emif
62 */
63 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
64 .rev_offs = 0x0000,
65 };
66
67 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
68 .name = "emif",
69 .sysc = &am33xx_emif_sysc,
70 };
71
72 static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
73 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
74 { .irq = -1 },
75 };
76
77 /* emif */
78 static struct omap_hwmod am33xx_emif_hwmod = {
79 .name = "emif",
80 .class = &am33xx_emif_hwmod_class,
81 .clkdm_name = "l3_clkdm",
82 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
83 .mpu_irqs = am33xx_emif_irqs,
84 .main_clk = "dpll_ddr_m2_div2_ck",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
88 .modulemode = MODULEMODE_SWCTRL,
89 },
90 },
91 };
92
93 /*
94 * 'l3' class
95 * instance(s): l3_main, l3_s, l3_instr
96 */
97 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
98 .name = "l3",
99 };
100
101 /* l3_main (l3_fast) */
102 static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
103 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
104 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
105 { .irq = -1 },
106 };
107
108 static struct omap_hwmod am33xx_l3_main_hwmod = {
109 .name = "l3_main",
110 .class = &am33xx_l3_hwmod_class,
111 .clkdm_name = "l3_clkdm",
112 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
113 .mpu_irqs = am33xx_l3_main_irqs,
114 .main_clk = "l3_gclk",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
118 .modulemode = MODULEMODE_SWCTRL,
119 },
120 },
121 };
122
123 /* l3_s */
124 static struct omap_hwmod am33xx_l3_s_hwmod = {
125 .name = "l3_s",
126 .class = &am33xx_l3_hwmod_class,
127 .clkdm_name = "l3s_clkdm",
128 };
129
130 /* l3_instr */
131 static struct omap_hwmod am33xx_l3_instr_hwmod = {
132 .name = "l3_instr",
133 .class = &am33xx_l3_hwmod_class,
134 .clkdm_name = "l3_clkdm",
135 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
136 .main_clk = "l3_gclk",
137 .prcm = {
138 .omap4 = {
139 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
140 .modulemode = MODULEMODE_SWCTRL,
141 },
142 },
143 };
144
145 /*
146 * 'l4' class
147 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
148 */
149 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
150 .name = "l4",
151 };
152
153 /* l4_ls */
154 static struct omap_hwmod am33xx_l4_ls_hwmod = {
155 .name = "l4_ls",
156 .class = &am33xx_l4_hwmod_class,
157 .clkdm_name = "l4ls_clkdm",
158 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
159 .main_clk = "l4ls_gclk",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
163 .modulemode = MODULEMODE_SWCTRL,
164 },
165 },
166 };
167
168 /* l4_hs */
169 static struct omap_hwmod am33xx_l4_hs_hwmod = {
170 .name = "l4_hs",
171 .class = &am33xx_l4_hwmod_class,
172 .clkdm_name = "l4hs_clkdm",
173 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
174 .main_clk = "l4hs_gclk",
175 .prcm = {
176 .omap4 = {
177 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
178 .modulemode = MODULEMODE_SWCTRL,
179 },
180 },
181 };
182
183
184 /* l4_wkup */
185 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
186 .name = "l4_wkup",
187 .class = &am33xx_l4_hwmod_class,
188 .clkdm_name = "l4_wkup_clkdm",
189 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
190 .prcm = {
191 .omap4 = {
192 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
193 .modulemode = MODULEMODE_SWCTRL,
194 },
195 },
196 };
197
198 /* l4_fw */
199 static struct omap_hwmod am33xx_l4_fw_hwmod = {
200 .name = "l4_fw",
201 .class = &am33xx_l4_hwmod_class,
202 .clkdm_name = "l4fw_clkdm",
203 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
204 .prcm = {
205 .omap4 = {
206 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
207 .modulemode = MODULEMODE_SWCTRL,
208 },
209 },
210 };
211
212 /*
213 * 'mpu' class
214 */
215 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
216 .name = "mpu",
217 };
218
219 /* mpu */
220 static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
221 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
222 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
223 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
224 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
225 { .irq = -1 },
226 };
227
228 static struct omap_hwmod am33xx_mpu_hwmod = {
229 .name = "mpu",
230 .class = &am33xx_mpu_hwmod_class,
231 .clkdm_name = "mpu_clkdm",
232 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
233 .mpu_irqs = am33xx_mpu_irqs,
234 .main_clk = "dpll_mpu_m2_ck",
235 .prcm = {
236 .omap4 = {
237 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
238 .modulemode = MODULEMODE_SWCTRL,
239 },
240 },
241 };
242
243 /*
244 * 'wakeup m3' class
245 * Wakeup controller sub-system under wakeup domain
246 */
247 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
248 .name = "wkup_m3",
249 };
250
251 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
252 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
253 };
254
255 static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
256 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
257 { .irq = -1 },
258 };
259
260 /* wkup_m3 */
261 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
262 .name = "wkup_m3",
263 .class = &am33xx_wkup_m3_hwmod_class,
264 .clkdm_name = "l4_wkup_aon_clkdm",
265 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
266 .mpu_irqs = am33xx_wkup_m3_irqs,
267 .main_clk = "dpll_core_m4_div2_ck",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
271 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
272 .modulemode = MODULEMODE_SWCTRL,
273 },
274 },
275 .rst_lines = am33xx_wkup_m3_resets,
276 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
277 };
278
279 /*
280 * 'pru-icss' class
281 * Programmable Real-Time Unit and Industrial Communication Subsystem
282 */
283 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
284 .name = "pruss",
285 };
286
287 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
288 { .name = "pruss", .rst_shift = 1 },
289 };
290
291 static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
292 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
293 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
294 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
295 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
296 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
297 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
298 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
299 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
300 { .irq = -1 },
301 };
302
303 /* pru-icss */
304 /* Pseudo hwmod for reset control purpose only */
305 static struct omap_hwmod am33xx_pruss_hwmod = {
306 .name = "pruss",
307 .class = &am33xx_pruss_hwmod_class,
308 .clkdm_name = "pruss_ocp_clkdm",
309 .mpu_irqs = am33xx_pruss_irqs,
310 .main_clk = "pruss_ocp_gclk",
311 .prcm = {
312 .omap4 = {
313 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
314 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
315 .modulemode = MODULEMODE_SWCTRL,
316 },
317 },
318 .rst_lines = am33xx_pruss_resets,
319 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
320 };
321
322 /* gfx */
323 /* Pseudo hwmod for reset control purpose only */
324 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
325 .name = "gfx",
326 };
327
328 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
329 { .name = "gfx", .rst_shift = 0 },
330 };
331
332 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
333 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
334 { .irq = -1 },
335 };
336
337 static struct omap_hwmod am33xx_gfx_hwmod = {
338 .name = "gfx",
339 .class = &am33xx_gfx_hwmod_class,
340 .clkdm_name = "gfx_l3_clkdm",
341 .mpu_irqs = am33xx_gfx_irqs,
342 .main_clk = "gfx_fck_div_ck",
343 .prcm = {
344 .omap4 = {
345 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
346 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
347 .modulemode = MODULEMODE_SWCTRL,
348 },
349 },
350 .rst_lines = am33xx_gfx_resets,
351 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
352 };
353
354 /*
355 * 'prcm' class
356 * power and reset manager (whole prcm infrastructure)
357 */
358 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
359 .name = "prcm",
360 };
361
362 /* prcm */
363 static struct omap_hwmod am33xx_prcm_hwmod = {
364 .name = "prcm",
365 .class = &am33xx_prcm_hwmod_class,
366 .clkdm_name = "l4_wkup_clkdm",
367 };
368
369 /*
370 * 'adc/tsc' class
371 * TouchScreen Controller (Anolog-To-Digital Converter)
372 */
373 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
374 .rev_offs = 0x00,
375 .sysc_offs = 0x10,
376 .sysc_flags = SYSC_HAS_SIDLEMODE,
377 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
378 SIDLE_SMART_WKUP),
379 .sysc_fields = &omap_hwmod_sysc_type2,
380 };
381
382 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
383 .name = "adc_tsc",
384 .sysc = &am33xx_adc_tsc_sysc,
385 };
386
387 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
388 { .irq = 16 + OMAP_INTC_START, },
389 { .irq = -1 },
390 };
391
392 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
393 .name = "adc_tsc",
394 .class = &am33xx_adc_tsc_hwmod_class,
395 .clkdm_name = "l4_wkup_clkdm",
396 .mpu_irqs = am33xx_adc_tsc_irqs,
397 .main_clk = "adc_tsc_fck",
398 .prcm = {
399 .omap4 = {
400 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
401 .modulemode = MODULEMODE_SWCTRL,
402 },
403 },
404 };
405
406 /*
407 * Modules omap_hwmod structures
408 *
409 * The following IPs are excluded for the moment because:
410 * - They do not need an explicit SW control using omap_hwmod API.
411 * - They still need to be validated with the driver
412 * properly adapted to omap_hwmod / omap_device
413 *
414 * - cEFUSE (doesn't fall under any ocp_if)
415 * - clkdiv32k
416 * - debugss
417 * - ocmc ram
418 * - ocp watch point
419 * - aes0
420 * - sha0
421 */
422 #if 0
423 /*
424 * 'cefuse' class
425 */
426 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
427 .name = "cefuse",
428 };
429
430 static struct omap_hwmod am33xx_cefuse_hwmod = {
431 .name = "cefuse",
432 .class = &am33xx_cefuse_hwmod_class,
433 .clkdm_name = "l4_cefuse_clkdm",
434 .main_clk = "cefuse_fck",
435 .prcm = {
436 .omap4 = {
437 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
438 .modulemode = MODULEMODE_SWCTRL,
439 },
440 },
441 };
442
443 /*
444 * 'clkdiv32k' class
445 */
446 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
447 .name = "clkdiv32k",
448 };
449
450 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
451 .name = "clkdiv32k",
452 .class = &am33xx_clkdiv32k_hwmod_class,
453 .clkdm_name = "clk_24mhz_clkdm",
454 .main_clk = "clkdiv32k_ick",
455 .prcm = {
456 .omap4 = {
457 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
458 .modulemode = MODULEMODE_SWCTRL,
459 },
460 },
461 };
462
463 /*
464 * 'debugss' class
465 * debug sub system
466 */
467 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
468 .name = "debugss",
469 };
470
471 static struct omap_hwmod am33xx_debugss_hwmod = {
472 .name = "debugss",
473 .class = &am33xx_debugss_hwmod_class,
474 .clkdm_name = "l3_aon_clkdm",
475 .main_clk = "debugss_ick",
476 .prcm = {
477 .omap4 = {
478 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
479 .modulemode = MODULEMODE_SWCTRL,
480 },
481 },
482 };
483
484 /* ocmcram */
485 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
486 .name = "ocmcram",
487 };
488
489 static struct omap_hwmod am33xx_ocmcram_hwmod = {
490 .name = "ocmcram",
491 .class = &am33xx_ocmcram_hwmod_class,
492 .clkdm_name = "l3_clkdm",
493 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
494 .main_clk = "l3_gclk",
495 .prcm = {
496 .omap4 = {
497 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
498 .modulemode = MODULEMODE_SWCTRL,
499 },
500 },
501 };
502
503 /* ocpwp */
504 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
505 .name = "ocpwp",
506 };
507
508 static struct omap_hwmod am33xx_ocpwp_hwmod = {
509 .name = "ocpwp",
510 .class = &am33xx_ocpwp_hwmod_class,
511 .clkdm_name = "l4ls_clkdm",
512 .main_clk = "l4ls_gclk",
513 .prcm = {
514 .omap4 = {
515 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
516 .modulemode = MODULEMODE_SWCTRL,
517 },
518 },
519 };
520
521 /*
522 * 'aes' class
523 */
524 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
525 .name = "aes",
526 };
527
528 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
529 { .irq = 102 + OMAP_INTC_START, },
530 { .irq = -1 },
531 };
532
533 static struct omap_hwmod am33xx_aes0_hwmod = {
534 .name = "aes0",
535 .class = &am33xx_aes_hwmod_class,
536 .clkdm_name = "l3_clkdm",
537 .mpu_irqs = am33xx_aes0_irqs,
538 .main_clk = "l3_gclk",
539 .prcm = {
540 .omap4 = {
541 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
542 .modulemode = MODULEMODE_SWCTRL,
543 },
544 },
545 };
546
547 /* sha0 */
548 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
549 .name = "sha0",
550 };
551
552 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
553 { .irq = 108 + OMAP_INTC_START, },
554 { .irq = -1 },
555 };
556
557 static struct omap_hwmod am33xx_sha0_hwmod = {
558 .name = "sha0",
559 .class = &am33xx_sha0_hwmod_class,
560 .clkdm_name = "l3_clkdm",
561 .mpu_irqs = am33xx_sha0_irqs,
562 .main_clk = "l3_gclk",
563 .prcm = {
564 .omap4 = {
565 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
566 .modulemode = MODULEMODE_SWCTRL,
567 },
568 },
569 };
570
571 #endif
572
573 /* 'smartreflex' class */
574 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
575 .name = "smartreflex",
576 };
577
578 /* smartreflex0 */
579 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
580 { .irq = 120 + OMAP_INTC_START, },
581 { .irq = -1 },
582 };
583
584 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
585 .name = "smartreflex0",
586 .class = &am33xx_smartreflex_hwmod_class,
587 .clkdm_name = "l4_wkup_clkdm",
588 .mpu_irqs = am33xx_smartreflex0_irqs,
589 .main_clk = "smartreflex0_fck",
590 .prcm = {
591 .omap4 = {
592 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
593 .modulemode = MODULEMODE_SWCTRL,
594 },
595 },
596 };
597
598 /* smartreflex1 */
599 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
600 { .irq = 121 + OMAP_INTC_START, },
601 { .irq = -1 },
602 };
603
604 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
605 .name = "smartreflex1",
606 .class = &am33xx_smartreflex_hwmod_class,
607 .clkdm_name = "l4_wkup_clkdm",
608 .mpu_irqs = am33xx_smartreflex1_irqs,
609 .main_clk = "smartreflex1_fck",
610 .prcm = {
611 .omap4 = {
612 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
613 .modulemode = MODULEMODE_SWCTRL,
614 },
615 },
616 };
617
618 /*
619 * 'control' module class
620 */
621 static struct omap_hwmod_class am33xx_control_hwmod_class = {
622 .name = "control",
623 };
624
625 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
626 { .irq = 8 + OMAP_INTC_START, },
627 { .irq = -1 },
628 };
629
630 static struct omap_hwmod am33xx_control_hwmod = {
631 .name = "control",
632 .class = &am33xx_control_hwmod_class,
633 .clkdm_name = "l4_wkup_clkdm",
634 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
635 .mpu_irqs = am33xx_control_irqs,
636 .main_clk = "dpll_core_m4_div2_ck",
637 .prcm = {
638 .omap4 = {
639 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
640 .modulemode = MODULEMODE_SWCTRL,
641 },
642 },
643 };
644
645 /*
646 * 'cpgmac' class
647 * cpsw/cpgmac sub system
648 */
649 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
650 .rev_offs = 0x0,
651 .sysc_offs = 0x8,
652 .syss_offs = 0x4,
653 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
654 SYSS_HAS_RESET_STATUS),
655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
656 MSTANDBY_NO),
657 .sysc_fields = &omap_hwmod_sysc_type3,
658 };
659
660 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
661 .name = "cpgmac0",
662 .sysc = &am33xx_cpgmac_sysc,
663 };
664
665 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
666 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
667 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
668 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
669 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
670 { .irq = -1 },
671 };
672
673 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
674 .name = "cpgmac0",
675 .class = &am33xx_cpgmac0_hwmod_class,
676 .clkdm_name = "cpsw_125mhz_clkdm",
677 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
678 .mpu_irqs = am33xx_cpgmac0_irqs,
679 .main_clk = "cpsw_125mhz_gclk",
680 .prcm = {
681 .omap4 = {
682 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
683 .modulemode = MODULEMODE_SWCTRL,
684 },
685 },
686 };
687
688 /*
689 * mdio class
690 */
691 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
692 .name = "davinci_mdio",
693 };
694
695 static struct omap_hwmod am33xx_mdio_hwmod = {
696 .name = "davinci_mdio",
697 .class = &am33xx_mdio_hwmod_class,
698 .clkdm_name = "cpsw_125mhz_clkdm",
699 .main_clk = "cpsw_125mhz_gclk",
700 };
701
702 /*
703 * dcan class
704 */
705 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
706 .name = "d_can",
707 };
708
709 /* dcan0 */
710 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
711 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
712 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
713 { .irq = -1 },
714 };
715
716 static struct omap_hwmod am33xx_dcan0_hwmod = {
717 .name = "d_can0",
718 .class = &am33xx_dcan_hwmod_class,
719 .clkdm_name = "l4ls_clkdm",
720 .mpu_irqs = am33xx_dcan0_irqs,
721 .main_clk = "dcan0_fck",
722 .prcm = {
723 .omap4 = {
724 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
725 .modulemode = MODULEMODE_SWCTRL,
726 },
727 },
728 };
729
730 /* dcan1 */
731 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
732 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
733 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
734 { .irq = -1 },
735 };
736 static struct omap_hwmod am33xx_dcan1_hwmod = {
737 .name = "d_can1",
738 .class = &am33xx_dcan_hwmod_class,
739 .clkdm_name = "l4ls_clkdm",
740 .mpu_irqs = am33xx_dcan1_irqs,
741 .main_clk = "dcan1_fck",
742 .prcm = {
743 .omap4 = {
744 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
745 .modulemode = MODULEMODE_SWCTRL,
746 },
747 },
748 };
749
750 /* elm */
751 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
752 .rev_offs = 0x0000,
753 .sysc_offs = 0x0010,
754 .syss_offs = 0x0014,
755 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
756 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
757 SYSS_HAS_RESET_STATUS),
758 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
759 .sysc_fields = &omap_hwmod_sysc_type1,
760 };
761
762 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
763 .name = "elm",
764 .sysc = &am33xx_elm_sysc,
765 };
766
767 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
768 { .irq = 4 + OMAP_INTC_START, },
769 { .irq = -1 },
770 };
771
772 static struct omap_hwmod am33xx_elm_hwmod = {
773 .name = "elm",
774 .class = &am33xx_elm_hwmod_class,
775 .clkdm_name = "l4ls_clkdm",
776 .mpu_irqs = am33xx_elm_irqs,
777 .main_clk = "l4ls_gclk",
778 .prcm = {
779 .omap4 = {
780 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
781 .modulemode = MODULEMODE_SWCTRL,
782 },
783 },
784 };
785
786 /*
787 * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
788 */
789 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
790 .rev_offs = 0x0,
791 .sysc_offs = 0x4,
792 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
793 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
794 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
795 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
796 .sysc_fields = &omap_hwmod_sysc_type2,
797 };
798
799 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
800 .name = "epwmss",
801 .sysc = &am33xx_epwmss_sysc,
802 };
803
804 /* ehrpwm0 */
805 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
806 { .name = "int", .irq = 86 + OMAP_INTC_START, },
807 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
808 { .irq = -1 },
809 };
810
811 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
812 .name = "ehrpwm0",
813 .class = &am33xx_epwmss_hwmod_class,
814 .clkdm_name = "l4ls_clkdm",
815 .mpu_irqs = am33xx_ehrpwm0_irqs,
816 .main_clk = "l4ls_gclk",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
820 .modulemode = MODULEMODE_SWCTRL,
821 },
822 },
823 };
824
825 /* ehrpwm1 */
826 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
827 { .name = "int", .irq = 87 + OMAP_INTC_START, },
828 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
829 { .irq = -1 },
830 };
831
832 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
833 .name = "ehrpwm1",
834 .class = &am33xx_epwmss_hwmod_class,
835 .clkdm_name = "l4ls_clkdm",
836 .mpu_irqs = am33xx_ehrpwm1_irqs,
837 .main_clk = "l4ls_gclk",
838 .prcm = {
839 .omap4 = {
840 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
841 .modulemode = MODULEMODE_SWCTRL,
842 },
843 },
844 };
845
846 /* ehrpwm2 */
847 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
848 { .name = "int", .irq = 39 + OMAP_INTC_START, },
849 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
850 { .irq = -1 },
851 };
852
853 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
854 .name = "ehrpwm2",
855 .class = &am33xx_epwmss_hwmod_class,
856 .clkdm_name = "l4ls_clkdm",
857 .mpu_irqs = am33xx_ehrpwm2_irqs,
858 .main_clk = "l4ls_gclk",
859 .prcm = {
860 .omap4 = {
861 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
862 .modulemode = MODULEMODE_SWCTRL,
863 },
864 },
865 };
866
867 /* ecap0 */
868 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
869 { .irq = 31 + OMAP_INTC_START, },
870 { .irq = -1 },
871 };
872
873 static struct omap_hwmod am33xx_ecap0_hwmod = {
874 .name = "ecap0",
875 .class = &am33xx_epwmss_hwmod_class,
876 .clkdm_name = "l4ls_clkdm",
877 .mpu_irqs = am33xx_ecap0_irqs,
878 .main_clk = "l4ls_gclk",
879 .prcm = {
880 .omap4 = {
881 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
882 .modulemode = MODULEMODE_SWCTRL,
883 },
884 },
885 };
886
887 /* ecap1 */
888 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
889 { .irq = 47 + OMAP_INTC_START, },
890 { .irq = -1 },
891 };
892
893 static struct omap_hwmod am33xx_ecap1_hwmod = {
894 .name = "ecap1",
895 .class = &am33xx_epwmss_hwmod_class,
896 .clkdm_name = "l4ls_clkdm",
897 .mpu_irqs = am33xx_ecap1_irqs,
898 .main_clk = "l4ls_gclk",
899 .prcm = {
900 .omap4 = {
901 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
902 .modulemode = MODULEMODE_SWCTRL,
903 },
904 },
905 };
906
907 /* ecap2 */
908 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
909 { .irq = 61 + OMAP_INTC_START, },
910 { .irq = -1 },
911 };
912
913 static struct omap_hwmod am33xx_ecap2_hwmod = {
914 .name = "ecap2",
915 .mpu_irqs = am33xx_ecap2_irqs,
916 .class = &am33xx_epwmss_hwmod_class,
917 .clkdm_name = "l4ls_clkdm",
918 .main_clk = "l4ls_gclk",
919 .prcm = {
920 .omap4 = {
921 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
922 .modulemode = MODULEMODE_SWCTRL,
923 },
924 },
925 };
926
927 /*
928 * 'gpio' class: for gpio 0,1,2,3
929 */
930 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
931 .rev_offs = 0x0000,
932 .sysc_offs = 0x0010,
933 .syss_offs = 0x0114,
934 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
935 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
936 SYSS_HAS_RESET_STATUS),
937 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
938 SIDLE_SMART_WKUP),
939 .sysc_fields = &omap_hwmod_sysc_type1,
940 };
941
942 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
943 .name = "gpio",
944 .sysc = &am33xx_gpio_sysc,
945 .rev = 2,
946 };
947
948 static struct omap_gpio_dev_attr gpio_dev_attr = {
949 .bank_width = 32,
950 .dbck_flag = true,
951 };
952
953 /* gpio0 */
954 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
955 { .role = "dbclk", .clk = "gpio0_dbclk" },
956 };
957
958 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
959 { .irq = 96 + OMAP_INTC_START, },
960 { .irq = -1 },
961 };
962
963 static struct omap_hwmod am33xx_gpio0_hwmod = {
964 .name = "gpio1",
965 .class = &am33xx_gpio_hwmod_class,
966 .clkdm_name = "l4_wkup_clkdm",
967 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
968 .mpu_irqs = am33xx_gpio0_irqs,
969 .main_clk = "dpll_core_m4_div2_ck",
970 .prcm = {
971 .omap4 = {
972 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
973 .modulemode = MODULEMODE_SWCTRL,
974 },
975 },
976 .opt_clks = gpio0_opt_clks,
977 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
978 .dev_attr = &gpio_dev_attr,
979 };
980
981 /* gpio1 */
982 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
983 { .irq = 98 + OMAP_INTC_START, },
984 { .irq = -1 },
985 };
986
987 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
988 { .role = "dbclk", .clk = "gpio1_dbclk" },
989 };
990
991 static struct omap_hwmod am33xx_gpio1_hwmod = {
992 .name = "gpio2",
993 .class = &am33xx_gpio_hwmod_class,
994 .clkdm_name = "l4ls_clkdm",
995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
996 .mpu_irqs = am33xx_gpio1_irqs,
997 .main_clk = "l4ls_gclk",
998 .prcm = {
999 .omap4 = {
1000 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1001 .modulemode = MODULEMODE_SWCTRL,
1002 },
1003 },
1004 .opt_clks = gpio1_opt_clks,
1005 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1006 .dev_attr = &gpio_dev_attr,
1007 };
1008
1009 /* gpio2 */
1010 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1011 { .irq = 32 + OMAP_INTC_START, },
1012 { .irq = -1 },
1013 };
1014
1015 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1016 { .role = "dbclk", .clk = "gpio2_dbclk" },
1017 };
1018
1019 static struct omap_hwmod am33xx_gpio2_hwmod = {
1020 .name = "gpio3",
1021 .class = &am33xx_gpio_hwmod_class,
1022 .clkdm_name = "l4ls_clkdm",
1023 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1024 .mpu_irqs = am33xx_gpio2_irqs,
1025 .main_clk = "l4ls_gclk",
1026 .prcm = {
1027 .omap4 = {
1028 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1029 .modulemode = MODULEMODE_SWCTRL,
1030 },
1031 },
1032 .opt_clks = gpio2_opt_clks,
1033 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1034 .dev_attr = &gpio_dev_attr,
1035 };
1036
1037 /* gpio3 */
1038 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1039 { .irq = 62 + OMAP_INTC_START, },
1040 { .irq = -1 },
1041 };
1042
1043 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1044 { .role = "dbclk", .clk = "gpio3_dbclk" },
1045 };
1046
1047 static struct omap_hwmod am33xx_gpio3_hwmod = {
1048 .name = "gpio4",
1049 .class = &am33xx_gpio_hwmod_class,
1050 .clkdm_name = "l4ls_clkdm",
1051 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1052 .mpu_irqs = am33xx_gpio3_irqs,
1053 .main_clk = "l4ls_gclk",
1054 .prcm = {
1055 .omap4 = {
1056 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1057 .modulemode = MODULEMODE_SWCTRL,
1058 },
1059 },
1060 .opt_clks = gpio3_opt_clks,
1061 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1062 .dev_attr = &gpio_dev_attr,
1063 };
1064
1065 /* gpmc */
1066 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1067 .rev_offs = 0x0,
1068 .sysc_offs = 0x10,
1069 .syss_offs = 0x14,
1070 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1071 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1072 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1073 .sysc_fields = &omap_hwmod_sysc_type1,
1074 };
1075
1076 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1077 .name = "gpmc",
1078 .sysc = &gpmc_sysc,
1079 };
1080
1081 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1082 { .irq = 100 + OMAP_INTC_START, },
1083 { .irq = -1 },
1084 };
1085
1086 static struct omap_hwmod am33xx_gpmc_hwmod = {
1087 .name = "gpmc",
1088 .class = &am33xx_gpmc_hwmod_class,
1089 .clkdm_name = "l3s_clkdm",
1090 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1091 .mpu_irqs = am33xx_gpmc_irqs,
1092 .main_clk = "l3s_gclk",
1093 .prcm = {
1094 .omap4 = {
1095 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1096 .modulemode = MODULEMODE_SWCTRL,
1097 },
1098 },
1099 };
1100
1101 /* 'i2c' class */
1102 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1103 .sysc_offs = 0x0010,
1104 .syss_offs = 0x0090,
1105 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1106 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1107 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1108 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1109 SIDLE_SMART_WKUP),
1110 .sysc_fields = &omap_hwmod_sysc_type1,
1111 };
1112
1113 static struct omap_hwmod_class i2c_class = {
1114 .name = "i2c",
1115 .sysc = &am33xx_i2c_sysc,
1116 .rev = OMAP_I2C_IP_VERSION_2,
1117 .reset = &omap_i2c_reset,
1118 };
1119
1120 static struct omap_i2c_dev_attr i2c_dev_attr = {
1121 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1122 };
1123
1124 /* i2c1 */
1125 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1126 { .irq = 70 + OMAP_INTC_START, },
1127 { .irq = -1 },
1128 };
1129
1130 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1131 { .name = "tx", .dma_req = 0, },
1132 { .name = "rx", .dma_req = 0, },
1133 { .dma_req = -1 }
1134 };
1135
1136 static struct omap_hwmod am33xx_i2c1_hwmod = {
1137 .name = "i2c1",
1138 .class = &i2c_class,
1139 .clkdm_name = "l4_wkup_clkdm",
1140 .mpu_irqs = i2c1_mpu_irqs,
1141 .sdma_reqs = i2c1_edma_reqs,
1142 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1143 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1144 .prcm = {
1145 .omap4 = {
1146 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1147 .modulemode = MODULEMODE_SWCTRL,
1148 },
1149 },
1150 .dev_attr = &i2c_dev_attr,
1151 };
1152
1153 /* i2c1 */
1154 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1155 { .irq = 71 + OMAP_INTC_START, },
1156 { .irq = -1 },
1157 };
1158
1159 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1160 { .name = "tx", .dma_req = 0, },
1161 { .name = "rx", .dma_req = 0, },
1162 { .dma_req = -1 }
1163 };
1164
1165 static struct omap_hwmod am33xx_i2c2_hwmod = {
1166 .name = "i2c2",
1167 .class = &i2c_class,
1168 .clkdm_name = "l4ls_clkdm",
1169 .mpu_irqs = i2c2_mpu_irqs,
1170 .sdma_reqs = i2c2_edma_reqs,
1171 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1172 .main_clk = "dpll_per_m2_div4_ck",
1173 .prcm = {
1174 .omap4 = {
1175 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1176 .modulemode = MODULEMODE_SWCTRL,
1177 },
1178 },
1179 .dev_attr = &i2c_dev_attr,
1180 };
1181
1182 /* i2c3 */
1183 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1184 { .name = "tx", .dma_req = 0, },
1185 { .name = "rx", .dma_req = 0, },
1186 { .dma_req = -1 }
1187 };
1188
1189 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1190 { .irq = 30 + OMAP_INTC_START, },
1191 { .irq = -1 },
1192 };
1193
1194 static struct omap_hwmod am33xx_i2c3_hwmod = {
1195 .name = "i2c3",
1196 .class = &i2c_class,
1197 .clkdm_name = "l4ls_clkdm",
1198 .mpu_irqs = i2c3_mpu_irqs,
1199 .sdma_reqs = i2c3_edma_reqs,
1200 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1201 .main_clk = "dpll_per_m2_div4_ck",
1202 .prcm = {
1203 .omap4 = {
1204 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1205 .modulemode = MODULEMODE_SWCTRL,
1206 },
1207 },
1208 .dev_attr = &i2c_dev_attr,
1209 };
1210
1211
1212 /* lcdc */
1213 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1214 .rev_offs = 0x0,
1215 .sysc_offs = 0x54,
1216 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1217 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1218 .sysc_fields = &omap_hwmod_sysc_type2,
1219 };
1220
1221 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1222 .name = "lcdc",
1223 .sysc = &lcdc_sysc,
1224 };
1225
1226 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1227 { .irq = 36 + OMAP_INTC_START, },
1228 { .irq = -1 },
1229 };
1230
1231 static struct omap_hwmod am33xx_lcdc_hwmod = {
1232 .name = "lcdc",
1233 .class = &am33xx_lcdc_hwmod_class,
1234 .clkdm_name = "lcdc_clkdm",
1235 .mpu_irqs = am33xx_lcdc_irqs,
1236 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1237 .main_clk = "lcd_gclk",
1238 .prcm = {
1239 .omap4 = {
1240 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1241 .modulemode = MODULEMODE_SWCTRL,
1242 },
1243 },
1244 };
1245
1246 /*
1247 * 'mailbox' class
1248 * mailbox module allowing communication between the on-chip processors using a
1249 * queued mailbox-interrupt mechanism.
1250 */
1251 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1252 .rev_offs = 0x0000,
1253 .sysc_offs = 0x0010,
1254 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1255 SYSC_HAS_SOFTRESET),
1256 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1257 .sysc_fields = &omap_hwmod_sysc_type2,
1258 };
1259
1260 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1261 .name = "mailbox",
1262 .sysc = &am33xx_mailbox_sysc,
1263 };
1264
1265 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1266 { .irq = 77 + OMAP_INTC_START, },
1267 { .irq = -1 },
1268 };
1269
1270 static struct omap_hwmod am33xx_mailbox_hwmod = {
1271 .name = "mailbox",
1272 .class = &am33xx_mailbox_hwmod_class,
1273 .clkdm_name = "l4ls_clkdm",
1274 .mpu_irqs = am33xx_mailbox_irqs,
1275 .main_clk = "l4ls_gclk",
1276 .prcm = {
1277 .omap4 = {
1278 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1279 .modulemode = MODULEMODE_SWCTRL,
1280 },
1281 },
1282 };
1283
1284 /*
1285 * 'mcasp' class
1286 */
1287 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1288 .rev_offs = 0x0,
1289 .sysc_offs = 0x4,
1290 .sysc_flags = SYSC_HAS_SIDLEMODE,
1291 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1292 .sysc_fields = &omap_hwmod_sysc_type3,
1293 };
1294
1295 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1296 .name = "mcasp",
1297 .sysc = &am33xx_mcasp_sysc,
1298 };
1299
1300 /* mcasp0 */
1301 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1302 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1303 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1304 { .irq = -1 },
1305 };
1306
1307 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1308 { .name = "tx", .dma_req = 8, },
1309 { .name = "rx", .dma_req = 9, },
1310 { .dma_req = -1 }
1311 };
1312
1313 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1314 .name = "mcasp0",
1315 .class = &am33xx_mcasp_hwmod_class,
1316 .clkdm_name = "l3s_clkdm",
1317 .mpu_irqs = am33xx_mcasp0_irqs,
1318 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1319 .main_clk = "mcasp0_fck",
1320 .prcm = {
1321 .omap4 = {
1322 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1323 .modulemode = MODULEMODE_SWCTRL,
1324 },
1325 },
1326 };
1327
1328 /* mcasp1 */
1329 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1330 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1331 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1332 { .irq = -1 },
1333 };
1334
1335 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1336 { .name = "tx", .dma_req = 10, },
1337 { .name = "rx", .dma_req = 11, },
1338 { .dma_req = -1 }
1339 };
1340
1341 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1342 .name = "mcasp1",
1343 .class = &am33xx_mcasp_hwmod_class,
1344 .clkdm_name = "l3s_clkdm",
1345 .mpu_irqs = am33xx_mcasp1_irqs,
1346 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1347 .main_clk = "mcasp1_fck",
1348 .prcm = {
1349 .omap4 = {
1350 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1351 .modulemode = MODULEMODE_SWCTRL,
1352 },
1353 },
1354 };
1355
1356 /* 'mmc' class */
1357 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1358 .rev_offs = 0x1fc,
1359 .sysc_offs = 0x10,
1360 .syss_offs = 0x14,
1361 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1362 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1363 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1364 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1365 .sysc_fields = &omap_hwmod_sysc_type1,
1366 };
1367
1368 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1369 .name = "mmc",
1370 .sysc = &am33xx_mmc_sysc,
1371 };
1372
1373 /* mmc0 */
1374 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1375 { .irq = 64 + OMAP_INTC_START, },
1376 { .irq = -1 },
1377 };
1378
1379 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1380 { .name = "tx", .dma_req = 24, },
1381 { .name = "rx", .dma_req = 25, },
1382 { .dma_req = -1 }
1383 };
1384
1385 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1386 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1387 };
1388
1389 static struct omap_hwmod am33xx_mmc0_hwmod = {
1390 .name = "mmc1",
1391 .class = &am33xx_mmc_hwmod_class,
1392 .clkdm_name = "l4ls_clkdm",
1393 .mpu_irqs = am33xx_mmc0_irqs,
1394 .sdma_reqs = am33xx_mmc0_edma_reqs,
1395 .main_clk = "mmc_clk",
1396 .prcm = {
1397 .omap4 = {
1398 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1399 .modulemode = MODULEMODE_SWCTRL,
1400 },
1401 },
1402 .dev_attr = &am33xx_mmc0_dev_attr,
1403 };
1404
1405 /* mmc1 */
1406 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1407 { .irq = 28 + OMAP_INTC_START, },
1408 { .irq = -1 },
1409 };
1410
1411 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1412 { .name = "tx", .dma_req = 2, },
1413 { .name = "rx", .dma_req = 3, },
1414 { .dma_req = -1 }
1415 };
1416
1417 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1418 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1419 };
1420
1421 static struct omap_hwmod am33xx_mmc1_hwmod = {
1422 .name = "mmc2",
1423 .class = &am33xx_mmc_hwmod_class,
1424 .clkdm_name = "l4ls_clkdm",
1425 .mpu_irqs = am33xx_mmc1_irqs,
1426 .sdma_reqs = am33xx_mmc1_edma_reqs,
1427 .main_clk = "mmc_clk",
1428 .prcm = {
1429 .omap4 = {
1430 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1431 .modulemode = MODULEMODE_SWCTRL,
1432 },
1433 },
1434 .dev_attr = &am33xx_mmc1_dev_attr,
1435 };
1436
1437 /* mmc2 */
1438 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1439 { .irq = 29 + OMAP_INTC_START, },
1440 { .irq = -1 },
1441 };
1442
1443 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1444 { .name = "tx", .dma_req = 64, },
1445 { .name = "rx", .dma_req = 65, },
1446 { .dma_req = -1 }
1447 };
1448
1449 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1450 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1451 };
1452 static struct omap_hwmod am33xx_mmc2_hwmod = {
1453 .name = "mmc3",
1454 .class = &am33xx_mmc_hwmod_class,
1455 .clkdm_name = "l3s_clkdm",
1456 .mpu_irqs = am33xx_mmc2_irqs,
1457 .sdma_reqs = am33xx_mmc2_edma_reqs,
1458 .main_clk = "mmc_clk",
1459 .prcm = {
1460 .omap4 = {
1461 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1462 .modulemode = MODULEMODE_SWCTRL,
1463 },
1464 },
1465 .dev_attr = &am33xx_mmc2_dev_attr,
1466 };
1467
1468 /*
1469 * 'rtc' class
1470 * rtc subsystem
1471 */
1472 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1473 .rev_offs = 0x0074,
1474 .sysc_offs = 0x0078,
1475 .sysc_flags = SYSC_HAS_SIDLEMODE,
1476 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1477 SIDLE_SMART | SIDLE_SMART_WKUP),
1478 .sysc_fields = &omap_hwmod_sysc_type3,
1479 };
1480
1481 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1482 .name = "rtc",
1483 .sysc = &am33xx_rtc_sysc,
1484 };
1485
1486 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1487 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1488 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1489 { .irq = -1 },
1490 };
1491
1492 static struct omap_hwmod am33xx_rtc_hwmod = {
1493 .name = "rtc",
1494 .class = &am33xx_rtc_hwmod_class,
1495 .clkdm_name = "l4_rtc_clkdm",
1496 .mpu_irqs = am33xx_rtc_irqs,
1497 .main_clk = "clk_32768_ck",
1498 .prcm = {
1499 .omap4 = {
1500 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1501 .modulemode = MODULEMODE_SWCTRL,
1502 },
1503 },
1504 };
1505
1506 /* 'spi' class */
1507 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1508 .rev_offs = 0x0000,
1509 .sysc_offs = 0x0110,
1510 .syss_offs = 0x0114,
1511 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1512 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1513 SYSS_HAS_RESET_STATUS),
1514 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1515 .sysc_fields = &omap_hwmod_sysc_type1,
1516 };
1517
1518 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1519 .name = "mcspi",
1520 .sysc = &am33xx_mcspi_sysc,
1521 .rev = OMAP4_MCSPI_REV,
1522 };
1523
1524 /* spi0 */
1525 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1526 { .irq = 65 + OMAP_INTC_START, },
1527 { .irq = -1 },
1528 };
1529
1530 static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1531 { .name = "rx0", .dma_req = 17 },
1532 { .name = "tx0", .dma_req = 16 },
1533 { .name = "rx1", .dma_req = 19 },
1534 { .name = "tx1", .dma_req = 18 },
1535 { .dma_req = -1 }
1536 };
1537
1538 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1539 .num_chipselect = 2,
1540 };
1541 static struct omap_hwmod am33xx_spi0_hwmod = {
1542 .name = "spi0",
1543 .class = &am33xx_spi_hwmod_class,
1544 .clkdm_name = "l4ls_clkdm",
1545 .mpu_irqs = am33xx_spi0_irqs,
1546 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1547 .main_clk = "dpll_per_m2_div4_ck",
1548 .prcm = {
1549 .omap4 = {
1550 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1551 .modulemode = MODULEMODE_SWCTRL,
1552 },
1553 },
1554 .dev_attr = &mcspi_attrib,
1555 };
1556
1557 /* spi1 */
1558 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1559 { .irq = 125 + OMAP_INTC_START, },
1560 { .irq = -1 },
1561 };
1562
1563 static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1564 { .name = "rx0", .dma_req = 43 },
1565 { .name = "tx0", .dma_req = 42 },
1566 { .name = "rx1", .dma_req = 45 },
1567 { .name = "tx1", .dma_req = 44 },
1568 { .dma_req = -1 }
1569 };
1570
1571 static struct omap_hwmod am33xx_spi1_hwmod = {
1572 .name = "spi1",
1573 .class = &am33xx_spi_hwmod_class,
1574 .clkdm_name = "l4ls_clkdm",
1575 .mpu_irqs = am33xx_spi1_irqs,
1576 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1577 .main_clk = "dpll_per_m2_div4_ck",
1578 .prcm = {
1579 .omap4 = {
1580 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1581 .modulemode = MODULEMODE_SWCTRL,
1582 },
1583 },
1584 .dev_attr = &mcspi_attrib,
1585 };
1586
1587 /*
1588 * 'spinlock' class
1589 * spinlock provides hardware assistance for synchronizing the
1590 * processes running on multiple processors
1591 */
1592 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1593 .name = "spinlock",
1594 };
1595
1596 static struct omap_hwmod am33xx_spinlock_hwmod = {
1597 .name = "spinlock",
1598 .class = &am33xx_spinlock_hwmod_class,
1599 .clkdm_name = "l4ls_clkdm",
1600 .main_clk = "l4ls_gclk",
1601 .prcm = {
1602 .omap4 = {
1603 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1604 .modulemode = MODULEMODE_SWCTRL,
1605 },
1606 },
1607 };
1608
1609 /* 'timer 2-7' class */
1610 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1611 .rev_offs = 0x0000,
1612 .sysc_offs = 0x0010,
1613 .syss_offs = 0x0014,
1614 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1615 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1616 SIDLE_SMART_WKUP),
1617 .sysc_fields = &omap_hwmod_sysc_type2,
1618 };
1619
1620 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1621 .name = "timer",
1622 .sysc = &am33xx_timer_sysc,
1623 };
1624
1625 /* timer1 1ms */
1626 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1627 .rev_offs = 0x0000,
1628 .sysc_offs = 0x0010,
1629 .syss_offs = 0x0014,
1630 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1631 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1632 SYSS_HAS_RESET_STATUS),
1633 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1634 .sysc_fields = &omap_hwmod_sysc_type1,
1635 };
1636
1637 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1638 .name = "timer",
1639 .sysc = &am33xx_timer1ms_sysc,
1640 };
1641
1642 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1643 { .irq = 67 + OMAP_INTC_START, },
1644 { .irq = -1 },
1645 };
1646
1647 static struct omap_hwmod am33xx_timer1_hwmod = {
1648 .name = "timer1",
1649 .class = &am33xx_timer1ms_hwmod_class,
1650 .clkdm_name = "l4_wkup_clkdm",
1651 .mpu_irqs = am33xx_timer1_irqs,
1652 .main_clk = "timer1_fck",
1653 .prcm = {
1654 .omap4 = {
1655 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1656 .modulemode = MODULEMODE_SWCTRL,
1657 },
1658 },
1659 };
1660
1661 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1662 { .irq = 68 + OMAP_INTC_START, },
1663 { .irq = -1 },
1664 };
1665
1666 static struct omap_hwmod am33xx_timer2_hwmod = {
1667 .name = "timer2",
1668 .class = &am33xx_timer_hwmod_class,
1669 .clkdm_name = "l4ls_clkdm",
1670 .mpu_irqs = am33xx_timer2_irqs,
1671 .main_clk = "timer2_fck",
1672 .prcm = {
1673 .omap4 = {
1674 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1675 .modulemode = MODULEMODE_SWCTRL,
1676 },
1677 },
1678 };
1679
1680 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1681 { .irq = 69 + OMAP_INTC_START, },
1682 { .irq = -1 },
1683 };
1684
1685 static struct omap_hwmod am33xx_timer3_hwmod = {
1686 .name = "timer3",
1687 .class = &am33xx_timer_hwmod_class,
1688 .clkdm_name = "l4ls_clkdm",
1689 .mpu_irqs = am33xx_timer3_irqs,
1690 .main_clk = "timer3_fck",
1691 .prcm = {
1692 .omap4 = {
1693 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1694 .modulemode = MODULEMODE_SWCTRL,
1695 },
1696 },
1697 };
1698
1699 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1700 { .irq = 92 + OMAP_INTC_START, },
1701 { .irq = -1 },
1702 };
1703
1704 static struct omap_hwmod am33xx_timer4_hwmod = {
1705 .name = "timer4",
1706 .class = &am33xx_timer_hwmod_class,
1707 .clkdm_name = "l4ls_clkdm",
1708 .mpu_irqs = am33xx_timer4_irqs,
1709 .main_clk = "timer4_fck",
1710 .prcm = {
1711 .omap4 = {
1712 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1713 .modulemode = MODULEMODE_SWCTRL,
1714 },
1715 },
1716 };
1717
1718 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1719 { .irq = 93 + OMAP_INTC_START, },
1720 { .irq = -1 },
1721 };
1722
1723 static struct omap_hwmod am33xx_timer5_hwmod = {
1724 .name = "timer5",
1725 .class = &am33xx_timer_hwmod_class,
1726 .clkdm_name = "l4ls_clkdm",
1727 .mpu_irqs = am33xx_timer5_irqs,
1728 .main_clk = "timer5_fck",
1729 .prcm = {
1730 .omap4 = {
1731 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1732 .modulemode = MODULEMODE_SWCTRL,
1733 },
1734 },
1735 };
1736
1737 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1738 { .irq = 94 + OMAP_INTC_START, },
1739 { .irq = -1 },
1740 };
1741
1742 static struct omap_hwmod am33xx_timer6_hwmod = {
1743 .name = "timer6",
1744 .class = &am33xx_timer_hwmod_class,
1745 .clkdm_name = "l4ls_clkdm",
1746 .mpu_irqs = am33xx_timer6_irqs,
1747 .main_clk = "timer6_fck",
1748 .prcm = {
1749 .omap4 = {
1750 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1751 .modulemode = MODULEMODE_SWCTRL,
1752 },
1753 },
1754 };
1755
1756 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1757 { .irq = 95 + OMAP_INTC_START, },
1758 { .irq = -1 },
1759 };
1760
1761 static struct omap_hwmod am33xx_timer7_hwmod = {
1762 .name = "timer7",
1763 .class = &am33xx_timer_hwmod_class,
1764 .clkdm_name = "l4ls_clkdm",
1765 .mpu_irqs = am33xx_timer7_irqs,
1766 .main_clk = "timer7_fck",
1767 .prcm = {
1768 .omap4 = {
1769 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1770 .modulemode = MODULEMODE_SWCTRL,
1771 },
1772 },
1773 };
1774
1775 /* tpcc */
1776 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1777 .name = "tpcc",
1778 };
1779
1780 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1781 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1782 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1783 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1784 { .irq = -1 },
1785 };
1786
1787 static struct omap_hwmod am33xx_tpcc_hwmod = {
1788 .name = "tpcc",
1789 .class = &am33xx_tpcc_hwmod_class,
1790 .clkdm_name = "l3_clkdm",
1791 .mpu_irqs = am33xx_tpcc_irqs,
1792 .main_clk = "l3_gclk",
1793 .prcm = {
1794 .omap4 = {
1795 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1796 .modulemode = MODULEMODE_SWCTRL,
1797 },
1798 },
1799 };
1800
1801 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1802 .rev_offs = 0x0,
1803 .sysc_offs = 0x10,
1804 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1805 SYSC_HAS_MIDLEMODE),
1806 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1807 .sysc_fields = &omap_hwmod_sysc_type2,
1808 };
1809
1810 /* 'tptc' class */
1811 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1812 .name = "tptc",
1813 .sysc = &am33xx_tptc_sysc,
1814 };
1815
1816 /* tptc0 */
1817 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1818 { .irq = 112 + OMAP_INTC_START, },
1819 { .irq = -1 },
1820 };
1821
1822 static struct omap_hwmod am33xx_tptc0_hwmod = {
1823 .name = "tptc0",
1824 .class = &am33xx_tptc_hwmod_class,
1825 .clkdm_name = "l3_clkdm",
1826 .mpu_irqs = am33xx_tptc0_irqs,
1827 .main_clk = "l3_gclk",
1828 .prcm = {
1829 .omap4 = {
1830 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1831 .modulemode = MODULEMODE_SWCTRL,
1832 },
1833 },
1834 };
1835
1836 /* tptc1 */
1837 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1838 { .irq = 113 + OMAP_INTC_START, },
1839 { .irq = -1 },
1840 };
1841
1842 static struct omap_hwmod am33xx_tptc1_hwmod = {
1843 .name = "tptc1",
1844 .class = &am33xx_tptc_hwmod_class,
1845 .clkdm_name = "l3_clkdm",
1846 .mpu_irqs = am33xx_tptc1_irqs,
1847 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1848 .main_clk = "l3_gclk",
1849 .prcm = {
1850 .omap4 = {
1851 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1852 .modulemode = MODULEMODE_SWCTRL,
1853 },
1854 },
1855 };
1856
1857 /* tptc2 */
1858 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1859 { .irq = 114 + OMAP_INTC_START, },
1860 { .irq = -1 },
1861 };
1862
1863 static struct omap_hwmod am33xx_tptc2_hwmod = {
1864 .name = "tptc2",
1865 .class = &am33xx_tptc_hwmod_class,
1866 .clkdm_name = "l3_clkdm",
1867 .mpu_irqs = am33xx_tptc2_irqs,
1868 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1869 .main_clk = "l3_gclk",
1870 .prcm = {
1871 .omap4 = {
1872 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1873 .modulemode = MODULEMODE_SWCTRL,
1874 },
1875 },
1876 };
1877
1878 /* 'uart' class */
1879 static struct omap_hwmod_class_sysconfig uart_sysc = {
1880 .rev_offs = 0x50,
1881 .sysc_offs = 0x54,
1882 .syss_offs = 0x58,
1883 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1884 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1885 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1886 SIDLE_SMART_WKUP),
1887 .sysc_fields = &omap_hwmod_sysc_type1,
1888 };
1889
1890 static struct omap_hwmod_class uart_class = {
1891 .name = "uart",
1892 .sysc = &uart_sysc,
1893 };
1894
1895 /* uart1 */
1896 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1897 { .name = "tx", .dma_req = 26, },
1898 { .name = "rx", .dma_req = 27, },
1899 { .dma_req = -1 }
1900 };
1901
1902 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1903 { .irq = 72 + OMAP_INTC_START, },
1904 { .irq = -1 },
1905 };
1906
1907 static struct omap_hwmod am33xx_uart1_hwmod = {
1908 .name = "uart1",
1909 .class = &uart_class,
1910 .clkdm_name = "l4_wkup_clkdm",
1911 .mpu_irqs = am33xx_uart1_irqs,
1912 .sdma_reqs = uart1_edma_reqs,
1913 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1914 .prcm = {
1915 .omap4 = {
1916 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1917 .modulemode = MODULEMODE_SWCTRL,
1918 },
1919 },
1920 };
1921
1922 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
1923 { .irq = 73 + OMAP_INTC_START, },
1924 { .irq = -1 },
1925 };
1926
1927 static struct omap_hwmod am33xx_uart2_hwmod = {
1928 .name = "uart2",
1929 .class = &uart_class,
1930 .clkdm_name = "l4ls_clkdm",
1931 .mpu_irqs = am33xx_uart2_irqs,
1932 .sdma_reqs = uart1_edma_reqs,
1933 .main_clk = "dpll_per_m2_div4_ck",
1934 .prcm = {
1935 .omap4 = {
1936 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1937 .modulemode = MODULEMODE_SWCTRL,
1938 },
1939 },
1940 };
1941
1942 /* uart3 */
1943 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
1944 { .name = "tx", .dma_req = 30, },
1945 { .name = "rx", .dma_req = 31, },
1946 { .dma_req = -1 }
1947 };
1948
1949 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
1950 { .irq = 74 + OMAP_INTC_START, },
1951 { .irq = -1 },
1952 };
1953
1954 static struct omap_hwmod am33xx_uart3_hwmod = {
1955 .name = "uart3",
1956 .class = &uart_class,
1957 .clkdm_name = "l4ls_clkdm",
1958 .mpu_irqs = am33xx_uart3_irqs,
1959 .sdma_reqs = uart3_edma_reqs,
1960 .main_clk = "dpll_per_m2_div4_ck",
1961 .prcm = {
1962 .omap4 = {
1963 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
1964 .modulemode = MODULEMODE_SWCTRL,
1965 },
1966 },
1967 };
1968
1969 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
1970 { .irq = 44 + OMAP_INTC_START, },
1971 { .irq = -1 },
1972 };
1973
1974 static struct omap_hwmod am33xx_uart4_hwmod = {
1975 .name = "uart4",
1976 .class = &uart_class,
1977 .clkdm_name = "l4ls_clkdm",
1978 .mpu_irqs = am33xx_uart4_irqs,
1979 .sdma_reqs = uart1_edma_reqs,
1980 .main_clk = "dpll_per_m2_div4_ck",
1981 .prcm = {
1982 .omap4 = {
1983 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
1984 .modulemode = MODULEMODE_SWCTRL,
1985 },
1986 },
1987 };
1988
1989 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
1990 { .irq = 45 + OMAP_INTC_START, },
1991 { .irq = -1 },
1992 };
1993
1994 static struct omap_hwmod am33xx_uart5_hwmod = {
1995 .name = "uart5",
1996 .class = &uart_class,
1997 .clkdm_name = "l4ls_clkdm",
1998 .mpu_irqs = am33xx_uart5_irqs,
1999 .sdma_reqs = uart1_edma_reqs,
2000 .main_clk = "dpll_per_m2_div4_ck",
2001 .prcm = {
2002 .omap4 = {
2003 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2004 .modulemode = MODULEMODE_SWCTRL,
2005 },
2006 },
2007 };
2008
2009 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2010 { .irq = 46 + OMAP_INTC_START, },
2011 { .irq = -1 },
2012 };
2013
2014 static struct omap_hwmod am33xx_uart6_hwmod = {
2015 .name = "uart6",
2016 .class = &uart_class,
2017 .clkdm_name = "l4ls_clkdm",
2018 .mpu_irqs = am33xx_uart6_irqs,
2019 .sdma_reqs = uart1_edma_reqs,
2020 .main_clk = "dpll_per_m2_div4_ck",
2021 .prcm = {
2022 .omap4 = {
2023 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2025 },
2026 },
2027 };
2028
2029 /* 'wd_timer' class */
2030 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2031 .name = "wd_timer",
2032 };
2033
2034 /*
2035 * XXX: device.c file uses hardcoded name for watchdog timer
2036 * driver "wd_timer2, so we are also using same name as of now...
2037 */
2038 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2039 .name = "wd_timer2",
2040 .class = &am33xx_wd_timer_hwmod_class,
2041 .clkdm_name = "l4_wkup_clkdm",
2042 .main_clk = "wdt1_fck",
2043 .prcm = {
2044 .omap4 = {
2045 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2046 .modulemode = MODULEMODE_SWCTRL,
2047 },
2048 },
2049 };
2050
2051 /*
2052 * 'usb_otg' class
2053 * high-speed on-the-go universal serial bus (usb_otg) controller
2054 */
2055 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2056 .rev_offs = 0x0,
2057 .sysc_offs = 0x10,
2058 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2059 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2060 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2061 .sysc_fields = &omap_hwmod_sysc_type2,
2062 };
2063
2064 static struct omap_hwmod_class am33xx_usbotg_class = {
2065 .name = "usbotg",
2066 .sysc = &am33xx_usbhsotg_sysc,
2067 };
2068
2069 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2070 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2071 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2072 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2073 { .irq = -1 + OMAP_INTC_START, },
2074 };
2075
2076 static struct omap_hwmod am33xx_usbss_hwmod = {
2077 .name = "usb_otg_hs",
2078 .class = &am33xx_usbotg_class,
2079 .clkdm_name = "l3s_clkdm",
2080 .mpu_irqs = am33xx_usbss_mpu_irqs,
2081 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2082 .main_clk = "usbotg_fck",
2083 .prcm = {
2084 .omap4 = {
2085 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2086 .modulemode = MODULEMODE_SWCTRL,
2087 },
2088 },
2089 };
2090
2091
2092 /*
2093 * Interfaces
2094 */
2095
2096 /* l4 fw -> emif fw */
2097 static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2098 .master = &am33xx_l4_fw_hwmod,
2099 .slave = &am33xx_emif_fw_hwmod,
2100 .clk = "l4fw_gclk",
2101 .user = OCP_USER_MPU,
2102 };
2103
2104 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2105 {
2106 .pa_start = 0x4c000000,
2107 .pa_end = 0x4c000fff,
2108 .flags = ADDR_TYPE_RT
2109 },
2110 { }
2111 };
2112 /* l3 main -> emif */
2113 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2114 .master = &am33xx_l3_main_hwmod,
2115 .slave = &am33xx_emif_hwmod,
2116 .clk = "dpll_core_m4_ck",
2117 .addr = am33xx_emif_addrs,
2118 .user = OCP_USER_MPU | OCP_USER_SDMA,
2119 };
2120
2121 /* mpu -> l3 main */
2122 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2123 .master = &am33xx_mpu_hwmod,
2124 .slave = &am33xx_l3_main_hwmod,
2125 .clk = "dpll_mpu_m2_ck",
2126 .user = OCP_USER_MPU,
2127 };
2128
2129 /* l3 main -> l4 hs */
2130 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2131 .master = &am33xx_l3_main_hwmod,
2132 .slave = &am33xx_l4_hs_hwmod,
2133 .clk = "l3s_gclk",
2134 .user = OCP_USER_MPU | OCP_USER_SDMA,
2135 };
2136
2137 /* l3 main -> l3 s */
2138 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2139 .master = &am33xx_l3_main_hwmod,
2140 .slave = &am33xx_l3_s_hwmod,
2141 .clk = "l3s_gclk",
2142 .user = OCP_USER_MPU | OCP_USER_SDMA,
2143 };
2144
2145 /* l3 s -> l4 per/ls */
2146 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2147 .master = &am33xx_l3_s_hwmod,
2148 .slave = &am33xx_l4_ls_hwmod,
2149 .clk = "l3s_gclk",
2150 .user = OCP_USER_MPU | OCP_USER_SDMA,
2151 };
2152
2153 /* l3 s -> l4 wkup */
2154 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2155 .master = &am33xx_l3_s_hwmod,
2156 .slave = &am33xx_l4_wkup_hwmod,
2157 .clk = "l3s_gclk",
2158 .user = OCP_USER_MPU | OCP_USER_SDMA,
2159 };
2160
2161 /* l3 s -> l4 fw */
2162 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2163 .master = &am33xx_l3_s_hwmod,
2164 .slave = &am33xx_l4_fw_hwmod,
2165 .clk = "l3s_gclk",
2166 .user = OCP_USER_MPU | OCP_USER_SDMA,
2167 };
2168
2169 /* l3 main -> l3 instr */
2170 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2171 .master = &am33xx_l3_main_hwmod,
2172 .slave = &am33xx_l3_instr_hwmod,
2173 .clk = "l3s_gclk",
2174 .user = OCP_USER_MPU | OCP_USER_SDMA,
2175 };
2176
2177 /* mpu -> prcm */
2178 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2179 .master = &am33xx_mpu_hwmod,
2180 .slave = &am33xx_prcm_hwmod,
2181 .clk = "dpll_mpu_m2_ck",
2182 .user = OCP_USER_MPU | OCP_USER_SDMA,
2183 };
2184
2185 /* l3 s -> l3 main*/
2186 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2187 .master = &am33xx_l3_s_hwmod,
2188 .slave = &am33xx_l3_main_hwmod,
2189 .clk = "l3s_gclk",
2190 .user = OCP_USER_MPU | OCP_USER_SDMA,
2191 };
2192
2193 /* pru-icss -> l3 main */
2194 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2195 .master = &am33xx_pruss_hwmod,
2196 .slave = &am33xx_l3_main_hwmod,
2197 .clk = "l3_gclk",
2198 .user = OCP_USER_MPU | OCP_USER_SDMA,
2199 };
2200
2201 /* wkup m3 -> l4 wkup */
2202 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2203 .master = &am33xx_wkup_m3_hwmod,
2204 .slave = &am33xx_l4_wkup_hwmod,
2205 .clk = "dpll_core_m4_div2_ck",
2206 .user = OCP_USER_MPU | OCP_USER_SDMA,
2207 };
2208
2209 /* gfx -> l3 main */
2210 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2211 .master = &am33xx_gfx_hwmod,
2212 .slave = &am33xx_l3_main_hwmod,
2213 .clk = "dpll_core_m4_ck",
2214 .user = OCP_USER_MPU | OCP_USER_SDMA,
2215 };
2216
2217 /* l4 wkup -> wkup m3 */
2218 static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2219 {
2220 .name = "umem",
2221 .pa_start = 0x44d00000,
2222 .pa_end = 0x44d00000 + SZ_16K - 1,
2223 .flags = ADDR_TYPE_RT
2224 },
2225 {
2226 .name = "dmem",
2227 .pa_start = 0x44d80000,
2228 .pa_end = 0x44d80000 + SZ_8K - 1,
2229 .flags = ADDR_TYPE_RT
2230 },
2231 { }
2232 };
2233
2234 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2235 .master = &am33xx_l4_wkup_hwmod,
2236 .slave = &am33xx_wkup_m3_hwmod,
2237 .clk = "dpll_core_m4_div2_ck",
2238 .addr = am33xx_wkup_m3_addrs,
2239 .user = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 /* l4 hs -> pru-icss */
2243 static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2244 {
2245 .pa_start = 0x4a300000,
2246 .pa_end = 0x4a300000 + SZ_512K - 1,
2247 .flags = ADDR_TYPE_RT
2248 },
2249 { }
2250 };
2251
2252 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2253 .master = &am33xx_l4_hs_hwmod,
2254 .slave = &am33xx_pruss_hwmod,
2255 .clk = "dpll_core_m4_ck",
2256 .addr = am33xx_pruss_addrs,
2257 .user = OCP_USER_MPU | OCP_USER_SDMA,
2258 };
2259
2260 /* l3 main -> gfx */
2261 static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2262 {
2263 .pa_start = 0x56000000,
2264 .pa_end = 0x56000000 + SZ_16M - 1,
2265 .flags = ADDR_TYPE_RT
2266 },
2267 { }
2268 };
2269
2270 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2271 .master = &am33xx_l3_main_hwmod,
2272 .slave = &am33xx_gfx_hwmod,
2273 .clk = "dpll_core_m4_ck",
2274 .addr = am33xx_gfx_addrs,
2275 .user = OCP_USER_MPU | OCP_USER_SDMA,
2276 };
2277
2278 /* l4 wkup -> smartreflex0 */
2279 static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2280 {
2281 .pa_start = 0x44e37000,
2282 .pa_end = 0x44e37000 + SZ_4K - 1,
2283 .flags = ADDR_TYPE_RT
2284 },
2285 { }
2286 };
2287
2288 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2289 .master = &am33xx_l4_wkup_hwmod,
2290 .slave = &am33xx_smartreflex0_hwmod,
2291 .clk = "dpll_core_m4_div2_ck",
2292 .addr = am33xx_smartreflex0_addrs,
2293 .user = OCP_USER_MPU,
2294 };
2295
2296 /* l4 wkup -> smartreflex1 */
2297 static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2298 {
2299 .pa_start = 0x44e39000,
2300 .pa_end = 0x44e39000 + SZ_4K - 1,
2301 .flags = ADDR_TYPE_RT
2302 },
2303 { }
2304 };
2305
2306 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2307 .master = &am33xx_l4_wkup_hwmod,
2308 .slave = &am33xx_smartreflex1_hwmod,
2309 .clk = "dpll_core_m4_div2_ck",
2310 .addr = am33xx_smartreflex1_addrs,
2311 .user = OCP_USER_MPU,
2312 };
2313
2314 /* l4 wkup -> control */
2315 static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2316 {
2317 .pa_start = 0x44e10000,
2318 .pa_end = 0x44e10000 + SZ_8K - 1,
2319 .flags = ADDR_TYPE_RT
2320 },
2321 { }
2322 };
2323
2324 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2325 .master = &am33xx_l4_wkup_hwmod,
2326 .slave = &am33xx_control_hwmod,
2327 .clk = "dpll_core_m4_div2_ck",
2328 .addr = am33xx_control_addrs,
2329 .user = OCP_USER_MPU,
2330 };
2331
2332 /* l4 wkup -> rtc */
2333 static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2334 {
2335 .pa_start = 0x44e3e000,
2336 .pa_end = 0x44e3e000 + SZ_4K - 1,
2337 .flags = ADDR_TYPE_RT
2338 },
2339 { }
2340 };
2341
2342 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2343 .master = &am33xx_l4_wkup_hwmod,
2344 .slave = &am33xx_rtc_hwmod,
2345 .clk = "clkdiv32k_ick",
2346 .addr = am33xx_rtc_addrs,
2347 .user = OCP_USER_MPU,
2348 };
2349
2350 /* l4 per/ls -> DCAN0 */
2351 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2352 {
2353 .pa_start = 0x481CC000,
2354 .pa_end = 0x481CC000 + SZ_4K - 1,
2355 .flags = ADDR_TYPE_RT
2356 },
2357 { }
2358 };
2359
2360 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2361 .master = &am33xx_l4_ls_hwmod,
2362 .slave = &am33xx_dcan0_hwmod,
2363 .clk = "l4ls_gclk",
2364 .addr = am33xx_dcan0_addrs,
2365 .user = OCP_USER_MPU | OCP_USER_SDMA,
2366 };
2367
2368 /* l4 per/ls -> DCAN1 */
2369 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2370 {
2371 .pa_start = 0x481D0000,
2372 .pa_end = 0x481D0000 + SZ_4K - 1,
2373 .flags = ADDR_TYPE_RT
2374 },
2375 { }
2376 };
2377
2378 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2379 .master = &am33xx_l4_ls_hwmod,
2380 .slave = &am33xx_dcan1_hwmod,
2381 .clk = "l4ls_gclk",
2382 .addr = am33xx_dcan1_addrs,
2383 .user = OCP_USER_MPU | OCP_USER_SDMA,
2384 };
2385
2386 /* l4 per/ls -> GPIO2 */
2387 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2388 {
2389 .pa_start = 0x4804C000,
2390 .pa_end = 0x4804C000 + SZ_4K - 1,
2391 .flags = ADDR_TYPE_RT,
2392 },
2393 { }
2394 };
2395
2396 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2397 .master = &am33xx_l4_ls_hwmod,
2398 .slave = &am33xx_gpio1_hwmod,
2399 .clk = "l4ls_gclk",
2400 .addr = am33xx_gpio1_addrs,
2401 .user = OCP_USER_MPU | OCP_USER_SDMA,
2402 };
2403
2404 /* l4 per/ls -> gpio3 */
2405 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2406 {
2407 .pa_start = 0x481AC000,
2408 .pa_end = 0x481AC000 + SZ_4K - 1,
2409 .flags = ADDR_TYPE_RT,
2410 },
2411 { }
2412 };
2413
2414 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2415 .master = &am33xx_l4_ls_hwmod,
2416 .slave = &am33xx_gpio2_hwmod,
2417 .clk = "l4ls_gclk",
2418 .addr = am33xx_gpio2_addrs,
2419 .user = OCP_USER_MPU | OCP_USER_SDMA,
2420 };
2421
2422 /* l4 per/ls -> gpio4 */
2423 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2424 {
2425 .pa_start = 0x481AE000,
2426 .pa_end = 0x481AE000 + SZ_4K - 1,
2427 .flags = ADDR_TYPE_RT,
2428 },
2429 { }
2430 };
2431
2432 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2433 .master = &am33xx_l4_ls_hwmod,
2434 .slave = &am33xx_gpio3_hwmod,
2435 .clk = "l4ls_gclk",
2436 .addr = am33xx_gpio3_addrs,
2437 .user = OCP_USER_MPU | OCP_USER_SDMA,
2438 };
2439
2440 /* L4 WKUP -> I2C1 */
2441 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2442 {
2443 .pa_start = 0x44E0B000,
2444 .pa_end = 0x44E0B000 + SZ_4K - 1,
2445 .flags = ADDR_TYPE_RT,
2446 },
2447 { }
2448 };
2449
2450 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2451 .master = &am33xx_l4_wkup_hwmod,
2452 .slave = &am33xx_i2c1_hwmod,
2453 .clk = "dpll_core_m4_div2_ck",
2454 .addr = am33xx_i2c1_addr_space,
2455 .user = OCP_USER_MPU,
2456 };
2457
2458 /* L4 WKUP -> GPIO1 */
2459 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2460 {
2461 .pa_start = 0x44E07000,
2462 .pa_end = 0x44E07000 + SZ_4K - 1,
2463 .flags = ADDR_TYPE_RT,
2464 },
2465 { }
2466 };
2467
2468 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2469 .master = &am33xx_l4_wkup_hwmod,
2470 .slave = &am33xx_gpio0_hwmod,
2471 .clk = "dpll_core_m4_div2_ck",
2472 .addr = am33xx_gpio0_addrs,
2473 .user = OCP_USER_MPU | OCP_USER_SDMA,
2474 };
2475
2476 /* L4 WKUP -> ADC_TSC */
2477 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2478 {
2479 .pa_start = 0x44E0D000,
2480 .pa_end = 0x44E0D000 + SZ_8K - 1,
2481 .flags = ADDR_TYPE_RT
2482 },
2483 { }
2484 };
2485
2486 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2487 .master = &am33xx_l4_wkup_hwmod,
2488 .slave = &am33xx_adc_tsc_hwmod,
2489 .clk = "dpll_core_m4_div2_ck",
2490 .addr = am33xx_adc_tsc_addrs,
2491 .user = OCP_USER_MPU,
2492 };
2493
2494 static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2495 /* cpsw ss */
2496 {
2497 .pa_start = 0x4a100000,
2498 .pa_end = 0x4a100000 + SZ_2K - 1,
2499 .flags = ADDR_TYPE_RT,
2500 },
2501 /* cpsw wr */
2502 {
2503 .pa_start = 0x4a101200,
2504 .pa_end = 0x4a101200 + SZ_256 - 1,
2505 .flags = ADDR_TYPE_RT,
2506 },
2507 { }
2508 };
2509
2510 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2511 .master = &am33xx_l4_hs_hwmod,
2512 .slave = &am33xx_cpgmac0_hwmod,
2513 .clk = "cpsw_125mhz_gclk",
2514 .addr = am33xx_cpgmac0_addr_space,
2515 .user = OCP_USER_MPU,
2516 };
2517
2518 struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2519 {
2520 .pa_start = 0x4A101000,
2521 .pa_end = 0x4A101000 + SZ_256 - 1,
2522 },
2523 { }
2524 };
2525
2526 struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2527 .master = &am33xx_cpgmac0_hwmod,
2528 .slave = &am33xx_mdio_hwmod,
2529 .addr = am33xx_mdio_addr_space,
2530 .user = OCP_USER_MPU,
2531 };
2532
2533 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2534 {
2535 .pa_start = 0x48080000,
2536 .pa_end = 0x48080000 + SZ_8K - 1,
2537 .flags = ADDR_TYPE_RT
2538 },
2539 { }
2540 };
2541
2542 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2543 .master = &am33xx_l4_ls_hwmod,
2544 .slave = &am33xx_elm_hwmod,
2545 .clk = "l4ls_gclk",
2546 .addr = am33xx_elm_addr_space,
2547 .user = OCP_USER_MPU,
2548 };
2549
2550 /*
2551 * Splitting the resources to handle access of PWMSS config space
2552 * and module specific part independently
2553 */
2554 static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2555 {
2556 .pa_start = 0x48300000,
2557 .pa_end = 0x48300000 + SZ_16 - 1,
2558 .flags = ADDR_TYPE_RT
2559 },
2560 {
2561 .pa_start = 0x48300200,
2562 .pa_end = 0x48300200 + SZ_256 - 1,
2563 .flags = ADDR_TYPE_RT
2564 },
2565 { }
2566 };
2567
2568 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
2569 .master = &am33xx_l4_ls_hwmod,
2570 .slave = &am33xx_ehrpwm0_hwmod,
2571 .clk = "l4ls_gclk",
2572 .addr = am33xx_ehrpwm0_addr_space,
2573 .user = OCP_USER_MPU,
2574 };
2575
2576 /*
2577 * Splitting the resources to handle access of PWMSS config space
2578 * and module specific part independently
2579 */
2580 static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2581 {
2582 .pa_start = 0x48302000,
2583 .pa_end = 0x48302000 + SZ_16 - 1,
2584 .flags = ADDR_TYPE_RT
2585 },
2586 {
2587 .pa_start = 0x48302200,
2588 .pa_end = 0x48302200 + SZ_256 - 1,
2589 .flags = ADDR_TYPE_RT
2590 },
2591 { }
2592 };
2593
2594 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
2595 .master = &am33xx_l4_ls_hwmod,
2596 .slave = &am33xx_ehrpwm1_hwmod,
2597 .clk = "l4ls_gclk",
2598 .addr = am33xx_ehrpwm1_addr_space,
2599 .user = OCP_USER_MPU,
2600 };
2601
2602 /*
2603 * Splitting the resources to handle access of PWMSS config space
2604 * and module specific part independently
2605 */
2606 static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2607 {
2608 .pa_start = 0x48304000,
2609 .pa_end = 0x48304000 + SZ_16 - 1,
2610 .flags = ADDR_TYPE_RT
2611 },
2612 {
2613 .pa_start = 0x48304200,
2614 .pa_end = 0x48304200 + SZ_256 - 1,
2615 .flags = ADDR_TYPE_RT
2616 },
2617 { }
2618 };
2619
2620 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
2621 .master = &am33xx_l4_ls_hwmod,
2622 .slave = &am33xx_ehrpwm2_hwmod,
2623 .clk = "l4ls_gclk",
2624 .addr = am33xx_ehrpwm2_addr_space,
2625 .user = OCP_USER_MPU,
2626 };
2627
2628 /*
2629 * Splitting the resources to handle access of PWMSS config space
2630 * and module specific part independently
2631 */
2632 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2633 {
2634 .pa_start = 0x48300000,
2635 .pa_end = 0x48300000 + SZ_16 - 1,
2636 .flags = ADDR_TYPE_RT
2637 },
2638 {
2639 .pa_start = 0x48300100,
2640 .pa_end = 0x48300100 + SZ_256 - 1,
2641 .flags = ADDR_TYPE_RT
2642 },
2643 { }
2644 };
2645
2646 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
2647 .master = &am33xx_l4_ls_hwmod,
2648 .slave = &am33xx_ecap0_hwmod,
2649 .clk = "l4ls_gclk",
2650 .addr = am33xx_ecap0_addr_space,
2651 .user = OCP_USER_MPU,
2652 };
2653
2654 /*
2655 * Splitting the resources to handle access of PWMSS config space
2656 * and module specific part independently
2657 */
2658 static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2659 {
2660 .pa_start = 0x48302000,
2661 .pa_end = 0x48302000 + SZ_16 - 1,
2662 .flags = ADDR_TYPE_RT
2663 },
2664 {
2665 .pa_start = 0x48302100,
2666 .pa_end = 0x48302100 + SZ_256 - 1,
2667 .flags = ADDR_TYPE_RT
2668 },
2669 { }
2670 };
2671
2672 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
2673 .master = &am33xx_l4_ls_hwmod,
2674 .slave = &am33xx_ecap1_hwmod,
2675 .clk = "l4ls_gclk",
2676 .addr = am33xx_ecap1_addr_space,
2677 .user = OCP_USER_MPU,
2678 };
2679
2680 /*
2681 * Splitting the resources to handle access of PWMSS config space
2682 * and module specific part independently
2683 */
2684 static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2685 {
2686 .pa_start = 0x48304000,
2687 .pa_end = 0x48304000 + SZ_16 - 1,
2688 .flags = ADDR_TYPE_RT
2689 },
2690 {
2691 .pa_start = 0x48304100,
2692 .pa_end = 0x48304100 + SZ_256 - 1,
2693 .flags = ADDR_TYPE_RT
2694 },
2695 { }
2696 };
2697
2698 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
2699 .master = &am33xx_l4_ls_hwmod,
2700 .slave = &am33xx_ecap2_hwmod,
2701 .clk = "l4ls_gclk",
2702 .addr = am33xx_ecap2_addr_space,
2703 .user = OCP_USER_MPU,
2704 };
2705
2706 /* l3s cfg -> gpmc */
2707 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2708 {
2709 .pa_start = 0x50000000,
2710 .pa_end = 0x50000000 + SZ_8K - 1,
2711 .flags = ADDR_TYPE_RT,
2712 },
2713 { }
2714 };
2715
2716 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2717 .master = &am33xx_l3_s_hwmod,
2718 .slave = &am33xx_gpmc_hwmod,
2719 .clk = "l3s_gclk",
2720 .addr = am33xx_gpmc_addr_space,
2721 .user = OCP_USER_MPU,
2722 };
2723
2724 /* i2c2 */
2725 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2726 {
2727 .pa_start = 0x4802A000,
2728 .pa_end = 0x4802A000 + SZ_4K - 1,
2729 .flags = ADDR_TYPE_RT,
2730 },
2731 { }
2732 };
2733
2734 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2735 .master = &am33xx_l4_ls_hwmod,
2736 .slave = &am33xx_i2c2_hwmod,
2737 .clk = "l4ls_gclk",
2738 .addr = am33xx_i2c2_addr_space,
2739 .user = OCP_USER_MPU,
2740 };
2741
2742 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2743 {
2744 .pa_start = 0x4819C000,
2745 .pa_end = 0x4819C000 + SZ_4K - 1,
2746 .flags = ADDR_TYPE_RT
2747 },
2748 { }
2749 };
2750
2751 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2752 .master = &am33xx_l4_ls_hwmod,
2753 .slave = &am33xx_i2c3_hwmod,
2754 .clk = "l4ls_gclk",
2755 .addr = am33xx_i2c3_addr_space,
2756 .user = OCP_USER_MPU,
2757 };
2758
2759 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2760 {
2761 .pa_start = 0x4830E000,
2762 .pa_end = 0x4830E000 + SZ_8K - 1,
2763 .flags = ADDR_TYPE_RT,
2764 },
2765 { }
2766 };
2767
2768 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2769 .master = &am33xx_l3_main_hwmod,
2770 .slave = &am33xx_lcdc_hwmod,
2771 .clk = "dpll_core_m4_ck",
2772 .addr = am33xx_lcdc_addr_space,
2773 .user = OCP_USER_MPU,
2774 };
2775
2776 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2777 {
2778 .pa_start = 0x480C8000,
2779 .pa_end = 0x480C8000 + (SZ_4K - 1),
2780 .flags = ADDR_TYPE_RT
2781 },
2782 { }
2783 };
2784
2785 /* l4 ls -> mailbox */
2786 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2787 .master = &am33xx_l4_ls_hwmod,
2788 .slave = &am33xx_mailbox_hwmod,
2789 .clk = "l4ls_gclk",
2790 .addr = am33xx_mailbox_addrs,
2791 .user = OCP_USER_MPU,
2792 };
2793
2794 /* l4 ls -> spinlock */
2795 static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2796 {
2797 .pa_start = 0x480Ca000,
2798 .pa_end = 0x480Ca000 + SZ_4K - 1,
2799 .flags = ADDR_TYPE_RT
2800 },
2801 { }
2802 };
2803
2804 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2805 .master = &am33xx_l4_ls_hwmod,
2806 .slave = &am33xx_spinlock_hwmod,
2807 .clk = "l4ls_gclk",
2808 .addr = am33xx_spinlock_addrs,
2809 .user = OCP_USER_MPU,
2810 };
2811
2812 /* l4 ls -> mcasp0 */
2813 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2814 {
2815 .pa_start = 0x48038000,
2816 .pa_end = 0x48038000 + SZ_8K - 1,
2817 .flags = ADDR_TYPE_RT
2818 },
2819 { }
2820 };
2821
2822 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2823 .master = &am33xx_l4_ls_hwmod,
2824 .slave = &am33xx_mcasp0_hwmod,
2825 .clk = "l4ls_gclk",
2826 .addr = am33xx_mcasp0_addr_space,
2827 .user = OCP_USER_MPU,
2828 };
2829
2830 /* l3 s -> mcasp0 data */
2831 static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2832 {
2833 .pa_start = 0x46000000,
2834 .pa_end = 0x46000000 + SZ_4M - 1,
2835 .flags = ADDR_TYPE_RT
2836 },
2837 { }
2838 };
2839
2840 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2841 .master = &am33xx_l3_s_hwmod,
2842 .slave = &am33xx_mcasp0_hwmod,
2843 .clk = "l3s_gclk",
2844 .addr = am33xx_mcasp0_data_addr_space,
2845 .user = OCP_USER_SDMA,
2846 };
2847
2848 /* l4 ls -> mcasp1 */
2849 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2850 {
2851 .pa_start = 0x4803C000,
2852 .pa_end = 0x4803C000 + SZ_8K - 1,
2853 .flags = ADDR_TYPE_RT
2854 },
2855 { }
2856 };
2857
2858 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2859 .master = &am33xx_l4_ls_hwmod,
2860 .slave = &am33xx_mcasp1_hwmod,
2861 .clk = "l4ls_gclk",
2862 .addr = am33xx_mcasp1_addr_space,
2863 .user = OCP_USER_MPU,
2864 };
2865
2866 /* l3 s -> mcasp1 data */
2867 static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
2868 {
2869 .pa_start = 0x46400000,
2870 .pa_end = 0x46400000 + SZ_4M - 1,
2871 .flags = ADDR_TYPE_RT
2872 },
2873 { }
2874 };
2875
2876 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
2877 .master = &am33xx_l3_s_hwmod,
2878 .slave = &am33xx_mcasp1_hwmod,
2879 .clk = "l3s_gclk",
2880 .addr = am33xx_mcasp1_data_addr_space,
2881 .user = OCP_USER_SDMA,
2882 };
2883
2884 /* l4 ls -> mmc0 */
2885 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2886 {
2887 .pa_start = 0x48060100,
2888 .pa_end = 0x48060100 + SZ_4K - 1,
2889 .flags = ADDR_TYPE_RT,
2890 },
2891 { }
2892 };
2893
2894 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
2895 .master = &am33xx_l4_ls_hwmod,
2896 .slave = &am33xx_mmc0_hwmod,
2897 .clk = "l4ls_gclk",
2898 .addr = am33xx_mmc0_addr_space,
2899 .user = OCP_USER_MPU,
2900 };
2901
2902 /* l4 ls -> mmc1 */
2903 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
2904 {
2905 .pa_start = 0x481d8100,
2906 .pa_end = 0x481d8100 + SZ_4K - 1,
2907 .flags = ADDR_TYPE_RT,
2908 },
2909 { }
2910 };
2911
2912 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
2913 .master = &am33xx_l4_ls_hwmod,
2914 .slave = &am33xx_mmc1_hwmod,
2915 .clk = "l4ls_gclk",
2916 .addr = am33xx_mmc1_addr_space,
2917 .user = OCP_USER_MPU,
2918 };
2919
2920 /* l3 s -> mmc2 */
2921 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
2922 {
2923 .pa_start = 0x47810100,
2924 .pa_end = 0x47810100 + SZ_64K - 1,
2925 .flags = ADDR_TYPE_RT,
2926 },
2927 { }
2928 };
2929
2930 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
2931 .master = &am33xx_l3_s_hwmod,
2932 .slave = &am33xx_mmc2_hwmod,
2933 .clk = "l3s_gclk",
2934 .addr = am33xx_mmc2_addr_space,
2935 .user = OCP_USER_MPU,
2936 };
2937
2938 /* l4 ls -> mcspi0 */
2939 static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
2940 {
2941 .pa_start = 0x48030000,
2942 .pa_end = 0x48030000 + SZ_1K - 1,
2943 .flags = ADDR_TYPE_RT,
2944 },
2945 { }
2946 };
2947
2948 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
2949 .master = &am33xx_l4_ls_hwmod,
2950 .slave = &am33xx_spi0_hwmod,
2951 .clk = "l4ls_gclk",
2952 .addr = am33xx_mcspi0_addr_space,
2953 .user = OCP_USER_MPU,
2954 };
2955
2956 /* l4 ls -> mcspi1 */
2957 static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
2958 {
2959 .pa_start = 0x481A0000,
2960 .pa_end = 0x481A0000 + SZ_1K - 1,
2961 .flags = ADDR_TYPE_RT,
2962 },
2963 { }
2964 };
2965
2966 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
2967 .master = &am33xx_l4_ls_hwmod,
2968 .slave = &am33xx_spi1_hwmod,
2969 .clk = "l4ls_gclk",
2970 .addr = am33xx_mcspi1_addr_space,
2971 .user = OCP_USER_MPU,
2972 };
2973
2974 /* l4 wkup -> timer1 */
2975 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2976 {
2977 .pa_start = 0x44E31000,
2978 .pa_end = 0x44E31000 + SZ_1K - 1,
2979 .flags = ADDR_TYPE_RT
2980 },
2981 { }
2982 };
2983
2984 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
2985 .master = &am33xx_l4_wkup_hwmod,
2986 .slave = &am33xx_timer1_hwmod,
2987 .clk = "dpll_core_m4_div2_ck",
2988 .addr = am33xx_timer1_addr_space,
2989 .user = OCP_USER_MPU,
2990 };
2991
2992 /* l4 per -> timer2 */
2993 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2994 {
2995 .pa_start = 0x48040000,
2996 .pa_end = 0x48040000 + SZ_1K - 1,
2997 .flags = ADDR_TYPE_RT
2998 },
2999 { }
3000 };
3001
3002 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3003 .master = &am33xx_l4_ls_hwmod,
3004 .slave = &am33xx_timer2_hwmod,
3005 .clk = "l4ls_gclk",
3006 .addr = am33xx_timer2_addr_space,
3007 .user = OCP_USER_MPU,
3008 };
3009
3010 /* l4 per -> timer3 */
3011 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3012 {
3013 .pa_start = 0x48042000,
3014 .pa_end = 0x48042000 + SZ_1K - 1,
3015 .flags = ADDR_TYPE_RT
3016 },
3017 { }
3018 };
3019
3020 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3021 .master = &am33xx_l4_ls_hwmod,
3022 .slave = &am33xx_timer3_hwmod,
3023 .clk = "l4ls_gclk",
3024 .addr = am33xx_timer3_addr_space,
3025 .user = OCP_USER_MPU,
3026 };
3027
3028 /* l4 per -> timer4 */
3029 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3030 {
3031 .pa_start = 0x48044000,
3032 .pa_end = 0x48044000 + SZ_1K - 1,
3033 .flags = ADDR_TYPE_RT
3034 },
3035 { }
3036 };
3037
3038 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3039 .master = &am33xx_l4_ls_hwmod,
3040 .slave = &am33xx_timer4_hwmod,
3041 .clk = "l4ls_gclk",
3042 .addr = am33xx_timer4_addr_space,
3043 .user = OCP_USER_MPU,
3044 };
3045
3046 /* l4 per -> timer5 */
3047 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3048 {
3049 .pa_start = 0x48046000,
3050 .pa_end = 0x48046000 + SZ_1K - 1,
3051 .flags = ADDR_TYPE_RT
3052 },
3053 { }
3054 };
3055
3056 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3057 .master = &am33xx_l4_ls_hwmod,
3058 .slave = &am33xx_timer5_hwmod,
3059 .clk = "l4ls_gclk",
3060 .addr = am33xx_timer5_addr_space,
3061 .user = OCP_USER_MPU,
3062 };
3063
3064 /* l4 per -> timer6 */
3065 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3066 {
3067 .pa_start = 0x48048000,
3068 .pa_end = 0x48048000 + SZ_1K - 1,
3069 .flags = ADDR_TYPE_RT
3070 },
3071 { }
3072 };
3073
3074 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3075 .master = &am33xx_l4_ls_hwmod,
3076 .slave = &am33xx_timer6_hwmod,
3077 .clk = "l4ls_gclk",
3078 .addr = am33xx_timer6_addr_space,
3079 .user = OCP_USER_MPU,
3080 };
3081
3082 /* l4 per -> timer7 */
3083 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3084 {
3085 .pa_start = 0x4804A000,
3086 .pa_end = 0x4804A000 + SZ_1K - 1,
3087 .flags = ADDR_TYPE_RT
3088 },
3089 { }
3090 };
3091
3092 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3093 .master = &am33xx_l4_ls_hwmod,
3094 .slave = &am33xx_timer7_hwmod,
3095 .clk = "l4ls_gclk",
3096 .addr = am33xx_timer7_addr_space,
3097 .user = OCP_USER_MPU,
3098 };
3099
3100 /* l3 main -> tpcc */
3101 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3102 {
3103 .pa_start = 0x49000000,
3104 .pa_end = 0x49000000 + SZ_32K - 1,
3105 .flags = ADDR_TYPE_RT
3106 },
3107 { }
3108 };
3109
3110 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3111 .master = &am33xx_l3_main_hwmod,
3112 .slave = &am33xx_tpcc_hwmod,
3113 .clk = "l3_gclk",
3114 .addr = am33xx_tpcc_addr_space,
3115 .user = OCP_USER_MPU,
3116 };
3117
3118 /* l3 main -> tpcc0 */
3119 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3120 {
3121 .pa_start = 0x49800000,
3122 .pa_end = 0x49800000 + SZ_8K - 1,
3123 .flags = ADDR_TYPE_RT,
3124 },
3125 { }
3126 };
3127
3128 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3129 .master = &am33xx_l3_main_hwmod,
3130 .slave = &am33xx_tptc0_hwmod,
3131 .clk = "l3_gclk",
3132 .addr = am33xx_tptc0_addr_space,
3133 .user = OCP_USER_MPU,
3134 };
3135
3136 /* l3 main -> tpcc1 */
3137 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3138 {
3139 .pa_start = 0x49900000,
3140 .pa_end = 0x49900000 + SZ_8K - 1,
3141 .flags = ADDR_TYPE_RT,
3142 },
3143 { }
3144 };
3145
3146 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3147 .master = &am33xx_l3_main_hwmod,
3148 .slave = &am33xx_tptc1_hwmod,
3149 .clk = "l3_gclk",
3150 .addr = am33xx_tptc1_addr_space,
3151 .user = OCP_USER_MPU,
3152 };
3153
3154 /* l3 main -> tpcc2 */
3155 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3156 {
3157 .pa_start = 0x49a00000,
3158 .pa_end = 0x49a00000 + SZ_8K - 1,
3159 .flags = ADDR_TYPE_RT,
3160 },
3161 { }
3162 };
3163
3164 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3165 .master = &am33xx_l3_main_hwmod,
3166 .slave = &am33xx_tptc2_hwmod,
3167 .clk = "l3_gclk",
3168 .addr = am33xx_tptc2_addr_space,
3169 .user = OCP_USER_MPU,
3170 };
3171
3172 /* l4 wkup -> uart1 */
3173 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3174 {
3175 .pa_start = 0x44E09000,
3176 .pa_end = 0x44E09000 + SZ_8K - 1,
3177 .flags = ADDR_TYPE_RT,
3178 },
3179 { }
3180 };
3181
3182 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3183 .master = &am33xx_l4_wkup_hwmod,
3184 .slave = &am33xx_uart1_hwmod,
3185 .clk = "dpll_core_m4_div2_ck",
3186 .addr = am33xx_uart1_addr_space,
3187 .user = OCP_USER_MPU,
3188 };
3189
3190 /* l4 ls -> uart2 */
3191 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3192 {
3193 .pa_start = 0x48022000,
3194 .pa_end = 0x48022000 + SZ_8K - 1,
3195 .flags = ADDR_TYPE_RT,
3196 },
3197 { }
3198 };
3199
3200 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3201 .master = &am33xx_l4_ls_hwmod,
3202 .slave = &am33xx_uart2_hwmod,
3203 .clk = "l4ls_gclk",
3204 .addr = am33xx_uart2_addr_space,
3205 .user = OCP_USER_MPU,
3206 };
3207
3208 /* l4 ls -> uart3 */
3209 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3210 {
3211 .pa_start = 0x48024000,
3212 .pa_end = 0x48024000 + SZ_8K - 1,
3213 .flags = ADDR_TYPE_RT,
3214 },
3215 { }
3216 };
3217
3218 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3219 .master = &am33xx_l4_ls_hwmod,
3220 .slave = &am33xx_uart3_hwmod,
3221 .clk = "l4ls_gclk",
3222 .addr = am33xx_uart3_addr_space,
3223 .user = OCP_USER_MPU,
3224 };
3225
3226 /* l4 ls -> uart4 */
3227 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3228 {
3229 .pa_start = 0x481A6000,
3230 .pa_end = 0x481A6000 + SZ_8K - 1,
3231 .flags = ADDR_TYPE_RT,
3232 },
3233 { }
3234 };
3235
3236 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3237 .master = &am33xx_l4_ls_hwmod,
3238 .slave = &am33xx_uart4_hwmod,
3239 .clk = "l4ls_gclk",
3240 .addr = am33xx_uart4_addr_space,
3241 .user = OCP_USER_MPU,
3242 };
3243
3244 /* l4 ls -> uart5 */
3245 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3246 {
3247 .pa_start = 0x481A8000,
3248 .pa_end = 0x481A8000 + SZ_8K - 1,
3249 .flags = ADDR_TYPE_RT,
3250 },
3251 { }
3252 };
3253
3254 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3255 .master = &am33xx_l4_ls_hwmod,
3256 .slave = &am33xx_uart5_hwmod,
3257 .clk = "l4ls_gclk",
3258 .addr = am33xx_uart5_addr_space,
3259 .user = OCP_USER_MPU,
3260 };
3261
3262 /* l4 ls -> uart6 */
3263 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3264 {
3265 .pa_start = 0x481aa000,
3266 .pa_end = 0x481aa000 + SZ_8K - 1,
3267 .flags = ADDR_TYPE_RT,
3268 },
3269 { }
3270 };
3271
3272 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3273 .master = &am33xx_l4_ls_hwmod,
3274 .slave = &am33xx_uart6_hwmod,
3275 .clk = "l4ls_gclk",
3276 .addr = am33xx_uart6_addr_space,
3277 .user = OCP_USER_MPU,
3278 };
3279
3280 /* l4 wkup -> wd_timer1 */
3281 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3282 {
3283 .pa_start = 0x44e35000,
3284 .pa_end = 0x44e35000 + SZ_4K - 1,
3285 .flags = ADDR_TYPE_RT
3286 },
3287 { }
3288 };
3289
3290 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3291 .master = &am33xx_l4_wkup_hwmod,
3292 .slave = &am33xx_wd_timer1_hwmod,
3293 .clk = "dpll_core_m4_div2_ck",
3294 .addr = am33xx_wd_timer1_addrs,
3295 .user = OCP_USER_MPU,
3296 };
3297
3298 /* usbss */
3299 /* l3 s -> USBSS interface */
3300 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3301 {
3302 .name = "usbss",
3303 .pa_start = 0x47400000,
3304 .pa_end = 0x47400000 + SZ_4K - 1,
3305 .flags = ADDR_TYPE_RT
3306 },
3307 {
3308 .name = "musb0",
3309 .pa_start = 0x47401000,
3310 .pa_end = 0x47401000 + SZ_2K - 1,
3311 .flags = ADDR_TYPE_RT
3312 },
3313 {
3314 .name = "musb1",
3315 .pa_start = 0x47401800,
3316 .pa_end = 0x47401800 + SZ_2K - 1,
3317 .flags = ADDR_TYPE_RT
3318 },
3319 { }
3320 };
3321
3322 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3323 .master = &am33xx_l3_s_hwmod,
3324 .slave = &am33xx_usbss_hwmod,
3325 .clk = "l3s_gclk",
3326 .addr = am33xx_usbss_addr_space,
3327 .user = OCP_USER_MPU,
3328 .flags = OCPIF_SWSUP_IDLE,
3329 };
3330
3331 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3332 &am33xx_l4_fw__emif_fw,
3333 &am33xx_l3_main__emif,
3334 &am33xx_mpu__l3_main,
3335 &am33xx_mpu__prcm,
3336 &am33xx_l3_s__l4_ls,
3337 &am33xx_l3_s__l4_wkup,
3338 &am33xx_l3_s__l4_fw,
3339 &am33xx_l3_main__l4_hs,
3340 &am33xx_l3_main__l3_s,
3341 &am33xx_l3_main__l3_instr,
3342 &am33xx_l3_main__gfx,
3343 &am33xx_l3_s__l3_main,
3344 &am33xx_pruss__l3_main,
3345 &am33xx_wkup_m3__l4_wkup,
3346 &am33xx_gfx__l3_main,
3347 &am33xx_l4_wkup__wkup_m3,
3348 &am33xx_l4_wkup__control,
3349 &am33xx_l4_wkup__smartreflex0,
3350 &am33xx_l4_wkup__smartreflex1,
3351 &am33xx_l4_wkup__uart1,
3352 &am33xx_l4_wkup__timer1,
3353 &am33xx_l4_wkup__rtc,
3354 &am33xx_l4_wkup__i2c1,
3355 &am33xx_l4_wkup__gpio0,
3356 &am33xx_l4_wkup__adc_tsc,
3357 &am33xx_l4_wkup__wd_timer1,
3358 &am33xx_l4_hs__pruss,
3359 &am33xx_l4_per__dcan0,
3360 &am33xx_l4_per__dcan1,
3361 &am33xx_l4_per__gpio1,
3362 &am33xx_l4_per__gpio2,
3363 &am33xx_l4_per__gpio3,
3364 &am33xx_l4_per__i2c2,
3365 &am33xx_l4_per__i2c3,
3366 &am33xx_l4_per__mailbox,
3367 &am33xx_l4_ls__mcasp0,
3368 &am33xx_l3_s__mcasp0_data,
3369 &am33xx_l4_ls__mcasp1,
3370 &am33xx_l3_s__mcasp1_data,
3371 &am33xx_l4_ls__mmc0,
3372 &am33xx_l4_ls__mmc1,
3373 &am33xx_l3_s__mmc2,
3374 &am33xx_l4_ls__timer2,
3375 &am33xx_l4_ls__timer3,
3376 &am33xx_l4_ls__timer4,
3377 &am33xx_l4_ls__timer5,
3378 &am33xx_l4_ls__timer6,
3379 &am33xx_l4_ls__timer7,
3380 &am33xx_l3_main__tpcc,
3381 &am33xx_l4_ls__uart2,
3382 &am33xx_l4_ls__uart3,
3383 &am33xx_l4_ls__uart4,
3384 &am33xx_l4_ls__uart5,
3385 &am33xx_l4_ls__uart6,
3386 &am33xx_l4_ls__spinlock,
3387 &am33xx_l4_ls__elm,
3388 &am33xx_l4_ls__ehrpwm0,
3389 &am33xx_l4_ls__ehrpwm1,
3390 &am33xx_l4_ls__ehrpwm2,
3391 &am33xx_l4_ls__ecap0,
3392 &am33xx_l4_ls__ecap1,
3393 &am33xx_l4_ls__ecap2,
3394 &am33xx_l3_s__gpmc,
3395 &am33xx_l3_main__lcdc,
3396 &am33xx_l4_ls__mcspi0,
3397 &am33xx_l4_ls__mcspi1,
3398 &am33xx_l3_main__tptc0,
3399 &am33xx_l3_main__tptc1,
3400 &am33xx_l3_main__tptc2,
3401 &am33xx_l3_s__usbss,
3402 &am33xx_l4_hs__cpgmac0,
3403 &am33xx_cpgmac0__mdio,
3404 NULL,
3405 };
3406
3407 int __init am33xx_hwmod_init(void)
3408 {
3409 omap_hwmod_init();
3410 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3411 }
kernel source for telekom puls (alcatel/mediatek)