2 * linux/arch/arm/mach-omap1/pm.c
4 * OMAP Power Management Routines
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/suspend.h>
39 #include <linux/sched.h>
40 #include <linux/proc_fs.h>
41 #include <linux/interrupt.h>
42 #include <linux/sysfs.h>
43 #include <linux/module.h>
45 #include <linux/atomic.h>
46 #include <linux/cpu.h>
48 #include <asm/fncpy.h>
49 #include <asm/system_misc.h>
51 #include <asm/mach/time.h>
52 #include <asm/mach/irq.h>
56 #include <linux/omap-dma.h>
57 #include <plat/dmtimer.h>
59 #include <mach/irqs.h>
66 static unsigned int arm_sleep_save
[ARM_SLEEP_SAVE_SIZE
];
67 static unsigned short dsp_sleep_save
[DSP_SLEEP_SAVE_SIZE
];
68 static unsigned short ulpd_sleep_save
[ULPD_SLEEP_SAVE_SIZE
];
69 static unsigned int mpui7xx_sleep_save
[MPUI7XX_SLEEP_SAVE_SIZE
];
70 static unsigned int mpui1510_sleep_save
[MPUI1510_SLEEP_SAVE_SIZE
];
71 static unsigned int mpui1610_sleep_save
[MPUI1610_SLEEP_SAVE_SIZE
];
73 #ifdef CONFIG_OMAP_32K_TIMER
75 static unsigned short enable_dyn_sleep
= 1;
77 static ssize_t
idle_show(struct kobject
*kobj
, struct kobj_attribute
*attr
,
80 return sprintf(buf
, "%hu\n", enable_dyn_sleep
);
83 static ssize_t
idle_store(struct kobject
*kobj
, struct kobj_attribute
*attr
,
84 const char * buf
, size_t n
)
87 if (sscanf(buf
, "%hu", &value
) != 1 ||
88 (value
!= 0 && value
!= 1)) {
89 printk(KERN_ERR
"idle_sleep_store: Invalid value\n");
92 enable_dyn_sleep
= value
;
96 static struct kobj_attribute sleep_while_idle_attr
=
97 __ATTR(sleep_while_idle
, 0644, idle_show
, idle_store
);
101 static void (*omap_sram_suspend
)(unsigned long r0
, unsigned long r1
) = NULL
;
104 * Let's power down on idle, but only if we are really
105 * idle, because once we start down the path of
106 * going idle we continue to do idle even if we get
107 * a clock tick interrupt . .
109 void omap1_pm_idle(void)
111 extern __u32 arm_idlect1_mask
;
112 __u32 use_idlect1
= arm_idlect1_mask
;
117 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
118 #warning Enable 32kHz OS timer in order to allow sleep states in idle
119 use_idlect1
= use_idlect1
& ~(1 << 9);
122 while (enable_dyn_sleep
) {
124 #ifdef CONFIG_CBUS_TAHVO_USB
125 extern int vbus_active
;
126 /* Clock requirements? */
136 #ifdef CONFIG_OMAP_DM_TIMER
137 use_idlect1
= omap_dm_timer_modify_idlect_mask(use_idlect1
);
140 if (omap_dma_running())
141 use_idlect1
&= ~(1 << 6);
143 /* We should be able to remove the do_sleep variable and multiple
144 * tests above as soon as drivers, timer and DMA code have been fixed.
145 * Even the sleep block count should become obsolete. */
146 if ((use_idlect1
!= ~0) || !do_sleep
) {
148 __u32 saved_idlect1
= omap_readl(ARM_IDLECT1
);
149 if (cpu_is_omap15xx())
150 use_idlect1
&= OMAP1510_BIG_SLEEP_REQUEST
;
152 use_idlect1
&= OMAP1610_IDLECT1_SLEEP_VAL
;
153 omap_writel(use_idlect1
, ARM_IDLECT1
);
154 __asm__
volatile ("mcr p15, 0, r0, c7, c0, 4");
155 omap_writel(saved_idlect1
, ARM_IDLECT1
);
160 omap_sram_suspend(omap_readl(ARM_IDLECT1
),
161 omap_readl(ARM_IDLECT2
));
167 * Configuration of the wakeup event is board specific. For the
168 * moment we put it into this helper function. Later it may move
169 * to board specific files.
171 static void omap_pm_wakeup_setup(void)
174 u32 level2_wake
= OMAP_IRQ_BIT(INT_UART2
);
177 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
178 * and the L2 wakeup interrupts: keypad and UART2. Note that the
179 * drivers must still separately call omap_set_gpio_wakeup() to
180 * wake up to a GPIO interrupt.
182 if (cpu_is_omap7xx())
183 level1_wake
= OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1
) |
184 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ
);
185 else if (cpu_is_omap15xx())
186 level1_wake
= OMAP_IRQ_BIT(INT_GPIO_BANK1
) |
187 OMAP_IRQ_BIT(INT_1510_IH2_IRQ
);
188 else if (cpu_is_omap16xx())
189 level1_wake
= OMAP_IRQ_BIT(INT_GPIO_BANK1
) |
190 OMAP_IRQ_BIT(INT_1610_IH2_IRQ
);
192 omap_writel(~level1_wake
, OMAP_IH1_MIR
);
194 if (cpu_is_omap7xx()) {
195 omap_writel(~level2_wake
, OMAP_IH2_0_MIR
);
196 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ
) |
197 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD
)),
199 } else if (cpu_is_omap15xx()) {
200 level2_wake
|= OMAP_IRQ_BIT(INT_KEYBOARD
);
201 omap_writel(~level2_wake
, OMAP_IH2_MIR
);
202 } else if (cpu_is_omap16xx()) {
203 level2_wake
|= OMAP_IRQ_BIT(INT_KEYBOARD
);
204 omap_writel(~level2_wake
, OMAP_IH2_0_MIR
);
206 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
207 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ
),
209 omap_writel(~0x0, OMAP_IH2_2_MIR
);
210 omap_writel(~0x0, OMAP_IH2_3_MIR
);
213 /* New IRQ agreement, recalculate in cascade order */
214 omap_writel(1, OMAP_IH2_CONTROL
);
215 omap_writel(1, OMAP_IH1_CONTROL
);
218 #define EN_DSPCK 13 /* ARM_CKCTL */
219 #define EN_APICK 6 /* ARM_IDLECT2 */
220 #define DSP_EN 1 /* ARM_RSTCT1 */
222 void omap1_pm_suspend(void)
224 unsigned long arg0
= 0, arg1
= 0;
226 printk(KERN_INFO
"PM: OMAP%x is trying to enter deep sleep...\n",
229 omap_serial_wake_trigger(1);
231 if (!cpu_is_omap15xx())
232 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG
);
235 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
242 * Step 2: save registers
244 * The omap is a strange/beautiful device. The caches, memory
245 * and register state are preserved across power saves.
246 * We have to save and restore very little register state to
249 * Save interrupt, MPUI, ARM and UPLD control registers.
252 if (cpu_is_omap7xx()) {
253 MPUI7XX_SAVE(OMAP_IH1_MIR
);
254 MPUI7XX_SAVE(OMAP_IH2_0_MIR
);
255 MPUI7XX_SAVE(OMAP_IH2_1_MIR
);
256 MPUI7XX_SAVE(MPUI_CTRL
);
257 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG
);
258 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG
);
259 MPUI7XX_SAVE(EMIFS_CONFIG
);
260 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG
);
262 } else if (cpu_is_omap15xx()) {
263 MPUI1510_SAVE(OMAP_IH1_MIR
);
264 MPUI1510_SAVE(OMAP_IH2_MIR
);
265 MPUI1510_SAVE(MPUI_CTRL
);
266 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG
);
267 MPUI1510_SAVE(MPUI_DSP_API_CONFIG
);
268 MPUI1510_SAVE(EMIFS_CONFIG
);
269 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG
);
270 } else if (cpu_is_omap16xx()) {
271 MPUI1610_SAVE(OMAP_IH1_MIR
);
272 MPUI1610_SAVE(OMAP_IH2_0_MIR
);
273 MPUI1610_SAVE(OMAP_IH2_1_MIR
);
274 MPUI1610_SAVE(OMAP_IH2_2_MIR
);
275 MPUI1610_SAVE(OMAP_IH2_3_MIR
);
276 MPUI1610_SAVE(MPUI_CTRL
);
277 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG
);
278 MPUI1610_SAVE(MPUI_DSP_API_CONFIG
);
279 MPUI1610_SAVE(EMIFS_CONFIG
);
280 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG
);
284 ARM_SAVE(ARM_IDLECT1
);
285 ARM_SAVE(ARM_IDLECT2
);
286 if (!(cpu_is_omap15xx()))
287 ARM_SAVE(ARM_IDLECT3
);
288 ARM_SAVE(ARM_EWUPCT
);
289 ARM_SAVE(ARM_RSTCT1
);
290 ARM_SAVE(ARM_RSTCT2
);
292 ULPD_SAVE(ULPD_CLOCK_CTRL
);
293 ULPD_SAVE(ULPD_STATUS_REQ
);
295 /* (Step 3 removed - we now allow deep sleep by default) */
298 * Step 4: OMAP DSP Shutdown
302 omap_writew(omap_readw(ARM_RSTCT1
) & ~(1 << DSP_EN
), ARM_RSTCT1
);
304 /* shut down dsp_ck */
305 if (!cpu_is_omap7xx())
306 omap_writew(omap_readw(ARM_CKCTL
) & ~(1 << EN_DSPCK
), ARM_CKCTL
);
308 /* temporarily enabling api_ck to access DSP registers */
309 omap_writew(omap_readw(ARM_IDLECT2
) | 1 << EN_APICK
, ARM_IDLECT2
);
311 /* save DSP registers */
312 DSP_SAVE(DSP_IDLECT2
);
314 /* Stop all DSP domain clocks */
315 __raw_writew(0, DSP_IDLECT2
);
318 * Step 5: Wakeup Event Setup
321 omap_pm_wakeup_setup();
324 * Step 6: ARM and Traffic controller shutdown
327 /* disable ARM watchdog */
328 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE
);
329 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE
);
332 * Step 6b: ARM and Traffic controller shutdown
334 * Step 6 continues here. Prepare jump to power management
335 * assembly code in internal SRAM.
337 * Since the omap_cpu_suspend routine has been copied to
338 * SRAM, we'll do an indirect procedure call to it and pass the
339 * contents of arm_idlect1 and arm_idlect2 so it can restore
340 * them when it wakes up and it will return.
343 arg0
= arm_sleep_save
[ARM_SLEEP_SAVE_ARM_IDLECT1
];
344 arg1
= arm_sleep_save
[ARM_SLEEP_SAVE_ARM_IDLECT2
];
347 * Step 6c: ARM and Traffic controller shutdown
349 * Jump to assembly code. The processor will stay there
352 omap_sram_suspend(arg0
, arg1
);
355 * If we are here, processor is woken up!
362 /* again temporarily enabling api_ck to access DSP registers */
363 omap_writew(omap_readw(ARM_IDLECT2
) | 1 << EN_APICK
, ARM_IDLECT2
);
365 /* Restore DSP domain clocks */
366 DSP_RESTORE(DSP_IDLECT2
);
369 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
372 if (!(cpu_is_omap15xx()))
373 ARM_RESTORE(ARM_IDLECT3
);
374 ARM_RESTORE(ARM_CKCTL
);
375 ARM_RESTORE(ARM_EWUPCT
);
376 ARM_RESTORE(ARM_RSTCT1
);
377 ARM_RESTORE(ARM_RSTCT2
);
378 ARM_RESTORE(ARM_SYSST
);
379 ULPD_RESTORE(ULPD_CLOCK_CTRL
);
380 ULPD_RESTORE(ULPD_STATUS_REQ
);
382 if (cpu_is_omap7xx()) {
383 MPUI7XX_RESTORE(EMIFS_CONFIG
);
384 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG
);
385 MPUI7XX_RESTORE(OMAP_IH1_MIR
);
386 MPUI7XX_RESTORE(OMAP_IH2_0_MIR
);
387 MPUI7XX_RESTORE(OMAP_IH2_1_MIR
);
388 } else if (cpu_is_omap15xx()) {
389 MPUI1510_RESTORE(MPUI_CTRL
);
390 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG
);
391 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG
);
392 MPUI1510_RESTORE(EMIFS_CONFIG
);
393 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG
);
394 MPUI1510_RESTORE(OMAP_IH1_MIR
);
395 MPUI1510_RESTORE(OMAP_IH2_MIR
);
396 } else if (cpu_is_omap16xx()) {
397 MPUI1610_RESTORE(MPUI_CTRL
);
398 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG
);
399 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG
);
400 MPUI1610_RESTORE(EMIFS_CONFIG
);
401 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG
);
403 MPUI1610_RESTORE(OMAP_IH1_MIR
);
404 MPUI1610_RESTORE(OMAP_IH2_0_MIR
);
405 MPUI1610_RESTORE(OMAP_IH2_1_MIR
);
406 MPUI1610_RESTORE(OMAP_IH2_2_MIR
);
407 MPUI1610_RESTORE(OMAP_IH2_3_MIR
);
410 if (!cpu_is_omap15xx())
411 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG
);
414 * Re-enable interrupts
420 omap_serial_wake_trigger(0);
422 printk(KERN_INFO
"PM: OMAP%x is re-starting from deep sleep...\n",
426 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
427 static int g_read_completed
;
430 * Read system PM registers for debugging
432 static int omap_pm_read_proc(
434 char **my_first_byte
,
440 int my_buffer_offset
= 0;
441 char * const my_base
= page_buffer
;
444 ARM_SAVE(ARM_IDLECT1
);
445 ARM_SAVE(ARM_IDLECT2
);
446 if (!(cpu_is_omap15xx()))
447 ARM_SAVE(ARM_IDLECT3
);
448 ARM_SAVE(ARM_EWUPCT
);
449 ARM_SAVE(ARM_RSTCT1
);
450 ARM_SAVE(ARM_RSTCT2
);
453 ULPD_SAVE(ULPD_IT_STATUS
);
454 ULPD_SAVE(ULPD_CLOCK_CTRL
);
455 ULPD_SAVE(ULPD_SOFT_REQ
);
456 ULPD_SAVE(ULPD_STATUS_REQ
);
457 ULPD_SAVE(ULPD_DPLL_CTRL
);
458 ULPD_SAVE(ULPD_POWER_CTRL
);
460 if (cpu_is_omap7xx()) {
461 MPUI7XX_SAVE(MPUI_CTRL
);
462 MPUI7XX_SAVE(MPUI_DSP_STATUS
);
463 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG
);
464 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG
);
465 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG
);
466 MPUI7XX_SAVE(EMIFS_CONFIG
);
467 } else if (cpu_is_omap15xx()) {
468 MPUI1510_SAVE(MPUI_CTRL
);
469 MPUI1510_SAVE(MPUI_DSP_STATUS
);
470 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG
);
471 MPUI1510_SAVE(MPUI_DSP_API_CONFIG
);
472 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG
);
473 MPUI1510_SAVE(EMIFS_CONFIG
);
474 } else if (cpu_is_omap16xx()) {
475 MPUI1610_SAVE(MPUI_CTRL
);
476 MPUI1610_SAVE(MPUI_DSP_STATUS
);
477 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG
);
478 MPUI1610_SAVE(MPUI_DSP_API_CONFIG
);
479 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG
);
480 MPUI1610_SAVE(EMIFS_CONFIG
);
483 if (virtual_start
== 0) {
484 g_read_completed
= 0;
486 my_buffer_offset
+= sprintf(my_base
+ my_buffer_offset
,
487 "ARM_CKCTL_REG: 0x%-8x \n"
488 "ARM_IDLECT1_REG: 0x%-8x \n"
489 "ARM_IDLECT2_REG: 0x%-8x \n"
490 "ARM_IDLECT3_REG: 0x%-8x \n"
491 "ARM_EWUPCT_REG: 0x%-8x \n"
492 "ARM_RSTCT1_REG: 0x%-8x \n"
493 "ARM_RSTCT2_REG: 0x%-8x \n"
494 "ARM_SYSST_REG: 0x%-8x \n"
495 "ULPD_IT_STATUS_REG: 0x%-4x \n"
496 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
497 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
498 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
499 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
500 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
502 ARM_SHOW(ARM_IDLECT1
),
503 ARM_SHOW(ARM_IDLECT2
),
504 ARM_SHOW(ARM_IDLECT3
),
505 ARM_SHOW(ARM_EWUPCT
),
506 ARM_SHOW(ARM_RSTCT1
),
507 ARM_SHOW(ARM_RSTCT2
),
509 ULPD_SHOW(ULPD_IT_STATUS
),
510 ULPD_SHOW(ULPD_CLOCK_CTRL
),
511 ULPD_SHOW(ULPD_SOFT_REQ
),
512 ULPD_SHOW(ULPD_DPLL_CTRL
),
513 ULPD_SHOW(ULPD_STATUS_REQ
),
514 ULPD_SHOW(ULPD_POWER_CTRL
));
516 if (cpu_is_omap7xx()) {
517 my_buffer_offset
+= sprintf(my_base
+ my_buffer_offset
,
518 "MPUI7XX_CTRL_REG 0x%-8x \n"
519 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
520 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
521 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
522 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
523 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
524 MPUI7XX_SHOW(MPUI_CTRL
),
525 MPUI7XX_SHOW(MPUI_DSP_STATUS
),
526 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG
),
527 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG
),
528 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG
),
529 MPUI7XX_SHOW(EMIFS_CONFIG
));
530 } else if (cpu_is_omap15xx()) {
531 my_buffer_offset
+= sprintf(my_base
+ my_buffer_offset
,
532 "MPUI1510_CTRL_REG 0x%-8x \n"
533 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
534 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
535 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
536 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
537 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
538 MPUI1510_SHOW(MPUI_CTRL
),
539 MPUI1510_SHOW(MPUI_DSP_STATUS
),
540 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG
),
541 MPUI1510_SHOW(MPUI_DSP_API_CONFIG
),
542 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG
),
543 MPUI1510_SHOW(EMIFS_CONFIG
));
544 } else if (cpu_is_omap16xx()) {
545 my_buffer_offset
+= sprintf(my_base
+ my_buffer_offset
,
546 "MPUI1610_CTRL_REG 0x%-8x \n"
547 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
548 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
549 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
550 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
551 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
552 MPUI1610_SHOW(MPUI_CTRL
),
553 MPUI1610_SHOW(MPUI_DSP_STATUS
),
554 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG
),
555 MPUI1610_SHOW(MPUI_DSP_API_CONFIG
),
556 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG
),
557 MPUI1610_SHOW(EMIFS_CONFIG
));
561 } else if (g_read_completed
>= 1) {
567 *my_first_byte
= page_buffer
;
568 return my_buffer_offset
;
571 static void omap_pm_init_proc(void)
573 /* XXX Appears to leak memory */
574 create_proc_read_entry("driver/omap_pm",
575 S_IWUSR
| S_IRUGO
, NULL
,
576 omap_pm_read_proc
, NULL
);
579 #endif /* DEBUG && CONFIG_PROC_FS */
582 * omap_pm_prepare - Do preliminary suspend work.
585 static int omap_pm_prepare(void)
587 /* We cannot sleep in idle until we have resumed */
588 cpu_idle_poll_ctrl(true);
594 * omap_pm_enter - Actually enter a sleep state.
595 * @state: State we're entering.
599 static int omap_pm_enter(suspend_state_t state
)
603 case PM_SUSPEND_STANDBY
:
616 * omap_pm_finish - Finish up suspend sequence.
618 * This is called after we wake back up (or if entering the sleep state
622 static void omap_pm_finish(void)
624 cpu_idle_poll_ctrl(false);
628 static irqreturn_t
omap_wakeup_interrupt(int irq
, void *dev
)
633 static struct irqaction omap_wakeup_irq
= {
634 .name
= "peripheral wakeup",
635 .flags
= IRQF_DISABLED
,
636 .handler
= omap_wakeup_interrupt
641 static const struct platform_suspend_ops omap_pm_ops
= {
642 .prepare
= omap_pm_prepare
,
643 .enter
= omap_pm_enter
,
644 .finish
= omap_pm_finish
,
645 .valid
= suspend_valid_only_mem
,
648 static int __init
omap_pm_init(void)
651 #ifdef CONFIG_OMAP_32K_TIMER
655 if (!cpu_class_is_omap1())
658 printk("Power Management for TI OMAP.\n");
661 * We copy the assembler sleep/wakeup routines to SRAM.
662 * These routines need to be in SRAM as that's the only
663 * memory the MPU can see when it wakes up.
665 if (cpu_is_omap7xx()) {
666 omap_sram_suspend
= omap_sram_push(omap7xx_cpu_suspend
,
667 omap7xx_cpu_suspend_sz
);
668 } else if (cpu_is_omap15xx()) {
669 omap_sram_suspend
= omap_sram_push(omap1510_cpu_suspend
,
670 omap1510_cpu_suspend_sz
);
671 } else if (cpu_is_omap16xx()) {
672 omap_sram_suspend
= omap_sram_push(omap1610_cpu_suspend
,
673 omap1610_cpu_suspend_sz
);
676 if (omap_sram_suspend
== NULL
) {
677 printk(KERN_ERR
"PM not initialized: Missing SRAM support\n");
681 arm_pm_idle
= omap1_pm_idle
;
683 if (cpu_is_omap7xx())
684 setup_irq(INT_7XX_WAKE_UP_REQ
, &omap_wakeup_irq
);
685 else if (cpu_is_omap16xx())
686 setup_irq(INT_1610_WAKE_UP_REQ
, &omap_wakeup_irq
);
688 /* Program new power ramp-up time
689 * (0 for most boards since we don't lower voltage when in deep sleep)
691 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL
, ULPD_SETUP_ANALOG_CELL_3
);
693 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
694 omap_writew(ULPD_POWER_CTRL_REG_VAL
, ULPD_POWER_CTRL
);
696 /* Configure IDLECT3 */
697 if (cpu_is_omap7xx())
698 omap_writel(OMAP7XX_IDLECT3_VAL
, OMAP7XX_IDLECT3
);
699 else if (cpu_is_omap16xx())
700 omap_writel(OMAP1610_IDLECT3_VAL
, OMAP1610_IDLECT3
);
702 suspend_set_ops(&omap_pm_ops
);
704 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
708 #ifdef CONFIG_OMAP_32K_TIMER
709 error
= sysfs_create_file(power_kobj
, &sleep_while_idle_attr
.attr
);
711 printk(KERN_ERR
"sysfs_create_file failed: %d\n", error
);
714 if (cpu_is_omap16xx()) {
715 /* configure LOW_PWR pin */
716 omap_cfg_reg(T20_1610_LOW_PWR
);
721 __initcall(omap_pm_init
);