1 #define __MT_CLKMGR_C__
3 #include <linux/kernel.h>
4 #include <linux/module.h>
5 #include <linux/types.h>
6 #include <linux/delay.h>
7 #include <linux/list.h>
8 #include <linux/slab.h>
9 #include <linux/spinlock.h>
10 #include <linux/proc_fs.h>
12 #include <asm/uaccess.h>
14 #include <linux/device.h>
15 #include <linux/platform_device.h>
17 #include <mach/mt_typedefs.h>
18 #include <mach/sync_write.h>
19 #include <mach/mt_clkmgr.h>
20 #include <mach/mt_dcm.h>
21 #include <mach/mt_spm.h>
22 #include <mach/mt_spm_mtcmos.h>
23 #include <mach/mt_spm_sleep.h>
24 #include <mach/mt_freqhopping.h>
25 #include <mach/mt_gpufreq.h>
26 #include <linux/earlysuspend.h>
29 #define DISABLE_BUG_ON_CNT 0
30 #define WORKAROUND_DPI0_MUX 1
31 #define WORKAROUND_DAPC 1
35 #include <linux/seq_file.h>
36 #endif /* CLKMGR_8127 */
38 /* #define CONFIG_CLKMGR_BRINGUP */
40 /* #define CLK_LOG_TOP */
43 /* #define MUX_LOG_TOP */
45 /* #define PLL_LOG_TOP */
48 /************************************************
49 ********** log debug **********
50 ************************************************/
55 #include <linux/xlog.h>
57 #define TAG "Power/clkmgr"
59 #define clk_err(fmt, args...) \
60 xlog_printk(ANDROID_LOG_ERROR, TAG, fmt, ##args)
61 #define clk_warn(fmt, args...) \
62 xlog_printk(ANDROID_LOG_WARN, TAG, fmt, ##args)
63 #define clk_info(fmt, args...) \
64 xlog_printk(ANDROID_LOG_INFO, TAG, fmt, ##args)
65 #define clk_dbg(fmt, args...) \
66 xlog_printk(ANDROID_LOG_DEBUG, TAG, fmt, ##args)
67 #define clk_ver(fmt, args...) \
68 xlog_printk(ANDROID_LOG_VERBOSE, TAG, fmt, ##args)
72 #define TAG "[Power/clkmgr] "
74 #define clk_err(fmt, args...) \
75 pr_err(TAG fmt, ##args)
76 #define clk_warn(fmt, args...) \
77 pr_warn(TAG fmt, ##args)
78 #define clk_info(fmt, args...) \
79 pr_notice(TAG fmt, ##args)
80 #define clk_dbg(fmt, args...) \
81 pr_info(TAG fmt, ##args)
82 #define clk_ver(fmt, args...) \
83 pr_debug(TAG fmt, ##args)
89 /************************************************
90 ********** macro / functions **********
91 ************************************************/
93 #define BITS(_bits_, _val_) ((BIT((1 ? _bits_) + 1) - BIT((0 ? _bits_))) & (_val_ << (0 ? _bits_)))
94 #define BITMASK(_bits_) (BIT((1 ? _bits_) + 1) - BIT((0 ? _bits_)))
95 #define ABS_DIFF(a, b) ((a) > (b) ? (a) - (b) : (b) - (a))
98 /************************************************
99 ********** register access **********
100 ************************************************/
102 #define clk_readl(addr) \
105 #define clk_writel(addr, val) \
106 mt65xx_reg_sync_writel(val, addr)
108 #define clk_setl(addr, val) \
109 mt65xx_reg_sync_writel(clk_readl(addr) | (val), addr)
111 #define clk_clrl(addr, val) \
112 mt65xx_reg_sync_writel(clk_readl(addr) & ~(val), addr)
114 #define clk_writel_mask(addr, mask, val) \
115 clk_writel(addr, (clk_readl(addr) & ~(mask)) | (val))
119 /************************************************
120 ********** struct definition **********
121 ************************************************/
123 /* #define CONFIG_CLKMGR_STAT */
127 int (*get_state
)(struct pll
*pll
);
128 void (*enable
)(struct pll
*pll
);
129 void (*disable
)(struct pll
*pll
);
130 void (*fsel
)(struct pll
*pll
, unsigned int value
);
131 int (*dump_regs
)(struct pll
*pll
, unsigned int *ptr
);
132 unsigned int (*vco_calc
)(struct pll
*pll
);
133 int (*hp_enable
)(struct pll
*pll
);
134 int (*hp_disable
)(struct pll
*pll
);
136 unsigned int (*get_postdiv
)(struct pll
*pll
);
137 void (*set_postdiv
)(struct pll
*pll
, unsigned int postdiv
);
138 unsigned int (*get_pcw
)(struct pll
*pll
);
139 void (*set_pcw
)(struct pll
*pll
, unsigned int pcw
);
140 int (*set_freq
)(struct pll
*pll
, unsigned int freq
);
141 #endif /* CLKMGR_8127 */
151 unsigned int en_mask
;
152 unsigned int base_addr
;
153 unsigned int pwr_addr
;
157 #ifdef CONFIG_CLKMGR_STAT
158 struct list_head head
;
165 int (*enable
)(struct subsys
*sys
);
166 int (*disable
)(struct subsys
*sys
);
167 int (*get_state
)(struct subsys
*sys
);
168 int (*dump_regs
)(struct subsys
*sys
, unsigned int *ptr
);
177 unsigned int default_sta
;
178 unsigned int sta_mask
; /* mask in PWR_STATUS */
179 unsigned int ctl_addr
;
180 struct subsys_ops
*ops
;
181 struct cg_grp
*start
;
182 unsigned int nr_grps
;
184 #ifdef CONFIG_CLKMGR_STAT
185 struct list_head head
;
192 void (*sel
)(struct clkmux
*mux
, unsigned int clksrc
);
193 void (*enable
)(struct clkmux
*mux
);
194 void (*disable
)(struct clkmux
*mux
);
200 unsigned int base_addr
;
201 unsigned int sel_mask
;
202 unsigned int pdn_mask
;
204 unsigned int nr_inputs
;
205 struct clkmux_ops
*ops
;
206 struct clkmux
*parent
;
207 struct clkmux
*siblings
;
209 #ifdef CONFIG_CLKMGR_STAT
210 struct list_head head
;
217 int (*prepare
)(struct cg_grp
*grp
);
218 int (*finished
)(struct cg_grp
*grp
);
219 unsigned int (*get_state
)(struct cg_grp
*grp
);
220 int (*dump_regs
)(struct cg_grp
*grp
, unsigned int *ptr
);
225 unsigned int set_addr
;
226 unsigned int clr_addr
;
227 unsigned int sta_addr
;
230 struct cg_grp_ops
*ops
;
237 int (*get_state
)(struct cg_clk
*clk
);
238 int (*check_validity
)(struct cg_clk
*clk
); /* 1: valid, 0: invalid */
239 int (*enable
)(struct cg_clk
*clk
);
240 int (*disable
)(struct cg_clk
*clk
);
248 struct cg_clk_ops
*ops
;
251 struct cg_clk
*parent
;
254 #endif /* CLKMGR_8127 */
255 #ifdef CONFIG_CLKMGR_STAT
256 struct list_head head
;
261 #ifdef CONFIG_CLKMGR_STAT
263 struct list_head link
;
265 unsigned int cnt_off
;
272 /************************************************
273 ********** global variablies **********
274 ************************************************/
279 static int initialized
;
281 static struct pll plls
[NR_PLLS
];
282 static struct subsys syss
[NR_SYSS
];
283 static struct clkmux muxs
[NR_MUXS
];
284 static struct cg_grp grps
[NR_GRPS
];
285 static struct cg_clk clks
[NR_CLKS
];
289 /************************************************
290 ********** spin lock protect **********
291 ************************************************/
293 static DEFINE_SPINLOCK(clock_lock
);
295 #define clkmgr_lock(flags) \
296 spin_lock_irqsave(&clock_lock, flags)
298 #define clkmgr_unlock(flags) \
299 spin_unlock_irqrestore(&clock_lock, flags)
301 #define clkmgr_locked() \
302 spin_is_locked(&clock_lock)
307 int clkmgr_is_locked(void)
309 return clkmgr_locked();
311 EXPORT_SYMBOL(clkmgr_is_locked
);
313 #endif /* !CLKMGR_8127 */
317 /************************************************
318 ********** clkmgr stat debug **********
319 ************************************************/
321 #ifdef CONFIG_CLKMGR_STAT
322 void update_stat_locked(struct list_head
*head
, char *name
, int op
)
324 struct list_head
*pos
= NULL
;
325 struct stat_node
*node
= NULL
;
326 int len
= strlen(name
);
329 list_for_each(pos
, head
) {
330 node
= list_entry(pos
, struct stat_node
, link
);
331 if (!strncmp(node
->name
, name
, len
)) {
339 node
= kzalloc(sizeof(*node
) + len
+ 1, GFP_ATOMIC
);
341 clk_err("[%s]: malloc stat node for %s fail\n", __func__
, name
);
344 memcpy(node
->name
, name
, len
);
345 list_add_tail(&node
->link
, head
);
358 /************************************************
359 ********** function declaration **********
360 ************************************************/
362 static int pll_enable_locked(struct pll
*pll
);
363 static int pll_disable_locked(struct pll
*pll
);
365 static int sys_enable_locked(struct subsys
*sys
);
366 static int sys_disable_locked(struct subsys
*sys
, int force_off
);
368 static void mux_enable_locked(struct clkmux
*mux
);
369 static void mux_disable_locked(struct clkmux
*mux
);
371 static int clk_enable_locked(struct cg_clk
*clk
);
372 static int clk_disable_locked(struct cg_clk
*clk
);
375 static inline int pll_enable_internal(struct pll
*pll
, char *name
)
378 err
= pll_enable_locked(pll
);
379 #ifdef CONFIG_CLKMGR_STAT
380 update_stat_locked(&pll
->head
, name
, 1);
385 static inline int pll_disable_internal(struct pll
*pll
, char *name
)
388 err
= pll_disable_locked(pll
);
389 #ifdef CONFIG_CLKMGR_STAT
390 update_stat_locked(&pll
->head
, name
, 0);
396 static inline int subsys_enable_internal(struct subsys
*sys
, char *name
)
399 err
= sys_enable_locked(sys
);
400 #ifdef CONFIG_CLKMGR_STAT
401 update_stat_locked(&sys
->head
, name
, 1);
406 static inline int subsys_disable_internal(struct subsys
*sys
, int force_off
, char *name
)
409 err
= sys_disable_locked(sys
, force_off
);
410 #ifdef CONFIG_CLKMGR_STAT
411 update_stat_locked(&sys
->head
, name
, 0);
417 static inline void mux_enable_internal(struct clkmux
*mux
, char *name
)
419 mux_enable_locked(mux
);
420 #ifdef CONFIG_CLKMGR_STAT
421 update_stat_locked(&mux
->head
, name
, 1);
425 static inline void mux_disable_internal(struct clkmux
*mux
, char *name
)
427 mux_disable_locked(mux
);
428 #ifdef CONFIG_CLKMGR_STAT
429 update_stat_locked(&mux
->head
, name
, 0);
434 static inline int clk_enable_internal(struct cg_clk
*clk
, char *name
)
437 err
= clk_enable_locked(clk
);
438 #ifdef CONFIG_CLKMGR_STAT
439 update_stat_locked(&clk
->head
, name
, 1);
444 static inline int clk_disable_internal(struct cg_clk
*clk
, char *name
)
447 err
= clk_disable_locked(clk
);
448 #ifdef CONFIG_CLKMGR_STAT
449 update_stat_locked(&clk
->head
, name
, 0);
456 /************************************************
457 ********** pll part **********
458 ************************************************/
460 #define PLL_TYPE_SDM 0
461 #define PLL_TYPE_LC 1
463 #define HAVE_RST_BAR (0x1 << 0)
464 #define HAVE_PLL_HP (0x1 << 1)
465 #define HAVE_FIX_FRQ (0x1 << 2)
466 #define Others (0x1 << 3)
468 #define RST_BAR_MASK 0x1000000
470 static struct pll_ops arm_pll_ops
;
471 static struct pll_ops sdm_pll_ops
;
474 static struct pll_ops aud_pll_ops
;
475 #endif /* CLKMGR_8127 */
477 static struct pll plls
[NR_PLLS
] = {
479 .name
= __stringify(ARMPLL
),
480 .type
= PLL_TYPE_SDM
,
482 .en_mask
= 0x00000001,
483 .base_addr
= ARMPLL_CON0
,
484 .pwr_addr
= ARMPLL_PWR_CON0
,
486 .hp_id
= MT658X_FH_ARM_PLL
,
490 .name
= __stringify(MAINPLL
),
491 .type
= PLL_TYPE_SDM
,
492 .feat
= HAVE_PLL_HP
| HAVE_RST_BAR
,
493 .en_mask
= 0x78000001,
494 .base_addr
= MAINPLL_CON0
,
495 .pwr_addr
= MAINPLL_PWR_CON0
,
497 .hp_id
= MT658X_FH_MAIN_PLL
,
501 .name
= __stringify(MSDCPLL
),
502 .type
= PLL_TYPE_SDM
,
504 .en_mask
= 0x00000001,
505 .base_addr
= MSDCPLL_CON0
,
506 .pwr_addr
= MSDCPLL_PWR_CON0
,
508 .hp_id
= MT658X_FH_MSDC_PLL
,
512 .name
= __stringify(UNIVPLL
),
513 .type
= PLL_TYPE_SDM
,
514 .feat
= HAVE_RST_BAR
| HAVE_FIX_FRQ
,
515 .en_mask
= 0xFC000001,
516 .base_addr
= UNIVPLL_CON0
,
517 .pwr_addr
= UNIVPLL_PWR_CON0
,
521 .name
= __stringify(MMPLL
),
522 .type
= PLL_TYPE_SDM
,
524 .en_mask
= 0x00000001,
525 .base_addr
= MMPLL_CON0
,
526 .pwr_addr
= MMPLL_PWR_CON0
,
528 .hp_id
= MT658X_FH_MM_PLL
,
532 .name
= __stringify(VENCPLL
),
533 .type
= PLL_TYPE_SDM
,
535 .en_mask
= 0x00000001,
536 .base_addr
= VENCPLL_CON0
,
537 .pwr_addr
= VENCPLL_PWR_CON0
,
539 .hp_id
= MT658X_FH_VENC_PLL
,
543 .name
= __stringify(TVDPLL
),
544 .type
= PLL_TYPE_SDM
,
546 .en_mask
= 0x00000001,
547 .base_addr
= TVDPLL_CON0
,
548 .pwr_addr
= TVDPLL_PWR_CON0
,
550 .hp_id
= MT658X_FH_TVD_PLL
,
554 .name
= __stringify(LVDSPLL
),
555 .type
= PLL_TYPE_SDM
,
557 .en_mask
= 0x00000001,
558 .base_addr
= LVDSPLL_CON0
,
559 .pwr_addr
= LVDSPLL_PWR_CON0
,
561 .hp_id
= MT658X_FH_LVDS_PLL
,
565 .name
= __stringify(AUDPLL
),
566 .type
= PLL_TYPE_SDM
,
568 .en_mask
= 0x00000001,
569 .base_addr
= AUDPLL_CON0
,
570 .pwr_addr
= AUDPLL_PWR_CON0
,
575 static struct pll
*id_to_pll(unsigned int id
)
577 return id
< NR_PLLS
? plls
+ id
: NULL
;
580 #define PLL_PWR_ON (0x1 << 0)
581 #define PLL_ISO_EN (0x1 << 1)
583 #define SDM_PLL_N_INFO_MASK 0x001FFFFF
584 #define UNIV_SDM_PLL_N_INFO_MASK 0x001fc000
585 #define AUD_SDM_PLL_N_INFO_MASK 0x7FFFFFFF
586 #define SDM_PLL_N_INFO_CHG 0x80000000
587 #define ARMPLL_POSDIV_MASK 0x07000000
589 #define PLL_FBKDIV_MASK 0x00007F00
590 #define PLL_FBKDIV_OFFSET 0x8
593 static int pll_get_state_op(struct pll
*pll
)
595 return clk_readl(pll
->base_addr
) & 0x1;
598 static void sdm_pll_enable_op(struct pll
*pll
)
601 clk_dbg("[%s]: pll->name=%s\n", __func__
, pll
->name
);
604 clk_setl(pll
->pwr_addr
, PLL_PWR_ON
);
606 clk_clrl(pll
->pwr_addr
, PLL_ISO_EN
);
608 clk_setl(pll
->base_addr
, pll
->en_mask
);
611 if (pll
->feat
& HAVE_RST_BAR
)
612 clk_setl(pll
->base_addr
, RST_BAR_MASK
);
615 static void sdm_pll_disable_op(struct pll
*pll
)
618 clk_dbg("[%s]: pll->name=%s\n", __func__
, pll
->name
);
621 if (pll
->feat
& HAVE_RST_BAR
)
622 clk_clrl(pll
->base_addr
, RST_BAR_MASK
);
624 clk_clrl(pll
->base_addr
, 0x1);
626 clk_setl(pll
->pwr_addr
, PLL_ISO_EN
);
627 clk_clrl(pll
->pwr_addr
, PLL_PWR_ON
);
630 static void sdm_pll_fsel_op(struct pll
*pll
, unsigned int value
)
632 unsigned int ctrl_value
;
634 ctrl_value
= clk_readl(pll
->base_addr
+ 4);
635 if (pll
->base_addr
== UNIVPLL_CON0
) {
636 ctrl_value
&= ~UNIV_SDM_PLL_N_INFO_MASK
;
637 ctrl_value
|= value
& UNIV_SDM_PLL_N_INFO_MASK
;
638 } else if (pll
->base_addr
== AUDPLL_CON0
) {
639 ctrl_value
&= ~AUD_SDM_PLL_N_INFO_MASK
;
640 ctrl_value
|= value
& AUD_SDM_PLL_N_INFO_MASK
;
642 ctrl_value
&= ~SDM_PLL_N_INFO_MASK
;
643 ctrl_value
|= value
& SDM_PLL_N_INFO_MASK
;
646 ctrl_value
|= SDM_PLL_N_INFO_CHG
;
648 clk_writel(pll
->base_addr
+ 4, ctrl_value
);
652 static int sdm_pll_dump_regs_op(struct pll
*pll
, unsigned int *ptr
)
654 *(ptr
) = clk_readl(pll
->base_addr
);
655 *(++ptr
) = clk_readl(pll
->base_addr
+ 4);
656 *(++ptr
) = clk_readl(pll
->pwr_addr
);
662 static const unsigned int pll_posdiv_map
[8] = {1, 2, 4, 8, 16, 16, 16, 16};
665 static unsigned int sdm_pll_get_postdiv_op(struct pll
*pll
)
667 unsigned int con0
= clk_readl(pll
->base_addr
); /* PLL_CON0 */
668 unsigned int posdiv
= (con0
& BITMASK(6 : 4)) >> 4; /* bit[6:4] */
674 static void sdm_pll_set_postdiv_op(struct pll
*pll
, unsigned int postdiv
)
676 unsigned con0_addr
= pll
->base_addr
;
677 unsigned int con0_value
= clk_readl(con0_addr
); /* PLL_CON0 */
679 clk_writel(con0_addr
, (con0_value
& ~BITMASK(6 : 4)) | BITS(6 : 4, postdiv
)); /* bit[8:6] */
683 static unsigned int sdm_pll_get_pcw_op(struct pll
*pll
)
685 unsigned int con1_addr
= pll
->base_addr
+ 4;
686 unsigned int reg_value
;
688 reg_value
= clk_readl(con1_addr
); /* PLL_CON1 */
689 reg_value
&= SDM_PLL_N_INFO_MASK
; /* bit[20:0] */
695 static void sdm_pll_set_pcw_op(struct pll
*pll
, unsigned int pcw
)
697 unsigned int con1_addr
= pll
->base_addr
+ 4;
698 unsigned int reg_value
;
701 pll_en
= clk_readl(pll
->base_addr
) & BIT(0); /* PLL_CON0[0] */
703 reg_value
= clk_readl(con1_addr
);
704 reg_value
&= ~SDM_PLL_N_INFO_MASK
;
705 reg_value
|= pcw
& SDM_PLL_N_INFO_MASK
; /* PLL_CON1[20:0] = pcw */
708 reg_value
|= SDM_PLL_N_INFO_CHG
; /* PLL_CON1[31] = 1 */
710 clk_writel(con1_addr
, reg_value
);
717 static unsigned int calc_pll_vco_freq(
720 unsigned int vcodivsel
,
722 unsigned int pcw_f_bits
)
724 /* vco = (fin * pcw * vcodivsel / prediv) >> pcw_f_bits; */
726 vco
= vco
* pcw
* vcodivsel
;
730 return (unsigned int)vco
;
734 static unsigned int sdm_pll_vco_calc_op(struct pll
*pll
)
736 unsigned int con1
= clk_readl(pll
->base_addr
+ 4);
738 unsigned int vcodivsel
= 1;
739 unsigned int prediv
= 1;
740 unsigned int pcw
= con1
& BITMASK(20 : 0); /* bit[20:0] */
742 return calc_pll_vco_freq(26000, pcw
, vcodivsel
, prediv
, 14); /* 26M = 26000K Hz */
746 static int general_pll_calc_freq(unsigned int *pcw
, int *postdiv_idx
, unsigned int freq
, int pcwfbits
)
748 const uint64_t freq_max
= 2000 * 1000 * 1000; /* 2000 MHz */
749 const uint64_t freq_min
= 1000 * 1000 * 1000; /* 1000 MHz */
750 const uint32_t fin
= 26 * 1000 * 1000; /* 26 MHz */
751 static const uint64_t postdiv
[] = {1, 2, 4, 8, 16};
755 /* search suitable postdiv */
756 for (idx
= 0; idx
< ARRAY_SIZE(postdiv
) && postdiv
[idx
] * freq
<= freq_min
; idx
++)
759 if (idx
>= ARRAY_SIZE(postdiv
))
760 return -2; /* freq is out of range (too low) */
761 else if (postdiv
[idx
] * freq
> freq_max
)
762 return -3; /* freq is out of range (too high) */
764 n_info
= (postdiv
[idx
] * freq
) << pcwfbits
; /* n_info = freq * postdiv / 26MHz * 2^pcwfbits */
768 *pcw
= (unsigned int)n_info
;
774 static int general_pll_set_freq_op(struct pll
*pll
, unsigned int freq
, int pcwfbits
)
777 unsigned int pcw
= 0;
780 r
= general_pll_calc_freq(&pcw
, &postdiv_idx
, freq
, pcwfbits
);
783 pll
->ops
->set_postdiv(pll
, postdiv_idx
);
784 pll
->ops
->set_pcw(pll
, pcw
);
791 static int sdm_pll_set_freq_op(struct pll
*pll
, unsigned int freq
)
793 return general_pll_set_freq_op(pll
, freq
, 14);
797 static int sdm_pll_hp_enable_op(struct pll
*pll
)
800 unsigned int vco
= 0;
802 if (!pll
->hp_switch
|| (pll
->state
== PWR_DOWN
))
805 err
= freqhopping_config(pll
->hp_id
, vco
, 1);
810 static int sdm_pll_hp_disable_op(struct pll
*pll
)
813 unsigned int vco
= 0;
815 if (!pll
->hp_switch
|| (pll
->state
== PWR_ON
))
818 err
= freqhopping_config(pll
->hp_id
, vco
, 0);
823 static struct pll_ops sdm_pll_ops
= {
824 .get_state
= pll_get_state_op
,
825 .enable
= sdm_pll_enable_op
,
826 .disable
= sdm_pll_disable_op
,
827 .fsel
= sdm_pll_fsel_op
,
828 .dump_regs
= sdm_pll_dump_regs_op
,
829 .vco_calc
= sdm_pll_vco_calc_op
,
830 .hp_enable
= sdm_pll_hp_enable_op
,
831 .hp_disable
= sdm_pll_hp_disable_op
,
833 .get_postdiv
= sdm_pll_get_postdiv_op
,
834 .set_postdiv
= sdm_pll_set_postdiv_op
,
835 .get_pcw
= sdm_pll_get_pcw_op
,
836 .set_pcw
= sdm_pll_set_pcw_op
,
837 .set_freq
= sdm_pll_set_freq_op
,
838 #endif /* CLKMGR_8127 */
845 static unsigned int aud_pll_get_pcw_op(struct pll
*pll
)
847 unsigned int con1_addr
= pll
->base_addr
+ 4;
848 unsigned int reg_value
= clk_readl(con1_addr
); /* PLL_CON1; */
850 reg_value
&= BITMASK(30 : 0); /* bit[30:0] */
855 static void aud_pll_set_pcw_op(struct pll
*pll
, unsigned int pcw
)
857 unsigned int con1_addr
= pll
->base_addr
+ 4;
858 unsigned int con3_addr
= pll
->base_addr
+ 0x01B8;
859 unsigned int reg_value
;
862 pll_en
= clk_readl(pll
->base_addr
) & BIT(0);
863 reg_value
= clk_readl(con1_addr
); /* AUDPLL_CON1[30:0] (PLL_SDM_PCW) = pcw */
864 reg_value
= (reg_value
& ~BITMASK(30 : 0)) | BITS(30 : 0, pcw
);
866 if (pll_en
) /* AUDPLL_CON1[31] (AUDPLL_SDM_PCW_CHG) = 1 "and" */
867 reg_value
|= SDM_PLL_N_INFO_CHG
; /* AUDPLL_CON3[31] (AUDPLL_TUNER_EN) = 1 */
869 clk_writel(con3_addr
, reg_value
+ 1); /* AUDPLL_CON3[30:0] (AUDPLL_TUNER_N_INFO) = (pcw + 1) */
870 clk_writel(con1_addr
, reg_value
); /* AUDPLL_CON1 */
877 static unsigned int aud_pll_vco_calc_op(struct pll
*pll
)
879 unsigned int con1
= clk_readl(pll
->base_addr
+ 4);
881 unsigned int vcodivsel
= 1;
882 unsigned int prediv
= 1;
883 unsigned int pcw
= con1
& BITMASK(30 : 0); /* bit[30:0] */
885 return calc_pll_vco_freq(26000, pcw
, vcodivsel
, prediv
, 24); /* 26M = 26000K Hz */
889 static int aud_pll_set_freq_op(struct pll
*pll
, unsigned int freq
)
891 return general_pll_set_freq_op(pll
, freq
, 24);
895 static struct pll_ops aud_pll_ops
= {
896 .get_state
= pll_get_state_op
,
897 .enable
= sdm_pll_enable_op
,
898 .disable
= sdm_pll_disable_op
,
899 .fsel
= sdm_pll_fsel_op
,
900 .dump_regs
= sdm_pll_dump_regs_op
,
901 .vco_calc
= aud_pll_vco_calc_op
,
902 .hp_enable
= sdm_pll_hp_enable_op
,
903 .hp_disable
= sdm_pll_hp_disable_op
,
904 .get_postdiv
= sdm_pll_get_postdiv_op
,
905 .set_postdiv
= sdm_pll_set_postdiv_op
,
906 .get_pcw
= aud_pll_get_pcw_op
,
907 .set_pcw
= aud_pll_set_pcw_op
,
908 .set_freq
= aud_pll_set_freq_op
,
912 #endif /* CLKMGR_8127 */
915 static void arm_pll_fsel_op(struct pll
*pll
, unsigned int value
)
917 unsigned int ctrl_value
;
919 ctrl_value
= clk_readl(pll
->base_addr
+ 4);
920 ctrl_value
&= ~(SDM_PLL_N_INFO_MASK
| ARMPLL_POSDIV_MASK
);
921 ctrl_value
|= value
& (SDM_PLL_N_INFO_MASK
| ARMPLL_POSDIV_MASK
);
922 ctrl_value
|= SDM_PLL_N_INFO_CHG
;
924 clk_writel(pll
->base_addr
+ 4, ctrl_value
);
932 static unsigned int arm_pll_get_postdiv_op(struct pll
*pll
)
934 unsigned int con1
= clk_readl(pll
->base_addr
+ 4); /* PLL_CON1 */
935 unsigned int posdiv
= (con1
& BITMASK(26 : 24)) >> 24; /* bit[26:24] */
941 static void arm_pll_set_postdiv_op(struct pll
*pll
, unsigned int postdiv
)
943 unsigned con1_addr
= pll
->base_addr
+ 4;
944 unsigned int con1_value
= clk_readl(con1_addr
); /* PLL_CON1 */
946 clk_writel(con1_addr
, (con1_value
& ~BITMASK(26 : 24)) | BITS(26 : 24, postdiv
)); /* bit[26:24] */
950 static int arm_pll_set_freq_op(struct pll
*pll
, unsigned int freq
)
952 const int pcwfbits
= 14;
954 unsigned int pcw
= 0;
957 r
= general_pll_calc_freq(&pcw
, &postdiv_idx
, freq
, pcwfbits
);
960 unsigned int reg_val
= BITS(26 : 24, postdiv_idx
) | BITS(20 : 0, pcw
);
961 arm_pll_fsel_op(pll
, reg_val
);
968 #endif /* CLKMGR_8127 */
971 static struct pll_ops arm_pll_ops
= {
972 .get_state
= pll_get_state_op
,
973 .enable
= sdm_pll_enable_op
,
974 .disable
= sdm_pll_disable_op
,
975 .fsel
= arm_pll_fsel_op
,
976 .dump_regs
= sdm_pll_dump_regs_op
,
977 .vco_calc
= sdm_pll_vco_calc_op
,
978 .hp_enable
= sdm_pll_hp_enable_op
,
979 .hp_disable
= sdm_pll_hp_disable_op
,
981 .get_postdiv
= arm_pll_get_postdiv_op
,
982 .set_postdiv
= arm_pll_set_postdiv_op
,
983 .get_pcw
= sdm_pll_get_pcw_op
,
984 .set_pcw
= sdm_pll_set_pcw_op
,
985 .set_freq
= arm_pll_set_freq_op
,
986 #endif /* CLKMGR_8127 */
993 static unsigned int pll_freq_calc_op(struct pll
*pll
)
995 return pll
->ops
->vco_calc(pll
) / pll_posdiv_map
[pll
->ops
->get_postdiv(pll
)];
999 unsigned int pll_get_freq(int id
)
1002 unsigned long flags
;
1003 struct pll
*pll
= id_to_pll(id
);
1007 r
= pll_freq_calc_op(pll
);
1008 clkmgr_unlock(flags
);
1012 EXPORT_SYMBOL(pll_get_freq
);
1015 unsigned int pll_set_freq(int id
, unsigned int freq_khz
)
1018 unsigned long flags
;
1019 struct pll
*pll
= id_to_pll(id
);
1023 r
= pll
->ops
->set_freq(pll
, freq_khz
* 1000);
1024 clkmgr_unlock(flags
);
1028 EXPORT_SYMBOL(pll_set_freq
);
1031 #endif /* CLKMGR_8127 */
1034 static int get_pll_state_locked(struct pll
*pll
)
1036 if (likely(initialized
))
1039 return pll
->ops
->get_state(pll
);
1042 static int pll_enable_locked(struct pll
*pll
)
1045 clk_info("[%s]: Start. pll->name=%s, pll->cnt=%d, pll->state=%d\n", __func__
, pll
->name
, pll
->cnt
, pll
->state
);
1053 if (pll
->state
== PWR_DOWN
) {
1054 pll
->ops
->enable(pll
);
1055 pll
->state
= PWR_ON
;
1058 if (pll
->ops
->hp_enable
)
1059 pll
->ops
->hp_enable(pll
);
1062 clk_info("[%s]: End. pll->name=%s, pll->cnt=%d, pll->state=%d\n", __func__
, pll
->name
, pll
->cnt
, pll
->state
);
1067 static int pll_disable_locked(struct pll
*pll
)
1070 clk_info("[%s]: Start. pll->name=%s, pll->cnt=%d, pll->state=%d\n", __func__
, pll
->name
, pll
->cnt
, pll
->state
);
1073 #if DISABLE_BUG_ON_CNT
1077 #else /* !DISABLE_BUG_ON_CNT */
1079 #endif /* DISABLE_BUG_ON_CNT */
1086 if (pll
->state
== PWR_ON
) {
1087 pll
->ops
->disable(pll
);
1088 pll
->state
= PWR_DOWN
;
1091 if (pll
->ops
->hp_disable
)
1092 pll
->ops
->hp_disable(pll
);
1095 clk_info("[%s]: End. pll->name=%s, pll->cnt=%d, pll->state=%d\n", __func__
, pll
->name
, pll
->cnt
, pll
->state
);
1101 static int pll_fsel_locked(struct pll
*pll
, unsigned int value
)
1103 pll
->ops
->fsel(pll
, value
);
1104 if (pll
->ops
->hp_enable
)
1105 pll
->ops
->hp_enable(pll
);
1110 int pll_is_on(int id
)
1113 unsigned long flags
;
1114 struct pll
*pll
= id_to_pll(id
);
1116 #if defined(CONFIG_CLKMGR_BRINGUP)
1123 state
= get_pll_state_locked(pll
);
1124 clkmgr_unlock(flags
);
1128 EXPORT_SYMBOL(pll_is_on
);
1130 int enable_pll(int id
, char *name
)
1133 unsigned long flags
;
1134 struct pll
*pll
= id_to_pll(id
);
1136 #if defined(CONFIG_CLKMGR_BRINGUP)
1140 BUG_ON(!initialized
);
1144 clk_info("[%s]: id=%d, name=%s\n", __func__
, id
, name
);
1147 err
= pll_enable_internal(pll
, name
);
1148 clkmgr_unlock(flags
);
1152 EXPORT_SYMBOL(enable_pll
);
1154 int disable_pll(int id
, char *name
)
1157 unsigned long flags
;
1158 struct pll
*pll
= id_to_pll(id
);
1160 #if defined(CONFIG_CLKMGR_BRINGUP)
1164 BUG_ON(!initialized
);
1168 clk_info("[%s]: id=%d, name=%s\n", __func__
, id
, name
);
1171 err
= pll_disable_internal(pll
, name
);
1172 clkmgr_unlock(flags
);
1176 EXPORT_SYMBOL(disable_pll
);
1182 int enable_pll_spec(int id
, char *name
)
1185 unsigned long flags
;
1186 struct pll
*pll
= id_to_pll(id
);
1188 #if defined(CONFIG_CLKMGR_BRINGUP)
1192 BUG_ON(!initialized
);
1196 clk_info("[%s]: id=%d, name=%s\n", __func__
, id
, name
);
1199 err
= pll_enable_internal(pll
, name
);
1200 clkmgr_unlock(flags
);
1204 EXPORT_SYMBOL(enable_pll_spec
);
1206 int disable_pll_spec(int id
, char *name
)
1209 unsigned long flags
;
1210 struct pll
*pll
= id_to_pll(id
);
1212 #if defined(CONFIG_CLKMGR_BRINGUP)
1216 BUG_ON(!initialized
);
1220 clk_info("[%s]: id=%d, name=%s\n", __func__
, id
, name
);
1223 err
= pll_disable_internal(pll
, name
);
1224 clkmgr_unlock(flags
);
1228 EXPORT_SYMBOL(disable_pll_spec
);
1231 #endif /* !CLKMGR_8127 */
1234 int pll_fsel(int id
, unsigned int value
)
1237 unsigned long flags
;
1238 struct pll
*pll
= id_to_pll(id
);
1240 #if defined(CONFIG_CLKMGR_BRINGUP)
1244 BUG_ON(!initialized
);
1248 err
= pll_fsel_locked(pll
, value
);
1249 clkmgr_unlock(flags
);
1253 EXPORT_SYMBOL(pll_fsel
);
1256 int pll_hp_switch_on(int id
, int hp_on
)
1259 unsigned long flags
;
1261 struct pll
*pll
= id_to_pll(id
);
1263 #if defined(CONFIG_CLKMGR_BRINGUP)
1267 BUG_ON(!initialized
);
1270 if (pll
->type
!= PLL_TYPE_SDM
) {
1276 old_value
= pll
->hp_switch
;
1277 if (old_value
== 0) {
1280 err
= pll
->ops
->hp_enable(pll
);
1282 clkmgr_unlock(flags
);
1287 EXPORT_SYMBOL(pll_hp_switch_on
);
1289 int pll_hp_switch_off(int id
, int hp_off
)
1292 unsigned long flags
;
1294 struct pll
*pll
= id_to_pll(id
);
1296 #if defined(CONFIG_CLKMGR_BRINGUP)
1300 BUG_ON(!initialized
);
1303 if (pll
->type
!= PLL_TYPE_SDM
) {
1309 old_value
= pll
->hp_switch
;
1310 if (old_value
== 1) {
1312 err
= pll
->ops
->hp_disable(pll
);
1315 clkmgr_unlock(flags
);
1320 EXPORT_SYMBOL(pll_hp_switch_off
);
1323 int pll_dump_regs(int id
, unsigned int *ptr
)
1325 struct pll
*pll
= id_to_pll(id
);
1327 BUG_ON(!initialized
);
1330 return pll
->ops
->dump_regs(pll
, ptr
);
1332 EXPORT_SYMBOL(pll_dump_regs
);
1334 const char *pll_get_name(int id
)
1336 struct pll
*pll
= id_to_pll(id
);
1338 BUG_ON(!initialized
);
1348 void enable_clksq1(void)
1350 unsigned long flags
;
1355 clk_setl(AP_PLL_CON0
, 0x1 << 0);
1357 clk_setl(AP_PLL_CON0
, 0x1 << 1);
1358 clkmgr_unlock(flags
);
1360 EXPORT_SYMBOL(enable_clksq1
);
1362 void disable_clksq1(void)
1364 unsigned long flags
;
1369 clk_clrl(AP_PLL_CON0
, 0x3 << 0);
1370 clkmgr_unlock(flags
);
1372 EXPORT_SYMBOL(disable_clksq1
);
1374 void clksq1_sw2hw(void)
1376 unsigned long flags
;
1381 clk_clrl(AP_PLL_CON1
, 0x3 << 0);
1382 clkmgr_unlock(flags
);
1384 EXPORT_SYMBOL(clksq1_sw2hw
);
1386 void clksq1_hw2sw(void)
1388 unsigned long flags
;
1393 clk_setl(AP_PLL_CON1
, 0x3 << 0);
1394 clkmgr_unlock(flags
);
1396 EXPORT_SYMBOL(clksq1_hw2sw
);
1399 #endif /* !CLKMGR_8127 */
1403 /************************************************
1404 ********** subsys part **********
1405 ************************************************/
1407 #define SYS_TYPE_MODEM 0
1408 #define SYS_TYPE_MEDIA 1
1409 #define SYS_TYPE_OTHER 2
1410 #define SYS_TYPE_CONN 3
1412 static struct subsys_ops conn_sys_ops
;
1413 static struct subsys_ops dpy_sys_ops
;
1414 static struct subsys_ops dis_sys_ops
;
1415 static struct subsys_ops mfg_sys_ops
;
1416 static struct subsys_ops isp_sys_ops
;
1417 static struct subsys_ops ifr_sys_ops
;
1418 static struct subsys_ops vde_sys_ops
;
1420 static struct subsys syss
[NR_SYSS
] = {
1422 .name
= __stringify(SYS_CONN
),
1423 .type
= SYS_TYPE_CONN
,
1424 .default_sta
= PWR_DOWN
,
1425 .sta_mask
= 1U << 1,
1426 .ctl_addr
= SPM_CONN_PWR_CON
,
1427 .ops
= &conn_sys_ops
,
1430 .name
= __stringify(SYS_DPY
),
1431 .type
= SYS_TYPE_OTHER
,
1432 .default_sta
= PWR_ON
,
1433 .sta_mask
= 1U << 2,
1434 .ctl_addr
= SPM_DPY_PWR_CON
,
1435 .ops
= &dpy_sys_ops
,
1438 .name
= __stringify(SYS_DIS
),
1439 .type
= SYS_TYPE_MEDIA
,
1440 .default_sta
= PWR_ON
,
1441 .sta_mask
= 1U << 3,
1442 .ctl_addr
= SPM_DIS_PWR_CON
,
1443 .ops
= &dis_sys_ops
,
1444 .start
= &grps
[CG_DISP0
],
1446 .mux
= &muxs
[MT_MUX_MM
],
1449 .name
= __stringify(SYS_MFG
),
1450 .type
= SYS_TYPE_MEDIA
,
1451 .default_sta
= PWR_ON
,
1452 .sta_mask
= 1U << 4,
1453 .ctl_addr
= SPM_MFG_PWR_CON
,
1454 .ops
= &mfg_sys_ops
,
1455 .start
= &grps
[CG_MFG
],
1457 .mux
= &muxs
[MT_MUX_MFG
],
1460 .name
= __stringify(SYS_ISP
),
1461 .type
= SYS_TYPE_MEDIA
,
1462 .default_sta
= PWR_ON
,
1463 .sta_mask
= 1U << 5,
1464 .ctl_addr
= SPM_ISP_PWR_CON
,
1465 .ops
= &isp_sys_ops
,
1466 .start
= &grps
[CG_IMAGE
],
1470 .name
= __stringify(SYS_IFR
),
1471 .type
= SYS_TYPE_OTHER
,
1472 .default_sta
= PWR_ON
,
1473 .sta_mask
= 1U << 6,
1474 .ctl_addr
= SPM_IFR_PWR_CON
,
1475 .ops
= &ifr_sys_ops
,
1478 .name
= __stringify(SYS_VDE
),
1479 .type
= SYS_TYPE_MEDIA
,
1480 .default_sta
= PWR_ON
,
1481 .sta_mask
= 1U << 7,
1482 .ctl_addr
= SPM_VDE_PWR_CON
,
1483 .ops
= &vde_sys_ops
,
1484 .start
= &grps
[CG_VDEC0
],
1486 .mux
= &muxs
[MT_MUX_VDEC
],
1491 static void larb_backup(int larb_idx
);
1492 static void larb_restore(int larb_idx
);
1495 static struct subsys
*id_to_sys(unsigned int id
)
1497 return id
< NR_SYSS
? syss
+ id
: NULL
;
1500 static int conn_sys_enable_op(struct subsys
*sys
)
1503 err
= spm_mtcmos_ctrl_connsys(STA_POWER_ON
);
1507 static int conn_sys_disable_op(struct subsys
*sys
)
1510 err
= spm_mtcmos_ctrl_connsys(STA_POWER_DOWN
);
1514 static int dpy_sys_enable_op(struct subsys
*sys
)
1517 err
= spm_mtcmos_ctrl_ddrphy(STA_POWER_ON
);
1521 static int dpy_sys_disable_op(struct subsys
*sys
)
1524 err
= spm_mtcmos_ctrl_ddrphy(STA_POWER_DOWN
);
1528 static int dis_sys_enable_op(struct subsys
*sys
)
1532 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1535 err
= spm_mtcmos_ctrl_disp(STA_POWER_ON
);
1536 larb_restore(MT_LARB_DISP
);
1540 static int dis_sys_disable_op(struct subsys
*sys
)
1544 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1547 larb_backup(MT_LARB_DISP
);
1548 err
= spm_mtcmos_ctrl_disp(STA_POWER_DOWN
);
1552 static int mfg_sys_enable_op(struct subsys
*sys
)
1556 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1559 err
= spm_mtcmos_ctrl_mfg(STA_POWER_ON
);
1564 static int mfg_sys_disable_op(struct subsys
*sys
)
1568 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1571 err
= spm_mtcmos_ctrl_mfg(STA_POWER_DOWN
);
1576 static int isp_sys_enable_op(struct subsys
*sys
)
1580 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1582 err
= spm_mtcmos_ctrl_isp(STA_POWER_ON
);
1583 larb_restore(MT_LARB_IMG
);
1587 static int isp_sys_disable_op(struct subsys
*sys
)
1591 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1593 larb_backup(MT_LARB_IMG
);
1594 err
= spm_mtcmos_ctrl_isp(STA_POWER_DOWN
);
1598 static int ifr_sys_enable_op(struct subsys
*sys
)
1602 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1604 err
= spm_mtcmos_ctrl_infra(STA_POWER_ON
);
1608 static int ifr_sys_disable_op(struct subsys
*sys
)
1612 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1614 err
= spm_mtcmos_ctrl_infra(STA_POWER_DOWN
);
1618 static int vde_sys_enable_op(struct subsys
*sys
)
1622 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1624 err
= spm_mtcmos_ctrl_vdec(STA_POWER_ON
);
1625 larb_restore(MT_LARB_VDEC
);
1629 static int vde_sys_disable_op(struct subsys
*sys
)
1633 clk_info("[%s]: sys->name=%s\n", __func__
, sys
->name
);
1635 larb_backup(MT_LARB_VDEC
);
1636 err
= spm_mtcmos_ctrl_vdec(STA_POWER_DOWN
);
1640 static int sys_get_state_op(struct subsys
*sys
)
1642 unsigned int sta
= clk_readl(SPM_PWR_STATUS
);
1643 unsigned int sta_s
= clk_readl(SPM_PWR_STATUS_S
);
1645 return (sta
& sys
->sta_mask
) && (sta_s
& sys
->sta_mask
);
1648 static int sys_dump_regs_op(struct subsys
*sys
, unsigned int *ptr
)
1650 *(ptr
) = clk_readl(sys
->ctl_addr
);
1654 static struct subsys_ops conn_sys_ops
= {
1655 .enable
= conn_sys_enable_op
,
1656 .disable
= conn_sys_disable_op
,
1657 .get_state
= sys_get_state_op
,
1658 .dump_regs
= sys_dump_regs_op
,
1661 static struct subsys_ops dpy_sys_ops
= {
1662 .enable
= dpy_sys_enable_op
,
1663 .disable
= dpy_sys_disable_op
,
1664 .get_state
= sys_get_state_op
,
1665 .dump_regs
= sys_dump_regs_op
,
1668 static struct subsys_ops dis_sys_ops
= {
1669 .enable
= dis_sys_enable_op
,
1670 .disable
= dis_sys_disable_op
,
1671 .get_state
= sys_get_state_op
,
1672 .dump_regs
= sys_dump_regs_op
,
1675 static struct subsys_ops mfg_sys_ops
= {
1676 .enable
= mfg_sys_enable_op
,
1677 .disable
= mfg_sys_disable_op
,
1678 .get_state
= sys_get_state_op
,
1679 .dump_regs
= sys_dump_regs_op
,
1682 static struct subsys_ops isp_sys_ops
= {
1683 .enable
= isp_sys_enable_op
,
1684 .disable
= isp_sys_disable_op
,
1685 .get_state
= sys_get_state_op
,
1686 .dump_regs
= sys_dump_regs_op
,
1689 static struct subsys_ops ifr_sys_ops
= {
1690 .enable
= ifr_sys_enable_op
,
1691 .disable
= ifr_sys_disable_op
,
1692 .get_state
= sys_get_state_op
,
1693 .dump_regs
= sys_dump_regs_op
,
1696 static struct subsys_ops vde_sys_ops
= {
1697 .enable
= vde_sys_enable_op
,
1698 .disable
= vde_sys_disable_op
,
1699 .get_state
= sys_get_state_op
,
1700 .dump_regs
= sys_dump_regs_op
,
1706 static int get_sys_state_locked(struct subsys
*sys
)
1708 if (likely(initialized
))
1711 return sys
->ops
->get_state(sys
);
1714 int subsys_is_on(int id
)
1717 unsigned long flags
;
1718 struct subsys
*sys
= id_to_sys(id
);
1720 #if defined(CONFIG_CLKMGR_BRINGUP)
1727 state
= get_sys_state_locked(sys
);
1728 clkmgr_unlock(flags
);
1732 EXPORT_SYMBOL(subsys_is_on
);
1734 /* #define STATE_CHECK_DEBUG */
1736 static int sys_enable_locked(struct subsys
*sys
)
1739 int local_state
= sys
->state
; /* get_subsys_local_state(sys); */
1741 #ifdef STATE_CHECK_DEBUG
1742 int reg_state
= sys
->ops
->get_state(sys
); /* get_subsys_reg_state(sys); */
1743 BUG_ON(local_state
!= reg_state
);
1747 clk_info("[%s]: Start. sys->name=%s, sys->state=%d\n", __func__
, sys
->name
, sys
->state
);
1750 if (local_state
== PWR_ON
)
1754 mux_enable_internal(sys
->mux
, "sys");
1756 err
= sys
->ops
->enable(sys
);
1760 sys
->state
= PWR_ON
;
1763 clk_info("[%s]: End. sys->name=%s, sys->state=%d\n", __func__
, sys
->name
, sys
->state
);
1768 static int sys_disable_locked(struct subsys
*sys
, int force_off
)
1771 int local_state
= sys
->state
; /* get_subsys_local_state(sys); */
1775 #ifdef STATE_CHECK_DEBUG
1776 int reg_state
= sys
->ops
->get_state(sys
); /* get_subsys_reg_state(sys); */
1777 BUG_ON(local_state
!= reg_state
);
1781 clk_info("[%s]: Start. sys->name=%s, sys->state=%d, force_off=%d\n",
1782 __func__
, sys
->name
, sys
->state
, force_off
);
1785 /* could be power off or not */
1786 for (i
= 0; i
< sys
->nr_grps
; i
++) {
1787 grp
= sys
->start
+ i
;
1793 if (local_state
== PWR_DOWN
)
1796 err
= sys
->ops
->disable(sys
);
1800 sys
->state
= PWR_DOWN
;
1803 mux_disable_internal(sys
->mux
, "sys");
1806 clk_info("[%s]: End. sys->name=%s, sys->state=%d, force_off=%d\n",
1807 __func__
, sys
->name
, sys
->state
, force_off
);
1812 int enable_subsys(int id
, char *name
)
1815 unsigned long flags
;
1816 struct subsys
*sys
= id_to_sys(id
);
1818 #if defined(CONFIG_CLKMGR_BRINGUP)
1822 BUG_ON(!initialized
);
1826 err
= subsys_enable_internal(sys
, name
);
1827 clkmgr_unlock(flags
);
1831 EXPORT_SYMBOL(enable_subsys
);
1833 int disable_subsys(int id
, char *name
)
1836 unsigned long flags
;
1837 struct subsys
*sys
= id_to_sys(id
);
1839 #if defined(CONFIG_CLKMGR_BRINGUP)
1843 BUG_ON(!initialized
);
1847 err
= subsys_disable_internal(sys
, 0, name
);
1848 clkmgr_unlock(flags
);
1852 EXPORT_SYMBOL(disable_subsys
);
1854 int disable_subsys_force(int id
, char *name
)
1857 unsigned long flags
;
1858 struct subsys
*sys
= id_to_sys(id
);
1860 BUG_ON(!initialized
);
1864 err
= subsys_disable_internal(sys
, 1, name
);
1865 clkmgr_unlock(flags
);
1870 int subsys_dump_regs(int id
, unsigned int *ptr
)
1872 struct subsys
*sys
= id_to_sys(id
);
1874 #if defined(CONFIG_CLKMGR_BRINGUP)
1878 BUG_ON(!initialized
);
1881 return sys
->ops
->dump_regs(sys
, ptr
);
1883 EXPORT_SYMBOL(subsys_dump_regs
);
1885 const char *subsys_get_name(int id
)
1887 struct subsys
*sys
= id_to_sys(id
);
1889 BUG_ON(!initialized
);
1895 #define JIFFIES_PER_LOOP 10
1901 int md_power_on(int id
)
1905 EXPORT_SYMBOL(md_power_on
);
1907 int md_power_off(int id
, unsigned int timeout
)
1911 EXPORT_SYMBOL(md_power_off
);
1914 #endif /* !CLKMGR_8127 */
1917 int conn_power_on(void)
1920 unsigned long flags
;
1921 struct subsys
*sys
= id_to_sys(SYS_CONN
);
1923 BUG_ON(!initialized
);
1925 BUG_ON(sys
->type
!= SYS_TYPE_CONN
);
1928 err
= subsys_enable_internal(sys
, "conn");
1929 clkmgr_unlock(flags
);
1935 EXPORT_SYMBOL(conn_power_on
);
1937 int conn_power_off(void)
1940 unsigned long flags
;
1941 struct subsys
*sys
= id_to_sys(SYS_CONN
);
1943 BUG_ON(!initialized
);
1945 BUG_ON(sys
->type
!= SYS_TYPE_CONN
);
1948 err
= subsys_disable_internal(sys
, 0, "conn");
1949 clkmgr_unlock(flags
);
1955 EXPORT_SYMBOL(conn_power_off
);
1958 static DEFINE_MUTEX(larb_monitor_lock
);
1959 static LIST_HEAD(larb_monitor_handlers
);
1961 void register_larb_monitor(struct larb_monitor
*handler
)
1963 struct list_head
*pos
;
1965 #if defined(CONFIG_CLKMGR_BRINGUP)
1969 mutex_lock(&larb_monitor_lock
);
1970 list_for_each(pos
, &larb_monitor_handlers
) {
1971 struct larb_monitor
*l
;
1972 l
= list_entry(pos
, struct larb_monitor
, link
);
1973 if (l
->level
> handler
->level
)
1976 list_add_tail(&handler
->link
, pos
);
1977 mutex_unlock(&larb_monitor_lock
);
1979 EXPORT_SYMBOL(register_larb_monitor
);
1982 void unregister_larb_monitor(struct larb_monitor
*handler
)
1984 #if defined(CONFIG_CLKMGR_BRINGUP)
1988 mutex_lock(&larb_monitor_lock
);
1989 list_del(&handler
->link
);
1990 mutex_unlock(&larb_monitor_lock
);
1992 EXPORT_SYMBOL(unregister_larb_monitor
);
1994 static void larb_clk_prepare(int larb_idx
)
1999 clk_writel(DISP_CG_CLR0
, 0x3);
2003 clk_writel(LARB_CKEN_SET
, 0x1);
2007 clk_writel(IMG_CG_CLR
, 0x1);
2014 static void larb_clk_finish(int larb_idx
)
2019 clk_writel(DISP_CG_SET0
, 0x3);
2023 clk_writel(LARB_CKEN_CLR
, 0x1);
2027 clk_writel(IMG_CG_SET
, 0x1);
2034 static void larb_backup(int larb_idx
)
2036 struct larb_monitor
*pos
;
2038 clk_dbg("[%s]: start to backup larb%d\n", __func__
, larb_idx
);
2040 larb_clk_prepare(larb_idx
);
2042 list_for_each_entry(pos
, &larb_monitor_handlers
, link
) {
2043 if (pos
->backup
!= NULL
)
2044 pos
->backup(pos
, larb_idx
);
2047 larb_clk_finish(larb_idx
);
2050 static void larb_restore(int larb_idx
)
2052 struct larb_monitor
*pos
;
2054 clk_dbg("[%s]: start to restore larb%d\n", __func__
, larb_idx
);
2056 larb_clk_prepare(larb_idx
);
2058 list_for_each_entry(pos
, &larb_monitor_handlers
, link
) {
2059 if (pos
->restore
!= NULL
)
2060 pos
->restore(pos
, larb_idx
);
2063 larb_clk_finish(larb_idx
);
2068 /************************************************
2069 ********** clkmux part **********
2070 ************************************************/
2072 static struct clkmux_ops clkmux_ops
;
2073 static struct clkmux_ops dpi0_clkmux_ops
;
2075 static struct clkmux muxs
[NR_MUXS
] = {
2077 .name
= __stringify(MT_MUX_MM
),
2078 .base_addr
= CLK_CFG_0
,
2079 .sel_mask
= 0x07000000,
2080 .pdn_mask
= 0x80000000,
2084 .pll
= &plls
[VENCPLL
],
2086 [MT_MUX_DDRPHYCFG
] = {
2087 .name
= __stringify(MT_MUX_DDRPHYCFG
),
2088 .base_addr
= CLK_CFG_0
,
2089 .sel_mask
= 0x00010000,
2090 .pdn_mask
= 0x00800000,
2096 .name
= __stringify(MT_MUX_MEM
),
2097 .base_addr
= CLK_CFG_0
,
2098 .sel_mask
= 0x00000100,
2099 .pdn_mask
= 0x00008000,
2105 .name
= __stringify(MT_MUX_AXI
),
2106 .base_addr
= CLK_CFG_0
,
2107 .sel_mask
= 0x00000007,
2108 .pdn_mask
= 0x00000080,
2114 .name
= __stringify(MT_MUX_CAMTG
),
2115 .base_addr
= CLK_CFG_1
,
2116 .sel_mask
= 0x07000000,
2117 .pdn_mask
= 0x80000000,
2121 .pll
= &plls
[UNIVPLL
],
2124 .name
= __stringify(MT_MUX_MFG
),
2125 .base_addr
= CLK_CFG_1
,
2126 .sel_mask
= 0x00070000,
2127 .pdn_mask
= 0x00800000,
2131 .pll
= &plls
[MMPLL
],
2134 .name
= __stringify(MT_MUX_VDEC
),
2135 .base_addr
= CLK_CFG_1
,
2136 .sel_mask
= 0x00000F00,
2137 .pdn_mask
= 0x00008000,
2143 .name
= __stringify(MT_MUX_PWM
),
2144 .base_addr
= CLK_CFG_1
,
2145 .sel_mask
= 0x00000003,
2146 .pdn_mask
= 0x00000080,
2150 .pll
= &plls
[UNIVPLL
],
2152 [MT_MUX_MSDC30_0
] = {
2153 .name
= __stringify(MT_MUX_MSDC30_0
),
2154 .base_addr
= CLK_CFG_2
,
2155 .sel_mask
= 0x07000000,
2156 .pdn_mask
= 0x80000000,
2160 .pll
= &plls
[MSDCPLL
],
2163 .name
= __stringify(MT_MUX_USB20
),
2164 .base_addr
= CLK_CFG_2
,
2165 .sel_mask
= 0x00030000,
2166 .pdn_mask
= 0x00800000,
2170 .pll
= &plls
[UNIVPLL
],
2173 .name
= __stringify(MT_MUX_SPI
),
2174 .base_addr
= CLK_CFG_2
,
2175 .sel_mask
= 0x00000700,
2176 .pdn_mask
= 0x00008000,
2182 .name
= __stringify(MT_MUX_UART
),
2183 .base_addr
= CLK_CFG_2
,
2184 .sel_mask
= 0x00000001,
2185 .pdn_mask
= 0x00000080,
2190 [MT_MUX_AUDINTBUS
] = {
2191 .name
= __stringify(MT_MUX_AUDINTBUS
),
2192 .base_addr
= CLK_CFG_3
,
2193 .sel_mask
= 0x07000000,
2194 .pdn_mask
= 0x80000000,
2198 .siblings
= &muxs
[MT_MUX_AUDIO
],
2201 .name
= __stringify(MT_MUX_AUDIO
),
2202 .base_addr
= CLK_CFG_3
,
2203 .sel_mask
= 0x00010000,
2204 .pdn_mask
= 0x00800000,
2209 [MT_MUX_MSDC30_2
] = {
2210 .name
= __stringify(MT_MUX_MSDC30_2
),
2211 .base_addr
= CLK_CFG_3
,
2212 .sel_mask
= 0x00000700,
2213 .pdn_mask
= 0x00008000,
2217 .pll
= &plls
[MSDCPLL
],
2219 [MT_MUX_MSDC30_1
] = {
2220 .name
= __stringify(MT_MUX_MSDC30_1
),
2221 .base_addr
= CLK_CFG_3
,
2222 .sel_mask
= 0x00000007,
2223 .pdn_mask
= 0x00000080,
2227 .pll
= &plls
[MSDCPLL
],
2230 .name
= __stringify(MT_MUX_DPI1
),
2231 .base_addr
= CLK_CFG_4
,
2232 .sel_mask
= 0x03000000,
2233 .pdn_mask
= 0x80000000,
2237 .pll
= &plls
[TVDPLL
],
2240 .name
= __stringify(MT_MUX_DPI0
),
2241 .base_addr
= CLK_CFG_4
,
2242 .sel_mask
= 0x00070000,
2243 .pdn_mask
= 0x00800000,
2246 .ops
= &dpi0_clkmux_ops
,
2247 .pll
= &plls
[LVDSPLL
],
2250 .name
= __stringify(MT_MUX_SCP
),
2251 .base_addr
= CLK_CFG_4
,
2252 .sel_mask
= 0x00000300,
2253 .pdn_mask
= 0x00008000,
2258 [MT_MUX_PMICSPI
] = {
2259 .name
= __stringify(MT_MUX_PMICSPI
),
2260 .base_addr
= CLK_CFG_4
,
2261 .sel_mask
= 0x0000000F,
2262 .pdn_mask
= 0x00000080,
2267 [MT_MUX_DPILVDS
] = {
2268 .name
= __stringify(MT_MUX_DPILVDS
),
2269 .base_addr
= CLK_CFG_5
,
2270 .sel_mask
= 0x07000000,
2271 .pdn_mask
= 0x80000000,
2275 .pll
= &plls
[LVDSPLL
],
2278 .name
= __stringify(MT_MUX_APLL
),
2279 .base_addr
= CLK_CFG_5
,
2280 .sel_mask
= 0x00070000,
2281 .pdn_mask
= 0x00800000,
2285 .pll
= &plls
[AUDPLL
],
2288 .name
= __stringify(MT_MUX_HDMI
),
2289 .base_addr
= CLK_CFG_5
,
2290 .sel_mask
= 0x00000300,
2291 .pdn_mask
= 0x00008000,
2297 .name
= __stringify(MT_MUX_TVE
),
2298 .base_addr
= CLK_CFG_5
,
2299 .sel_mask
= 0x00000007,
2300 .pdn_mask
= 0x00000080,
2304 .pll
= &plls
[TVDPLL
],
2306 [MT_MUX_ETH_50M
] = {
2307 .name
= __stringify(MT_MUX_ETH_50M
),
2308 .base_addr
= CLK_CFG_6
,
2309 .sel_mask
= 0x00070000,
2310 .pdn_mask
= 0x00800000,
2314 .pll
= &plls
[LVDSPLL
],
2317 .name
= __stringify(MT_MUX_NFI2X
),
2318 .base_addr
= CLK_CFG_6
,
2319 .sel_mask
= 0x00000700,
2320 .pdn_mask
= 0x00008000,
2326 .name
= __stringify(MT_MUX_RTC
),
2327 .base_addr
= CLK_CFG_6
,
2328 .sel_mask
= 0x00000003,
2329 .pdn_mask
= 0x00000080,
2337 static struct clkmux
*id_to_mux(unsigned int id
)
2339 return id
< NR_MUXS
? muxs
+ id
: NULL
;
2342 static void clkmux_sel_op(struct clkmux
*mux
, unsigned clksrc
)
2347 clk_dbg("[%s]: mux->name=%s, clksrc=%d\n", __func__
, mux
->name
, clksrc
);
2350 reg
= clk_readl(mux
->base_addr
);
2352 reg
&= ~(mux
->sel_mask
);
2353 reg
|= (clksrc
<< mux
->offset
) & mux
->sel_mask
;
2355 clk_writel(mux
->base_addr
, reg
);
2358 static void clkmux_enable_op(struct clkmux
*mux
)
2361 clk_dbg("[%s]: mux->name=%s\n", __func__
, mux
->name
);
2364 clk_clrl(mux
->base_addr
, mux
->pdn_mask
);
2367 static void clkmux_disable_op(struct clkmux
*mux
)
2370 clk_dbg("[%s]: mux->name=%s\n", __func__
, mux
->name
);
2373 clk_setl(mux
->base_addr
, mux
->pdn_mask
);
2376 static struct clkmux_ops clkmux_ops
= {
2377 .sel
= clkmux_sel_op
,
2378 .enable
= clkmux_enable_op
,
2379 .disable
= clkmux_disable_op
,
2383 static void dpi0_clkmux_sel_op(struct clkmux
*mux
, unsigned clksrc
)
2388 clk_dbg("[%s]: mux->name=%s, clksrc=%d\n", __func__
, mux
->name
, clksrc
);
2391 reg
= clk_readl(mux
->base_addr
);
2393 #if WORKAROUND_DPI0_MUX
2396 unsigned int old_setting
= (reg
& mux
->sel_mask
) >> mux
->offset
;
2397 unsigned int lsb_mask
= 0x3; /* lowest 2 bits */
2399 if ((old_setting
!= clksrc
) && ((old_setting
^ clksrc
) & lsb_mask
) == 0) {
2400 /* if lowest 2 bits are the same, then change mux to a temp setting */
2401 unsigned int temp_setting
[] = {5, 4, 5, 6};
2402 reg
&= ~(mux
->sel_mask
);
2403 reg
|= (temp_setting
[clksrc
& lsb_mask
] << mux
->offset
) & mux
->sel_mask
;
2404 clk_writel(mux
->base_addr
, reg
);
2406 reg
= clk_readl(mux
->base_addr
);
2410 #endif /* WORKAROUND_DPI0_MUX */
2412 reg
&= ~(mux
->sel_mask
);
2413 reg
|= (clksrc
<< mux
->offset
) & mux
->sel_mask
;
2414 clk_writel(mux
->base_addr
, reg
);
2418 static struct clkmux_ops dpi0_clkmux_ops
= {
2419 .sel
= dpi0_clkmux_sel_op
,
2420 .enable
= clkmux_enable_op
,
2421 .disable
= clkmux_disable_op
,
2424 static void clkmux_sel_locked(struct clkmux
*mux
, unsigned int clksrc
)
2426 mux
->ops
->sel(mux
, clksrc
);
2429 static void mux_enable_locked(struct clkmux
*mux
)
2432 clk_info("[%s]: Start. mux->name=%s, mux->cnt=%d\n", __func__
, mux
->name
, mux
->cnt
);
2441 pll_enable_internal(mux
->pll
, "mux");
2443 mux
->ops
->enable(mux
);
2446 mux_enable_internal(mux
->siblings
, "mux_s");
2449 clk_info("[%s]: End. mux->name=%s, mux->cnt=%d\n", __func__
, mux
->name
, mux
->cnt
);
2453 static void mux_disable_locked(struct clkmux
*mux
)
2456 clk_info("[%s]: Start. mux->name=%s, mux->cnt=%d\n", __func__
, mux
->name
, mux
->cnt
);
2459 #if DISABLE_BUG_ON_CNT
2463 #else /* !DISABLE_BUG_ON_CNT */
2465 #endif /* DISABLE_BUG_ON_CNT */
2472 mux
->ops
->disable(mux
);
2475 mux_disable_internal(mux
->siblings
, "mux_s");
2478 pll_disable_internal(mux
->pll
, "mux");
2481 clk_info("[%s]: End. mux->name=%s, mux->cnt=%d\n", __func__
, mux
->name
, mux
->cnt
);
2485 int clkmux_sel(int id
, unsigned int clksrc
, char *name
)
2487 unsigned long flags
;
2488 struct clkmux
*mux
= id_to_mux(id
);
2490 #if defined(CONFIG_CLKMGR_BRINGUP)
2494 BUG_ON(!initialized
);
2496 BUG_ON(clksrc
>= mux
->nr_inputs
);
2499 clkmux_sel_locked(mux
, clksrc
);
2500 clkmgr_unlock(flags
);
2504 EXPORT_SYMBOL(clkmux_sel
);
2506 void enable_mux(int id
, char *name
)
2508 unsigned long flags
;
2509 struct clkmux
*mux
= id_to_mux(id
);
2511 #if defined(CONFIG_CLKMGR_BRINGUP) || defined(CONFIG_MT8127_FPGA)
2515 BUG_ON(!initialized
);
2519 clk_info("[%s]: id=%d, name=%s\n", __func__
, id
, name
);
2522 mux_enable_internal(mux
, name
);
2523 clkmgr_unlock(flags
);
2527 EXPORT_SYMBOL(enable_mux
);
2529 void disable_mux(int id
, char *name
)
2531 unsigned long flags
;
2532 struct clkmux
*mux
= id_to_mux(id
);
2534 #if defined(CONFIG_CLKMGR_BRINGUP) || defined(CONFIG_MT8127_FPGA)
2538 BUG_ON(!initialized
);
2542 clk_info("[%s]: id=%d, name=%s\n", __func__
, id
, name
);
2545 mux_disable_internal(mux
, name
);
2546 clkmgr_unlock(flags
);
2550 EXPORT_SYMBOL(disable_mux
);
2553 /************************************************
2554 ********** cg_grp part **********
2555 ************************************************/
2557 static struct cg_grp_ops general_cg_grp_ops
;
2558 static struct cg_grp_ops vdec_cg_grp_ops
;
2561 static struct cg_grp grps
[NR_GRPS
] = {
2563 .name
= __stringify(CG_PERI0
),
2564 .set_addr
= PERI_PDN0_SET
,
2565 .clr_addr
= PERI_PDN0_CLR
,
2566 .sta_addr
= PERI_PDN0_STA
,
2567 .ops
= &general_cg_grp_ops
,
2570 .name
= __stringify(CG_PERI1
),
2571 .set_addr
= PERI_PDN1_SET
,
2572 .clr_addr
= PERI_PDN1_CLR
,
2573 .sta_addr
= PERI_PDN1_STA
,
2574 .ops
= &general_cg_grp_ops
,
2577 .name
= __stringify(CG_INFRA
),
2578 .set_addr
= INFRA_PDN_SET
,
2579 .clr_addr
= INFRA_PDN_CLR
,
2580 .sta_addr
= INFRA_PDN_STA
,
2581 .ops
= &general_cg_grp_ops
,
2584 .name
= __stringify(CG_TOPCK
),
2585 .set_addr
= CLK_CFG_4_SET
,
2586 .clr_addr
= CLK_CFG_4_CLR
,
2587 .sta_addr
= CLK_CFG_4
,
2588 .ops
= &general_cg_grp_ops
,
2591 .name
= __stringify(CG_DISP0
),
2592 .set_addr
= DISP_CG_SET0
,
2593 .clr_addr
= DISP_CG_CLR0
,
2594 .sta_addr
= DISP_CG_CON0
,
2595 .ops
= &general_cg_grp_ops
,
2596 .sys
= &syss
[SYS_DIS
],
2599 .name
= __stringify(CG_DISP1
),
2600 .set_addr
= DISP_CG_SET1
,
2601 .clr_addr
= DISP_CG_CLR1
,
2602 .sta_addr
= DISP_CG_CON1
,
2603 .ops
= &general_cg_grp_ops
,
2604 .sys
= &syss
[SYS_DIS
],
2607 .name
= __stringify(CG_IMAGE
),
2608 .set_addr
= IMG_CG_SET
,
2609 .clr_addr
= IMG_CG_CLR
,
2610 .sta_addr
= IMG_CG_CON
,
2611 .ops
= &general_cg_grp_ops
,
2612 .sys
= &syss
[SYS_ISP
],
2615 .name
= __stringify(CG_MFG
),
2616 .set_addr
= MFG_CG_SET
,
2617 .clr_addr
= MFG_CG_CLR
,
2618 .sta_addr
= MFG_CG_CON
,
2619 .ops
= &general_cg_grp_ops
,
2620 .sys
= &syss
[SYS_MFG
],
2623 .name
= __stringify(CG_AUDIO
),
2624 .sta_addr
= AUDIO_TOP_CON0
,
2625 .ops
= &general_cg_grp_ops
,
2628 .name
= __stringify(CG_VDEC0
),
2629 .set_addr
= VDEC_CKEN_CLR
, /* revert CLR and SET here to reuse general_cg_grp_ops */
2630 .clr_addr
= VDEC_CKEN_SET
,
2631 .ops
= &vdec_cg_grp_ops
,
2632 .sys
= &syss
[SYS_VDE
],
2635 .name
= __stringify(CG_VDEC1
),
2636 .set_addr
= LARB_CKEN_CLR
, /* revert CLR and SET here to reuse general_cg_grp_ops */
2637 .clr_addr
= LARB_CKEN_SET
,
2638 .ops
= &vdec_cg_grp_ops
,
2639 .sys
= &syss
[SYS_VDE
],
2643 static struct cg_grp
*id_to_grp(unsigned int id
)
2645 return id
< NR_GRPS
? grps
+ id
: NULL
;
2648 static unsigned int general_grp_get_state_op(struct cg_grp
*grp
)
2651 struct subsys
*sys
= grp
->sys
;
2653 if (sys
&& !sys
->state
)
2656 val
= clk_readl(grp
->sta_addr
);
2657 val
= (~val
) & (grp
->mask
);
2661 static int general_grp_dump_regs_op(struct cg_grp
*grp
, unsigned int *ptr
)
2663 *(ptr
) = clk_readl(grp
->sta_addr
);
2668 static struct cg_grp_ops general_cg_grp_ops
= {
2669 .get_state
= general_grp_get_state_op
,
2670 .dump_regs
= general_grp_dump_regs_op
,
2673 static unsigned int vdec_grp_get_state_op(struct cg_grp
*grp
)
2675 unsigned int val
= clk_readl(grp
->set_addr
);
2680 static int vdec_grp_dump_regs_op(struct cg_grp
*grp
, unsigned int *ptr
)
2682 *(ptr
) = clk_readl(grp
->set_addr
);
2683 *(++ptr
) = clk_readl(grp
->clr_addr
);
2688 static struct cg_grp_ops vdec_cg_grp_ops
= {
2689 .get_state
= vdec_grp_get_state_op
,
2690 .dump_regs
= vdec_grp_dump_regs_op
,
2695 /************************************************
2696 ********** cg_clk part **********
2697 ************************************************/
2699 static struct cg_clk_ops general_cg_clk_ops
;
2700 static struct cg_clk_ops audio_cg_clk_ops
;
2701 static struct cg_clk_ops audsys_cg_clk_ops
; /* @audio sys */
2702 static struct cg_clk_ops vdec_cg_clk_ops
;
2705 static struct cg_clk clks
[NR_CLKS
] = {
2706 [MT_CG_PERI_NFI
] = {
2707 .name
= "MT_CG_PERI_NFI",
2708 .grp
= &grps
[CG_PERI0
],
2710 .ops
= &general_cg_clk_ops
,
2711 .mux
= &muxs
[MT_MUX_NFI2X
],
2713 [MT_CG_PERI_THERM
] = {
2714 .name
= "MT_CG_PERI_THERM",
2715 .grp
= &grps
[CG_PERI0
],
2717 .ops
= &general_cg_clk_ops
,
2719 [MT_CG_PERI_PWM1
] = {
2720 .name
= "MT_CG_PERI_PWM1",
2721 .grp
= &grps
[CG_PERI0
],
2723 .ops
= &general_cg_clk_ops
,
2725 [MT_CG_PERI_PWM2
] = {
2726 .name
= "MT_CG_PERI_PWM2",
2727 .grp
= &grps
[CG_PERI0
],
2729 .ops
= &general_cg_clk_ops
,
2731 [MT_CG_PERI_PWM3
] = {
2732 .name
= "MT_CG_PERI_PWM3",
2733 .grp
= &grps
[CG_PERI0
],
2735 .ops
= &general_cg_clk_ops
,
2737 [MT_CG_PERI_PWM4
] = {
2738 .name
= "MT_CG_PERI_PWM4",
2739 .grp
= &grps
[CG_PERI0
],
2741 .ops
= &general_cg_clk_ops
,
2743 [MT_CG_PERI_PWM5
] = {
2744 .name
= "MT_CG_PERI_PWM5",
2745 .grp
= &grps
[CG_PERI0
],
2747 .ops
= &general_cg_clk_ops
,
2749 [MT_CG_PERI_PWM6
] = {
2750 .name
= "MT_CG_PERI_PWM6",
2751 .grp
= &grps
[CG_PERI0
],
2753 .ops
= &general_cg_clk_ops
,
2755 [MT_CG_PERI_PWM7
] = {
2756 .name
= "MT_CG_PERI_PWM7",
2757 .grp
= &grps
[CG_PERI0
],
2759 .ops
= &general_cg_clk_ops
,
2761 [MT_CG_PERI_PWM
] = {
2762 .name
= "MT_CG_PERI_PWM",
2763 .grp
= &grps
[CG_PERI0
],
2765 .ops
= &general_cg_clk_ops
,
2767 [MT_CG_PERI_USB0
] = {
2768 .name
= "MT_CG_PERI_USB0",
2769 .grp
= &grps
[CG_PERI0
],
2771 .ops
= &general_cg_clk_ops
,
2772 .mux
= &muxs
[MT_MUX_USB20
],
2774 [MT_CG_PERI_USB1
] = {
2775 .name
= "MT_CG_PERI_USB1",
2776 .grp
= &grps
[CG_PERI0
],
2778 .ops
= &general_cg_clk_ops
,
2779 .mux
= &muxs
[MT_MUX_USB20
],
2781 [MT_CG_PERI_AP_DMA
] = {
2782 .name
= "MT_CG_PERI_AP_DMA",
2783 .grp
= &grps
[CG_PERI0
],
2785 .ops
= &general_cg_clk_ops
,
2787 [MT_CG_PERI_MSDC30_0
] = {
2788 .name
= "MT_CG_PERI_MSDC30_0",
2789 .grp
= &grps
[CG_PERI0
],
2791 .ops
= &general_cg_clk_ops
,
2792 .mux
= &muxs
[MT_MUX_MSDC30_0
],
2794 [MT_CG_PERI_MSDC30_1
] = {
2795 .name
= "MT_CG_PERI_MSDC30_1",
2796 .grp
= &grps
[CG_PERI0
],
2798 .ops
= &general_cg_clk_ops
,
2799 .mux
= &muxs
[MT_MUX_MSDC30_1
],
2801 [MT_CG_PERI_MSDC30_2
] = {
2802 .name
= "MT_CG_PERI_MSDC30_2",
2803 .grp
= &grps
[CG_PERI0
],
2805 .ops
= &general_cg_clk_ops
,
2806 .mux
= &muxs
[MT_MUX_MSDC30_2
],
2808 [MT_CG_PERI_NLI
] = {
2809 .name
= "MT_CG_PERI_NLI",
2810 .grp
= &grps
[CG_PERI0
],
2812 .ops
= &general_cg_clk_ops
,
2814 [MT_CG_PERI_UART0
] = {
2815 .name
= "MT_CG_PERI_UART0",
2816 .grp
= &grps
[CG_PERI0
],
2818 .ops
= &general_cg_clk_ops
,
2819 .mux
= &muxs
[MT_MUX_UART
],
2821 [MT_CG_PERI_UART1
] = {
2822 .name
= "MT_CG_PERI_UART1",
2823 .grp
= &grps
[CG_PERI0
],
2825 .ops
= &general_cg_clk_ops
,
2826 .mux
= &muxs
[MT_MUX_UART
],
2828 [MT_CG_PERI_UART2
] = {
2829 .name
= "MT_CG_PERI_UART2",
2830 .grp
= &grps
[CG_PERI0
],
2832 .ops
= &general_cg_clk_ops
,
2833 .mux
= &muxs
[MT_MUX_UART
],
2835 [MT_CG_PERI_UART3
] = {
2836 .name
= "MT_CG_PERI_UART3",
2837 .grp
= &grps
[CG_PERI0
],
2839 .ops
= &general_cg_clk_ops
,
2840 .mux
= &muxs
[MT_MUX_UART
],
2842 [MT_CG_PERI_BTIF
] = {
2843 .name
= "MT_CG_PERI_BTIF",
2844 .grp
= &grps
[CG_PERI0
],
2846 .ops
= &general_cg_clk_ops
,
2848 [MT_CG_PERI_I2C0
] = {
2849 .name
= "MT_CG_PERI_I2C0",
2850 .grp
= &grps
[CG_PERI0
],
2852 .ops
= &general_cg_clk_ops
,
2854 [MT_CG_PERI_I2C1
] = {
2855 .name
= "MT_CG_PERI_I2C1",
2856 .grp
= &grps
[CG_PERI0
],
2858 .ops
= &general_cg_clk_ops
,
2860 [MT_CG_PERI_I2C2
] = {
2861 .name
= "MT_CG_PERI_I2C2",
2862 .grp
= &grps
[CG_PERI0
],
2864 .ops
= &general_cg_clk_ops
,
2866 [MT_CG_PERI_I2C3
] = {
2867 .name
= "MT_CG_PERI_I2C3",
2868 .grp
= &grps
[CG_PERI0
],
2870 .ops
= &general_cg_clk_ops
,
2872 [MT_CG_PERI_AUXADC
] = {
2873 .name
= "MT_CG_PERI_AUXADC",
2874 .grp
= &grps
[CG_PERI0
],
2876 .ops
= &general_cg_clk_ops
,
2878 [MT_CG_PERI_SPI0
] = {
2879 .name
= "MT_CG_PERI_SPI0",
2880 .grp
= &grps
[CG_PERI0
],
2882 .ops
= &general_cg_clk_ops
,
2883 .mux
= &muxs
[MT_MUX_SPI
],
2885 [MT_CG_PERI_ETH
] = {
2886 .name
= "MT_CG_PERI_ETH",
2887 .grp
= &grps
[CG_PERI0
],
2889 .ops
= &general_cg_clk_ops
,
2890 .mux
= &muxs
[MT_MUX_ETH_50M
],
2892 [MT_CG_PERI_USB0_MCU
] = {
2893 .name
= "MT_CG_PERI_USB0_MCU",
2894 .grp
= &grps
[CG_PERI0
],
2896 .ops
= &general_cg_clk_ops
,
2898 [MT_CG_PERI_USB1_MCU
] = {
2899 .name
= "MT_CG_PERI_USB1_MCU",
2900 .grp
= &grps
[CG_PERI0
],
2902 .ops
= &general_cg_clk_ops
,
2904 [MT_CG_PERI_USB_SLV
] = {
2905 .name
= "MT_CG_PERI_USB_SLV",
2906 .grp
= &grps
[CG_PERI0
],
2908 .ops
= &general_cg_clk_ops
,
2910 [MT_CG_PERI_GCPU
] = {
2911 .name
= "MT_CG_PERI_GCPU",
2912 .grp
= &grps
[CG_PERI1
],
2914 .ops
= &general_cg_clk_ops
,
2916 [MT_CG_PERI_NFI_ECC
] = {
2917 .name
= "MT_CG_PERI_NFI_ECC",
2918 .grp
= &grps
[CG_PERI1
],
2920 .ops
= &general_cg_clk_ops
,
2921 .mux
= &muxs
[MT_MUX_NFI2X
],
2923 [MT_CG_PERI_NFIPAD
] = {
2924 .name
= "MT_CG_PERI_NFIPAD",
2925 .grp
= &grps
[CG_PERI1
],
2927 .ops
= &general_cg_clk_ops
,
2928 .mux
= &muxs
[MT_MUX_NFI2X
],
2931 [MT_CG_INFRA_DBGCLK
] = {
2932 .name
= "MT_CG_INFRA_DBGCLK",
2933 .grp
= &grps
[CG_INFRA
],
2935 .ops
= &general_cg_clk_ops
,
2937 [MT_CG_INFRA_SMI
] = {
2938 .name
= "MT_CG_INFRA_SMI",
2939 .grp
= &grps
[CG_INFRA
],
2941 .ops
= &general_cg_clk_ops
,
2943 [MT_CG_INFRA_AUDIO
] = {
2944 .name
= "MT_CG_INFRA_AUDIO",
2945 .grp
= &grps
[CG_INFRA
],
2947 .ops
= &audio_cg_clk_ops
,
2948 .mux
= &muxs
[MT_MUX_AUDINTBUS
],
2950 [MT_CG_INFRA_EFUSE
] = {
2951 .name
= "MT_CG_INFRA_EFUSE",
2952 .grp
= &grps
[CG_INFRA
],
2954 .ops
= &general_cg_clk_ops
,
2956 [MT_CG_INFRA_L2C_SRAM
] = {
2957 .name
= "MT_CG_INFRA_L2C_SRAM",
2958 .grp
= &grps
[CG_INFRA
],
2960 .ops
= &general_cg_clk_ops
,
2962 [MT_CG_INFRA_M4U
] = {
2963 .name
= "MT_CG_INFRA_M4U",
2964 .grp
= &grps
[CG_INFRA
],
2966 .ops
= &general_cg_clk_ops
,
2968 [MT_CG_INFRA_CONNMCU
] = {
2969 .name
= "MT_CG_INFRA_CONNMCU",
2970 .grp
= &grps
[CG_INFRA
],
2972 .ops
= &general_cg_clk_ops
,
2974 [MT_CG_INFRA_TRNG
] = {
2975 .name
= "MT_CG_INFRA_TRNG",
2976 .grp
= &grps
[CG_INFRA
],
2978 .ops
= &general_cg_clk_ops
,
2980 [MT_CG_INFRA_CPUM
] = {
2981 .name
= "MT_CG_INFRA_CPUM",
2982 .grp
= &grps
[CG_INFRA
],
2984 .ops
= &general_cg_clk_ops
,
2986 [MT_CG_INFRA_KP
] = {
2987 .name
= "MT_CG_INFRA_KP",
2988 .grp
= &grps
[CG_INFRA
],
2990 .ops
= &general_cg_clk_ops
,
2992 [MT_CG_INFRA_CEC
] = {
2993 .name
= "MT_CG_INFRA_CEC",
2994 .grp
= &grps
[CG_INFRA
],
2996 .ops
= &general_cg_clk_ops
,
2998 [MT_CG_INFRA_IRRX
] = {
2999 .name
= "MT_CG_INFRA_IRRX",
3000 .grp
= &grps
[CG_INFRA
],
3002 .ops
= &general_cg_clk_ops
,
3004 [MT_CG_INFRA_PMICSPI_SHARE
] = {
3005 .name
= "MT_CG_INFRA_PMICSPI_SHARE",
3006 .grp
= &grps
[CG_INFRA
],
3008 .ops
= &general_cg_clk_ops
,
3009 .mux
= &muxs
[MT_MUX_PMICSPI
],
3011 [MT_CG_INFRA_PMICWRAP
] = {
3012 .name
= "MT_CG_INFRA_PMICWRAP",
3013 .grp
= &grps
[CG_INFRA
],
3015 .ops
= &general_cg_clk_ops
,
3018 [MT_CG_TOPCK_PMICSPI
] = {
3019 .name
= "MT_CG_TOPCK_PMICSPI",
3020 .grp
= &grps
[CG_TOPCK
],
3022 .ops
= &general_cg_clk_ops
,
3025 [MT_CG_DISP0_SMI_COMMON
] = {
3026 .name
= "MT_CG_DISP0_SMI_COMMON",
3027 .grp
= &grps
[CG_DISP0
],
3029 .ops
= &general_cg_clk_ops
,
3031 [MT_CG_DISP0_SMI_LARB0
] = {
3032 .name
= "MT_CG_DISP0_SMI_LARB0",
3033 .grp
= &grps
[CG_DISP0
],
3035 .ops
= &general_cg_clk_ops
,
3037 [MT_CG_DISP0_MM_CMDQ
] = {
3038 .name
= "MT_CG_DISP0_MM_CMDQ",
3039 .grp
= &grps
[CG_DISP0
],
3041 .ops
= &general_cg_clk_ops
,
3043 [MT_CG_DISP0_MUTEX
] = {
3044 .name
= "MT_CG_DISP0_MUTEX",
3045 .grp
= &grps
[CG_DISP0
],
3047 .ops
= &general_cg_clk_ops
,
3049 [MT_CG_DISP0_DISP_COLOR
] = {
3050 .name
= "MT_CG_DISP0_DISP_COLOR",
3051 .grp
= &grps
[CG_DISP0
],
3053 .ops
= &general_cg_clk_ops
,
3055 [MT_CG_DISP0_DISP_BLS
] = {
3056 .name
= "MT_CG_DISP0_DISP_BLS",
3057 .grp
= &grps
[CG_DISP0
],
3059 .ops
= &general_cg_clk_ops
,
3060 .mux
= &muxs
[MT_MUX_PWM
],
3062 [MT_CG_DISP0_DISP_WDMA
] = {
3063 .name
= "MT_CG_DISP0_DISP_WDMA",
3064 .grp
= &grps
[CG_DISP0
],
3066 .ops
= &general_cg_clk_ops
,
3068 [MT_CG_DISP0_DISP_RDMA
] = {
3069 .name
= "MT_CG_DISP0_DISP_RDMA",
3070 .grp
= &grps
[CG_DISP0
],
3072 .ops
= &general_cg_clk_ops
,
3074 [MT_CG_DISP0_DISP_OVL
] = {
3075 .name
= "MT_CG_DISP0_DISP_OVL",
3076 .grp
= &grps
[CG_DISP0
],
3078 .ops
= &general_cg_clk_ops
,
3080 [MT_CG_DISP0_MDP_TDSHP
] = {
3081 .name
= "MT_CG_DISP0_MDP_TDSHP",
3082 .grp
= &grps
[CG_DISP0
],
3084 .ops
= &general_cg_clk_ops
,
3086 [MT_CG_DISP0_MDP_WROT
] = {
3087 .name
= "MT_CG_DISP0_MDP_WROT",
3088 .grp
= &grps
[CG_DISP0
],
3090 .ops
= &general_cg_clk_ops
,
3092 [MT_CG_DISP0_MDP_WDMA
] = {
3093 .name
= "MT_CG_DISP0_MDP_WDMA",
3094 .grp
= &grps
[CG_DISP0
],
3096 .ops
= &general_cg_clk_ops
,
3098 [MT_CG_DISP0_MDP_RSZ1
] = {
3099 .name
= "MT_CG_DISP0_MDP_RSZ1",
3100 .grp
= &grps
[CG_DISP0
],
3102 .ops
= &general_cg_clk_ops
,
3104 [MT_CG_DISP0_MDP_RSZ0
] = {
3105 .name
= "MT_CG_DISP0_MDP_RSZ0",
3106 .grp
= &grps
[CG_DISP0
],
3108 .ops
= &general_cg_clk_ops
,
3110 [MT_CG_DISP0_MDP_RDMA
] = {
3111 .name
= "MT_CG_DISP0_MDP_RDMA",
3112 .grp
= &grps
[CG_DISP0
],
3114 .ops
= &general_cg_clk_ops
,
3116 [MT_CG_DISP0_MDP_BLS_26M
] = {
3117 .name
= "MT_CG_DISP0_MDP_BLS_26M",
3118 .grp
= &grps
[CG_DISP0
],
3120 .ops
= &general_cg_clk_ops
,
3121 .mux
= &muxs
[MT_MUX_PWM
],
3123 [MT_CG_DISP0_CAM_MDP
] = {
3124 .name
= "MT_CG_DISP0_CAM_MDP",
3125 .grp
= &grps
[CG_DISP0
],
3127 .ops
= &general_cg_clk_ops
,
3129 [MT_CG_DISP0_FAKE_ENG
] = {
3130 .name
= "MT_CG_DISP0_FAKE_ENG",
3131 .grp
= &grps
[CG_DISP0
],
3133 .ops
= &general_cg_clk_ops
,
3135 [MT_CG_DISP0_MUTEX_32K
] = {
3136 .name
= "MT_CG_DISP0_MUTEX_32K",
3137 .grp
= &grps
[CG_DISP0
],
3139 .ops
= &general_cg_clk_ops
,
3141 [MT_CG_DISP0_DISP_RMDA1
] = {
3142 .name
= "MT_CG_DISP0_DISP_RMDA1",
3143 .grp
= &grps
[CG_DISP0
],
3145 .ops
= &general_cg_clk_ops
,
3147 [MT_CG_DISP0_DISP_UFOE
] = {
3148 .name
= "MT_CG_DISP0_DISP_UFOE",
3149 .grp
= &grps
[CG_DISP0
],
3151 .ops
= &general_cg_clk_ops
,
3154 [MT_CG_DISP1_DSI_ENGINE
] = {
3155 .name
= "MT_CG_DISP1_DSI_ENGINE",
3156 .grp
= &grps
[CG_DISP1
],
3158 .ops
= &general_cg_clk_ops
,
3160 [MT_CG_DISP1_DSI_DIGITAL
] = {
3161 .name
= "MT_CG_DISP1_DSI_DIGITAL",
3162 .grp
= &grps
[CG_DISP1
],
3164 .ops
= &general_cg_clk_ops
,
3166 [MT_CG_DISP1_DPI_DIGITAL_LANE
] = {
3167 .name
= "MT_CG_DISP1_DPI_DIGITAL_LANE",
3168 .grp
= &grps
[CG_DISP1
],
3170 .ops
= &general_cg_clk_ops
,
3172 [MT_CG_DISP1_DPI_ENGINE
] = {
3173 .name
= "MT_CG_DISP1_DPI_ENGINE",
3174 .grp
= &grps
[CG_DISP1
],
3176 .ops
= &general_cg_clk_ops
,
3178 [MT_CG_DISP1_DPI1_DIGITAL_LANE
] = {
3179 .name
= "MT_CG_DISP1_DPI1_DIGITAL_LANE",
3180 .grp
= &grps
[CG_DISP1
],
3182 .ops
= &general_cg_clk_ops
,
3183 .mux
= &muxs
[MT_MUX_DPI1
],
3185 [MT_CG_DISP1_DPI1_ENGINE
] = {
3186 .name
= "MT_CG_DISP1_DPI1_ENGINE",
3187 .grp
= &grps
[CG_DISP1
],
3189 .ops
= &general_cg_clk_ops
,
3191 [MT_CG_DISP1_TVE_OUTPUT_CLOCK
] = {
3192 .name
= "MT_CG_DISP1_TVE_OUTPUT_CLOCK",
3193 .grp
= &grps
[CG_DISP1
],
3195 .ops
= &general_cg_clk_ops
,
3196 .mux
= &muxs
[MT_MUX_TVE
],
3198 [MT_CG_DISP1_TVE_INPUT_CLOCK
] = {
3199 .name
= "MT_CG_DISP1_TVE_INPUT_CLOCK",
3200 .grp
= &grps
[CG_DISP1
],
3202 .ops
= &general_cg_clk_ops
,
3204 [MT_CG_DISP1_HDMI_PIXEL_CLOCK
] = {
3205 .name
= "MT_CG_DISP1_HDMI_PIXEL_CLOCK",
3206 .grp
= &grps
[CG_DISP1
],
3208 .ops
= &general_cg_clk_ops
,
3209 .mux
= &muxs
[MT_MUX_DPI1
],
3211 [MT_CG_DISP1_HDMI_PLL_CLOCK
] = {
3212 .name
= "MT_CG_DISP1_HDMI_PLL_CLOCK",
3213 .grp
= &grps
[CG_DISP1
],
3215 .ops
= &general_cg_clk_ops
,
3216 .mux
= &muxs
[MT_MUX_HDMI
],
3218 [MT_CG_DISP1_HDMI_AUDIO_CLOCK
] = {
3219 .name
= "MT_CG_DISP1_HDMI_AUDIO_CLOCK",
3220 .grp
= &grps
[CG_DISP1
],
3222 .ops
= &general_cg_clk_ops
,
3224 [MT_CG_DISP1_HDMI_SPDIF_CLOCK
] = {
3225 .name
= "MT_CG_DISP1_HDMI_SPDIF_CLOCK",
3226 .grp
= &grps
[CG_DISP1
],
3228 .ops
= &general_cg_clk_ops
,
3229 .mux
= &muxs
[MT_MUX_APLL
],
3231 [MT_CG_DISP1_LVDS_PIXEL_CLOCK
] = {
3232 .name
= "MT_CG_DISP1_LVDS_PIXEL_CLOCK",
3233 .grp
= &grps
[CG_DISP1
],
3235 .ops
= &general_cg_clk_ops
,
3237 [MT_CG_DISP1_LVDS_CTS_CLOCK
] = {
3238 .name
= "MT_CG_DISP1_LVDS_CTS_CLOCK",
3239 .grp
= &grps
[CG_DISP1
],
3241 .ops
= &general_cg_clk_ops
,
3244 [MT_CG_IMAGE_LARB2_SMI
] = {
3245 .name
= "MT_CG_IMAGE_LARB2_SMI",
3246 .grp
= &grps
[CG_IMAGE
],
3248 .ops
= &general_cg_clk_ops
,
3250 [MT_CG_IMAGE_CAM_SMI
] = {
3251 .name
= "MT_CG_IMAGE_CAM_SMI",
3252 .grp
= &grps
[CG_IMAGE
],
3254 .ops
= &general_cg_clk_ops
,
3256 [MT_CG_IMAGE_CAM_CAM
] = {
3257 .name
= "MT_CG_IMAGE_CAM_CAM",
3258 .grp
= &grps
[CG_IMAGE
],
3260 .ops
= &general_cg_clk_ops
,
3262 [MT_CG_IMAGE_SEN_TG
] = {
3263 .name
= "MT_CG_IMAGE_SEN_TG",
3264 .grp
= &grps
[CG_IMAGE
],
3266 .ops
= &general_cg_clk_ops
,
3267 .mux
= &muxs
[MT_MUX_CAMTG
],
3269 [MT_CG_IMAGE_SEN_CAM
] = {
3270 .name
= "MT_CG_IMAGE_SEN_CAM",
3271 .grp
= &grps
[CG_IMAGE
],
3273 .ops
= &general_cg_clk_ops
,
3274 .mux
= &muxs
[MT_MUX_CAMTG
],
3276 [MT_CG_IMAGE_VENC_JPENC
] = {
3277 .name
= "MT_CG_IMAGE_VENC_JPENC",
3278 .grp
= &grps
[CG_IMAGE
],
3280 .ops
= &general_cg_clk_ops
,
3284 .name
= "MT_CG_MFG_G3D",
3285 .grp
= &grps
[CG_MFG
],
3287 .ops
= &general_cg_clk_ops
,
3290 [MT_CG_AUDIO_AFE
] = {
3291 .name
= "MT_CG_AUDIO_AFE",
3292 .grp
= &grps
[CG_AUDIO
],
3294 .ops
= &audsys_cg_clk_ops
,
3295 .parent
= &clks
[MT_CG_INFRA_AUDIO
],
3297 [MT_CG_AUDIO_I2S
] = {
3298 .name
= "MT_CG_AUDIO_I2S",
3299 .grp
= &grps
[CG_AUDIO
],
3301 .ops
= &audsys_cg_clk_ops
,
3302 .parent
= &clks
[MT_CG_INFRA_AUDIO
],
3304 [MT_CG_AUDIO_APLL_TUNER_CK
] = {
3305 .name
= "MT_CG_AUDIO_APLL_TUNER_CK",
3306 .grp
= &grps
[CG_AUDIO
],
3308 .ops
= &audsys_cg_clk_ops
,
3309 .mux
= &muxs
[MT_MUX_APLL
],
3310 .parent
= &clks
[MT_CG_INFRA_AUDIO
],
3312 [MT_CG_AUDIO_HDMI_CK
] = {
3313 .name
= "MT_CG_AUDIO_HDMI_CK",
3314 .grp
= &grps
[CG_AUDIO
],
3316 .ops
= &audsys_cg_clk_ops
,
3317 .mux
= &muxs
[MT_MUX_APLL
],
3318 .parent
= &clks
[MT_CG_INFRA_AUDIO
],
3320 [MT_CG_AUDIO_SPDF_CK
] = {
3321 .name
= "MT_CG_AUDIO_SPDF_CK",
3322 .grp
= &grps
[CG_AUDIO
],
3324 .ops
= &audsys_cg_clk_ops
,
3325 .mux
= &muxs
[MT_MUX_APLL
],
3326 .parent
= &clks
[MT_CG_INFRA_AUDIO
],
3328 [MT_CG_AUDIO_SPDF2_CK
] = {
3329 .name
= "MT_CG_AUDIO_SPDF2_CK",
3330 .grp
= &grps
[CG_AUDIO
],
3332 .ops
= &audsys_cg_clk_ops
,
3333 .mux
= &muxs
[MT_MUX_APLL
],
3334 .parent
= &clks
[MT_CG_INFRA_AUDIO
],
3337 [MT_CG_VDEC0_VDEC
] = {
3338 .name
= "MT_CG_VDEC0_VDEC",
3339 .grp
= &grps
[CG_VDEC0
],
3341 .ops
= &vdec_cg_clk_ops
,
3342 .mux
= &muxs
[MT_MUX_VDEC
],
3345 [MT_CG_VDEC1_LARB
] = {
3346 .name
= "MT_CG_VDEC1_LARB",
3347 .grp
= &grps
[CG_VDEC1
],
3349 .ops
= &vdec_cg_clk_ops
,
3354 static struct cg_clk
*id_to_clk(unsigned int id
)
3356 return id
< NR_CLKS
? clks
+ id
: NULL
;
3359 static int general_clk_get_state_op(struct cg_clk
*clk
)
3361 struct subsys
*sys
= clk
->grp
->sys
;
3362 if (sys
&& !sys
->state
)
3365 return (clk_readl(clk
->grp
->sta_addr
) & (clk
->mask
)) ? PWR_DOWN
: PWR_ON
;
3368 static int general_clk_check_validity_op(struct cg_clk
*clk
)
3371 if (clk
->mask
& clk
->grp
->mask
)
3377 static int general_clk_enable_op(struct cg_clk
*clk
)
3380 clk_info("[%s]: clk->grp->name=%s, clk->mask=0x%x\n", __func__
, clk
->grp
->name
, clk
->mask
);
3383 clk_writel(clk
->grp
->clr_addr
, clk
->mask
);
3387 static int general_clk_disable_op(struct cg_clk
*clk
)
3390 clk_info("[%s]: clk->grp->name=%s, clk->mask=0x%x\n", __func__
, clk
->grp
->name
, clk
->mask
);
3393 clk_writel(clk
->grp
->set_addr
, clk
->mask
);
3397 static struct cg_clk_ops general_cg_clk_ops
= {
3398 .get_state
= general_clk_get_state_op
,
3399 .check_validity
= general_clk_check_validity_op
,
3400 .enable
= general_clk_enable_op
,
3401 .disable
= general_clk_disable_op
,
3404 static int audio_clk_enable_op(struct cg_clk
*clk
)
3407 clk_info("[%s]: clk->grp->name=%s, clk->mask=0x%x\n", __func__
, clk
->grp
->name
, clk
->mask
);
3410 clk_writel(clk
->grp
->clr_addr
, clk
->mask
);
3414 static int audio_clk_disable_op(struct cg_clk
*clk
)
3417 clk_info("[%s]: clk->grp->name=%s, clk->mask=0x%x\n", __func__
, clk
->grp
->name
, clk
->mask
);
3420 clk_writel(clk
->grp
->set_addr
, clk
->mask
);
3424 static struct cg_clk_ops audio_cg_clk_ops
= {
3425 .get_state
= general_clk_get_state_op
,
3426 .check_validity
= general_clk_check_validity_op
,
3427 .enable
= audio_clk_enable_op
,
3428 .disable
= audio_clk_disable_op
,
3432 static int audsys_clk_enable_op(struct cg_clk
*clk
)
3434 clk_clrl(clk
->grp
->sta_addr
, clk
->mask
);
3438 static int audsys_clk_disable_op(struct cg_clk
*clk
)
3440 clk_setl(clk
->grp
->sta_addr
, clk
->mask
);
3444 static struct cg_clk_ops audsys_cg_clk_ops
= {
3445 .get_state
= general_clk_get_state_op
,
3446 .check_validity
= general_clk_check_validity_op
,
3447 .enable
= audsys_clk_enable_op
,
3448 .disable
= audsys_clk_disable_op
,
3451 static int vdec_clk_get_state_op(struct cg_clk
*clk
)
3453 return (clk_readl(clk
->grp
->set_addr
) & (clk
->mask
)) ? PWR_ON
: PWR_DOWN
;
3456 static struct cg_clk_ops vdec_cg_clk_ops
= {
3457 .get_state
= vdec_clk_get_state_op
,
3458 .check_validity
= general_clk_check_validity_op
,
3459 .enable
= general_clk_enable_op
,
3460 .disable
= general_clk_disable_op
,
3464 static int power_prepare_locked(struct cg_grp
*grp
)
3468 err
= subsys_enable_internal(grp
->sys
, "clk");
3473 static int power_finish_locked(struct cg_grp
*grp
)
3477 err
= subsys_disable_internal(grp
->sys
, 0, "clk");
3482 static int clk_enable_locked(struct cg_clk
*clk
)
3484 struct cg_grp
*grp
= clk
->grp
;
3485 unsigned int local_state
;
3486 #ifdef STATE_CHECK_DEBUG
3487 unsigned int reg_state
;
3492 clk_info("[%s]: Start. grp->name=%s, grp->state=0x%x, clk->mask=0x%x, clk->cnt=%d, clk->state=%d\n",
3493 __func__
, grp
->name
, grp
->state
, clk
->mask
, clk
->cnt
, clk
->state
);
3501 local_state
= clk
->state
;
3503 #ifdef STATE_CHECK_DEBUG
3504 reg_state
= grp
->ops
->get_state(grp
, clk
);
3505 BUG_ON(local_state
!= reg_state
);
3508 #if !defined(CONFIG_MTK_LDVT)
3510 mux_enable_internal(clk
->mux
, "clk");
3512 err
= power_prepare_locked(grp
);
3517 clk_enable_internal(clk
->parent
, "clk");
3519 if (local_state
== PWR_ON
)
3522 clk
->ops
->enable(clk
);
3524 clk
->state
= PWR_ON
;
3525 grp
->state
|= clk
->mask
;
3527 clk_info("[%s]: End. grp->name=%s, grp->state=0x%x, clk->mask=0x%x, clk->cnt=%d, clk->state=%d\n",
3528 __func__
, grp
->name
, grp
->state
, clk
->mask
, clk
->cnt
, clk
->state
);
3534 static int clk_disable_locked(struct cg_clk
*clk
)
3536 struct cg_grp
*grp
= clk
->grp
;
3537 unsigned int local_state
;
3538 #ifdef STATE_CHECK_DEBUG
3539 unsigned int reg_state
;
3544 clk_info("[%s]: Start. grp->name=%s, grp->state=0x%x, clk->mask=0x%x, clk->cnt=%d, clk->state=%d\n",
3545 __func__
, grp
->name
, grp
->state
, clk
->mask
, clk
->cnt
, clk
->state
);
3548 #if defined(CONFIG_CLKMGR_BRINGUP)
3552 #if DISABLE_BUG_ON_CNT
3556 #else /* !DISABLE_BUG_ON_CNT */
3558 #endif /* DISABLE_BUG_ON_CNT */
3565 local_state
= clk
->state
;
3567 #ifdef STATE_CHECK_DEBUG
3568 reg_state
= grp
->ops
->get_state(grp
, clk
);
3569 BUG_ON(local_state
!= reg_state
);
3572 if (local_state
== PWR_DOWN
)
3578 clk
->ops
->disable(clk
);
3580 clk
->state
= PWR_DOWN
;
3581 grp
->state
&= ~(clk
->mask
);
3584 clk_disable_internal(clk
->parent
, "clk");
3586 #if !defined(CONFIG_MTK_LDVT)
3587 err
= power_finish_locked(grp
);
3591 mux_disable_internal(clk
->mux
, "clk");
3596 clk_info("[%s]: End. grp->name=%s, grp->state=0x%x, clk->mask=0x%x, clk->cnt=%d, clk->state=%d\n",
3597 __func__
, grp
->name
, grp
->state
, clk
->mask
, clk
->cnt
, clk
->state
);
3603 static int get_clk_state_locked(struct cg_clk
*clk
)
3605 if (likely(initialized
))
3608 return clk
->ops
->get_state(clk
);
3611 int mt_enable_clock(enum cg_clk_id id
, char *name
)
3614 unsigned long flags
;
3615 struct cg_clk
*clk
= id_to_clk(id
);
3617 #if defined(CONFIG_CLKMGR_BRINGUP) || defined(CONFIG_MT8127_FPGA)
3621 BUG_ON(!initialized
);
3624 BUG_ON(!clk
->ops
->check_validity(clk
));
3627 clk_info("[%s]: id=%d, names=%s\n", __func__
, id
, name
);
3629 if (id
== MT_CG_DISP0_SMI_COMMON
)
3630 clk_dbg("[%s]: id=%d, names=%s\n", __func__
, id
, name
);
3634 err
= clk_enable_internal(clk
, name
);
3635 clkmgr_unlock(flags
);
3639 EXPORT_SYMBOL(mt_enable_clock
);
3642 int mt_disable_clock(enum cg_clk_id id
, char *name
)
3645 unsigned long flags
;
3646 struct cg_clk
*clk
= id_to_clk(id
);
3648 #if defined(CONFIG_CLKMGR_BRINGUP) || defined(CONFIG_MT8127_FPGA)
3652 BUG_ON(!initialized
);
3655 BUG_ON(!clk
->ops
->check_validity(clk
));
3658 clk_info("[%s]: id=%d, names=%s\n", __func__
, id
, name
);
3660 if (id
== MT_CG_DISP0_SMI_COMMON
)
3661 clk_dbg("[%s]: id=%d, names=%s\n", __func__
, id
, name
);
3665 err
= clk_disable_internal(clk
, name
);
3666 clkmgr_unlock(flags
);
3670 EXPORT_SYMBOL(mt_disable_clock
);
3676 int enable_clock_ext_locked(int id
, char *name
)
3679 struct cg_clk
*clk
= id_to_clk(id
);
3681 #if defined(CONFIG_CLKMGR_BRINGUP)
3685 BUG_ON(!initialized
);
3688 BUG_ON(!clk
->ops
->check_validity(clk
));
3690 BUG_ON(!clkmgr_locked());
3691 err
= clk_enable_internal(clk
, name
);
3695 EXPORT_SYMBOL(enable_clock_ext_locked
);
3698 int disable_clock_ext_locked(int id
, char *name
)
3701 struct cg_clk
*clk
= id_to_clk(id
);
3703 #if defined(CONFIG_CLKMGR_BRINGUP)
3707 BUG_ON(!initialized
);
3710 BUG_ON(!clk
->ops
->check_validity(clk
));
3712 BUG_ON(!clkmgr_locked());
3713 err
= clk_disable_internal(clk
, name
);
3717 EXPORT_SYMBOL(disable_clock_ext_locked
);
3720 #endif /* !CLKMGR_8127 */
3723 int clock_is_on(int id
)
3726 unsigned long flags
;
3727 struct cg_clk
*clk
= id_to_clk(id
);
3729 #if defined(CONFIG_CLKMGR_BRINGUP) || defined(CONFIG_MT8127_FPGA)
3735 BUG_ON(!clk
->ops
->check_validity(clk
));
3738 state
= get_clk_state_locked(clk
);
3739 clkmgr_unlock(flags
);
3743 EXPORT_SYMBOL(clock_is_on
);
3746 static void clk_set_force_on_locked(struct cg_clk
*clk
)
3751 static void clk_clr_force_on_locked(struct cg_clk
*clk
)
3756 void clk_set_force_on(int id
)
3758 unsigned long flags
;
3759 struct cg_clk
*clk
= id_to_clk(id
);
3761 #if defined(CONFIG_CLKMGR_BRINGUP)
3765 BUG_ON(!initialized
);
3768 BUG_ON(!clk
->ops
->check_validity(clk
));
3771 clk_set_force_on_locked(clk
);
3772 clkmgr_unlock(flags
);
3774 EXPORT_SYMBOL(clk_set_force_on
);
3776 void clk_clr_force_on(int id
)
3778 unsigned long flags
;
3779 struct cg_clk
*clk
= id_to_clk(id
);
3781 #if defined(CONFIG_CLKMGR_BRINGUP)
3785 BUG_ON(!initialized
);
3788 BUG_ON(!clk
->ops
->check_validity(clk
));
3791 clk_clr_force_on_locked(clk
);
3792 clkmgr_unlock(flags
);
3794 EXPORT_SYMBOL(clk_clr_force_on
);
3796 int clk_is_force_on(int id
)
3798 struct cg_clk
*clk
= id_to_clk(id
);
3800 #if defined(CONFIG_CLKMGR_BRINGUP)
3804 BUG_ON(!initialized
);
3807 BUG_ON(!clk
->ops
->check_validity(clk
));
3809 return clk
->force_on
;
3812 int grp_dump_regs(int id
, unsigned int *ptr
)
3814 struct cg_grp
*grp
= id_to_grp(id
);
3818 return grp
->ops
->dump_regs(grp
, ptr
);
3820 EXPORT_SYMBOL(grp_dump_regs
);
3822 const char *grp_get_name(int id
)
3824 struct cg_grp
*grp
= id_to_grp(id
);
3831 void print_grp_regs(void)
3835 unsigned int value
[2];
3838 for (i
= 0; i
< NR_GRPS
; i
++) {
3839 name
= grp_get_name(i
);
3840 cnt
= grp_dump_regs(i
, value
);
3842 clk_info("[%02d][%-8s]=[0x%08x]\n", i
, name
, value
[0]);
3844 clk_info("[%02d][%-8s]=[0x%08x][0x%08x]\n", i
, name
, value
[0], value
[1]);
3848 int clk_id_to_grp_id(enum cg_clk_id id
)
3850 struct cg_clk
*clk
= id_to_clk(id
);
3851 return (NULL
== clk
) ? NR_GRPS
: (clk
->grp
- &grps
[0]);
3854 unsigned int clk_id_to_mask(enum cg_clk_id id
)
3856 struct cg_clk
*clk
= id_to_clk(id
);
3857 return (NULL
== clk
) ? 0 : clk
->mask
;
3862 /************************************************
3863 ********** initialization **********
3864 ************************************************/
3866 static void cg_all_force_on(void)
3869 for (i
= 0; i
< NR_CLKS
; i
++) {
3870 struct cg_clk
*clk
= id_to_clk(i
);
3871 BUG_ON(!clk
|| !clk
->ops
);
3873 clk
->ops
->enable(clk
);
3875 clk
->state
= PWR_ON
;
3876 clk
->grp
->mask
|= clk
->mask
;
3877 clk
->grp
->state
|= clk
->mask
;
3878 #ifdef CONFIG_CLKMGR_STAT
3879 INIT_LIST_HEAD(&clk
->head
);
3881 #endif /* !WORKAROUND_DAPC */
3885 static void cg_bootup_pdn(void)
3887 enum cg_clk_id ignored_pdn
[] = {
3892 MT_CG_PERI_USB0_MCU
,
3893 MT_CG_PERI_USB1_MCU
,
3901 MT_CG_INFRA_PMICSPI_SHARE
,
3902 MT_CG_INFRA_PMICWRAP
,
3903 MT_CG_TOPCK_PMICSPI
,
3904 MT_CG_DISP0_SMI_COMMON
,
3905 MT_CG_DISP0_SMI_LARB0
,
3906 MT_CG_DISP0_DISP_COLOR
,
3907 MT_CG_DISP0_DISP_BLS
,
3908 MT_CG_DISP0_DISP_RDMA
,
3909 MT_CG_DISP0_DISP_OVL
,
3910 MT_CG_DISP0_MDP_BLS_26M
,
3911 MT_CG_DISP0_MUTEX_32K
,
3912 MT_CG_DISP0_DISP_UFOE
,
3913 MT_CG_DISP1_DSI_ENGINE
,
3914 MT_CG_DISP1_DSI_DIGITAL
,
3915 MT_CG_DISP1_DPI_DIGITAL_LANE
,
3916 MT_CG_DISP1_DPI_ENGINE
,
3917 MT_CG_DISP1_LVDS_PIXEL_CLOCK
,
3918 MT_CG_DISP1_LVDS_CTS_CLOCK
,
3921 int len
= ARRAY_SIZE(ignored_pdn
);
3923 for (i
= NR_CLKS
- 1; i
>= 0; i
--) {
3927 for (j
= 0; j
< len
&& i
!= ignored_pdn
[j
]; j
++)
3930 if (j
!= len
) /* ignore this clock */
3934 clk
->ops
->disable(clk
);
3936 clk
->state
= PWR_DOWN
;
3937 clk
->grp
->state
&= ~(clk
->mask
);
3938 #endif /* !WORKAROUND_DAPC */
3943 static void mt_subsys_init(void)
3948 for (i
= 0; i
< NR_SYSS
; i
++) {
3950 sys
->state
= sys
->ops
->get_state(sys
);
3951 if (sys
->state
!= sys
->default_sta
) {
3952 clk_info("[%s]%s, change state: (%u->%u)\n", __func__
,
3953 sys
->name
, sys
->state
, sys
->default_sta
);
3954 if (sys
->default_sta
== PWR_DOWN
)
3955 sys_disable_locked(sys
, 1);
3957 sys_enable_locked(sys
);
3959 #ifdef CONFIG_CLKMGR_STAT
3960 INIT_LIST_HEAD(&sys
->head
);
3965 static void mt_plls_init(void)
3969 for (i
= 0; i
< NR_PLLS
; i
++) {
3971 pll
->state
= pll
->ops
->get_state(pll
);
3973 #ifdef CONFIG_CLKMGR_STAT
3974 INIT_LIST_HEAD(&pll
->head
);
3983 static void mt_plls_enable_hp(void)
3987 for (i
= 0; i
< NR_PLLS
; i
++) {
3989 if (pll
->ops
->hp_enable
)
3990 pll
->ops
->hp_enable(pll
);
3995 #endif /* CLKMGR_8127 */
3998 static void mt_muxs_init(void)
4003 clk_setl(CLK_CFG_2
, 0x00008000);
4005 for (i
= 0; i
< NR_MUXS
; i
++) {
4007 #ifdef CONFIG_CLKMGR_STAT
4008 INIT_LIST_HEAD(&mux
->head
);
4015 static void mt_clks_init(void)
4017 #if !WORKAROUND_DAPC
4022 for (i
= 0; i
< NR_CLKS
; i
++) {
4024 BUG_ON(!clk
|| !clk
->ops
);
4026 clk
->state
= clk
->ops
->get_state(clk
);
4027 clk
->grp
->mask
|= clk
->mask
;
4029 #ifdef CONFIG_CLKMGR_STAT
4030 INIT_LIST_HEAD(&clk
->head
);
4034 for (i
= 0; i
< NR_GRPS
; i
++) {
4036 grp
->state
= grp
->ops
->get_state(grp
);
4038 #endif /* !WORKAROUND_DAPC */
4040 /* Don't disable these clock until it's clk_clr_force_on() is called */
4041 clk_set_force_on_locked(&clks
[MT_CG_DISP0_SMI_LARB0
]);
4042 clk_set_force_on_locked(&clks
[MT_CG_DISP0_SMI_COMMON
]);
4048 static int id_from_mux(struct clkmux
*mux
)
4051 for (i
= 0; i
< NR_MUXS
; i
++) {
4052 if (mux
== &muxs
[i
])
4060 static int id_from_pll(struct pll
*p
)
4063 for (i
= 0; i
< NR_PLLS
; i
++) {
4072 static void init_pll_by_mux(int muxid
, int8_t *mux_init
, int8_t *pll_init
, int clkstate
, int sysstate
)
4079 if (mux_init
[muxid
] < 0)
4080 mux_init
[muxid
] = 0;
4082 if (clkstate
== PWR_ON
|| sysstate
== PWR_ON
)
4085 mux
= id_to_mux(muxid
);
4087 if (sysstate
== PWR_ON
) {
4094 if (mux_init
[muxid
] > 1 && sysstate
!= PWR_ON
)
4098 int pllid
= id_from_pll(mux
->pll
);
4100 if (pll_init
[pllid
] < 0)
4101 pll_init
[pllid
] = 0;
4103 if (clkstate
== PWR_ON
)
4109 int id
= id_from_mux(mux
->parent
);
4110 init_pll_by_mux(id
, mux_init
, pll_init
, clkstate
, sysstate
);
4113 if (mux
->siblings
) {
4114 int id
= id_from_mux(mux
->siblings
);
4115 init_pll_by_mux(id
, mux_init
, pll_init
, clkstate
, sysstate
);
4120 static void init_mux_pll_by_clk(struct cg_clk
*clk
, int8_t *mux_init
, int8_t *pll_init
)
4126 int id
= id_from_mux(clk
->mux
);
4127 init_pll_by_mux(id
, mux_init
, pll_init
, clk
->state
, PWR_DOWN
);
4130 if (clk
->grp
&& clk
->grp
->sys
&& clk
->grp
->sys
->mux
) {
4131 int id
= id_from_mux(clk
->grp
->sys
->mux
);
4132 init_pll_by_mux(id
, mux_init
, pll_init
, clk
->state
, PWR_DOWN
);
4136 init_mux_pll_by_clk(clk
->parent
, mux_init
, pll_init
);
4140 static void init_mux_pll_by_subsys(struct subsys
*sys
, int8_t *mux_init
, int8_t *pll_init
)
4146 int id
= id_from_mux(sys
->mux
);
4147 init_pll_by_mux(id
, mux_init
, pll_init
, PWR_DOWN
, sys
->state
);
4152 static void mt_clk_mux_pll_post_init(void)
4156 int8_t mux_init
[NR_MUXS
]; /* -1: ignore ; 0: off ; 1+: on */
4157 int8_t pll_init
[NR_PLLS
];
4159 memset(mux_init
, -1, sizeof(mux_init
));
4160 memset(pll_init
, -1, sizeof(pll_init
));
4162 for (i
= 0; i
< NR_CLKS
; i
++) {
4163 struct cg_clk
*clk
= id_to_clk(i
);
4164 init_mux_pll_by_clk(clk
, mux_init
, pll_init
);
4167 for (i
= 0; i
< NR_SYSS
; i
++) {
4168 struct subsys
*sys
= id_to_sys(i
);
4169 init_mux_pll_by_subsys(sys
, mux_init
, pll_init
);
4172 for (i
= 0; i
< NR_MUXS
; i
++) {
4173 struct clkmux
*mux
= id_to_mux(i
);
4175 if (mux_init
[i
] || mux
->cnt
> 0)
4176 mux
->ops
->enable(mux
);
4178 mux
->ops
->disable(mux
);
4181 for (i
= 0; i
< NR_PLLS
; i
++) {
4182 struct pll
*p
= id_to_pll(i
);
4184 if (pll_init
[i
] || p
->cnt
> 0) {
4189 p
->state
= PWR_DOWN
;
4195 #endif /* CLKMGR_8127 */
4198 int mt_clkmgr_bringup_init(void)
4200 #if (!defined(CONFIG_CLKMGR_BRINGUP) && !defined(CONFIG_MTK_LDVT))
4201 BUG_ON(initialized
);
4207 spm_mtcmos_ctrl_vdec(STA_POWER_ON
);
4208 spm_mtcmos_ctrl_isp(STA_POWER_ON
);
4209 spm_mtcmos_ctrl_mfg(STA_POWER_ON
);
4212 #if (!defined(CONFIG_CLKMGR_BRINGUP) && !defined(CONFIG_MTK_LDVT))
4215 #if (!defined(CONFIG_CLKMGR_BRINGUP))
4221 mt_clk_mux_pll_post_init();
4222 #endif /* CLKMGR_8127 */
4226 mt_freqhopping_init();
4227 mt_freqhopping_pll_init();
4228 #if !defined(CONFIG_CLKMGR_BRINGUP) && !WORKAROUND_DAPC
4234 void mt_clkmgr_init(void)
4238 mt_clkmgr_bringup_init();
4240 #else /* !CLKMGR_8127 */
4242 unsigned long flags
;
4243 BUG_ON(initialized
);
4249 mt_clk_mux_pll_post_init();
4253 mt_freqhopping_init();
4256 mt_freqhopping_pll_init();
4257 mt_plls_enable_hp();
4258 clkmgr_unlock(flags
);
4260 #endif /* CLKMGR_8127 */
4265 #ifdef CONFIG_MTK_MMC
4266 /* msdc_clk_status() is declared in mt_clkmgr.h */
4268 void msdc_clk_status(int *status
)
4274 bool clkmgr_idle_can_enter(unsigned int *condition_mask
, unsigned int *block_mask
)
4277 unsigned int cg_mask
= 0;
4279 #ifdef MTK_EMMC_SUPPORT
4280 unsigned int sd_mask
= 0;
4281 msdc_clk_status(&sd_mask
);
4283 block_mask
[CG_PERI0
] |= sd_mask
;
4288 for (i
= CG_PERI0
; i
< NR_GRPS
; i
++) {
4289 cg_mask
= grps
[i
].state
& condition_mask
[i
];
4291 for (j
= CG_PERI0
; j
< NR_GRPS
; j
++)
4292 block_mask
[j
] = grps
[j
].state
& condition_mask
[j
];
4302 bool isp_vdec_on_off(void)
4306 state
= subsys_is_on(SYS_ISP
);
4307 if (state
== PWR_ON
)
4310 state
= subsys_is_on(SYS_VDE
);
4311 if (state
== PWR_ON
)
4316 EXPORT_SYMBOL(isp_vdec_on_off
);
4319 /************************************************
4320 ********** function debug **********
4321 ************************************************/
4326 static void dump_pll_info1(struct seq_file
*s
, int clkidx
)
4328 if (clkidx
< NR_PLLS
) {
4329 struct pll
*pll
= &plls
[clkidx
];
4330 unsigned int freq
= pll_freq_calc_op(pll
);
4332 seq_printf(s
, "[%d] %7s: %4d.%03d MHz: %3s (%2d)\n",
4333 clkidx
, pll
->name
, freq
/ 1000, freq
% 1000, pll
->state
? "ON" : "off", pll
->cnt
);
4338 #endif /* CLKMGR_8127 */
4341 static int pll_test_show(struct seq_file
*s
, void *v
)
4345 unsigned int value
[3];
4349 for (i
= 0; i
< NR_PLLS
; i
++)
4350 dump_pll_info1(s
, i
);
4351 #endif /* CLKMGR_8127 */
4353 seq_printf(s
, "********** pll register dump **********\n");
4354 for (i
= 0; i
< NR_PLLS
; i
++) {
4355 name
= pll_get_name(i
);
4356 cnt
= pll_dump_regs(i
, value
);
4357 for (j
= 0; j
< cnt
; j
++)
4358 seq_printf(s
, "[%d][%-7s reg%d]=[0x%08x]\n", i
, name
, j
, value
[j
]);
4360 seq_printf(s
, "MIPI : CLK_DSI_PLL_CON0=0x%08x\n", clk_readl(CLK_DSI_PLL_CON0
));
4362 seq_printf(s
, "\n********** pll_test help **********\n");
4363 seq_printf(s
, "enable pll: echo enable id [mod_name] > /proc/clkmgr/pll_test\n");
4364 seq_printf(s
, "disable pll: echo disable id [mod_name] > /proc/clkmgr/pll_test\n");
4366 seq_printf(s
, "set freq : echo setfreq id freq_khz > /proc/clkmgr/pll_test\n");
4367 #endif /* CLKMGR_8127 */
4373 static int pll_test_open(struct inode
*inode
, struct file
*file
)
4375 return single_open(file
, pll_test_show
, NULL
);
4379 static int pll_test_write(struct file
*file
, const char *buffer
, size_t count
, loff_t
*data
)
4390 len
= (count
< (sizeof(desc
) - 1)) ? count
: (sizeof(desc
) - 1);
4391 if (copy_from_user(desc
, buffer
, len
))
4396 if (sscanf(desc
, "%s %d %u", cmd
, &id
, &freq
) == 3) {
4397 if (!strcmp(cmd
, "setfreq")) {
4398 unsigned int r
= pll_set_freq(id
, freq
);
4400 clk_info("pll_set_freq(): 0x%08x, id: %d, freq: %u\n", r
, id
, freq
);
4402 } else if (sscanf(desc
, "%s %d %s", cmd
, &id
, mod_name
) == 3) {
4403 if (!strcmp(cmd
, "enable"))
4404 err
= enable_pll(id
, mod_name
);
4405 else if (!strcmp(cmd
, "disable"))
4406 err
= disable_pll(id
, mod_name
);
4407 } else if (sscanf(desc
, "%s %d", cmd
, &id
) == 2) {
4408 if (!strcmp(cmd
, "enable"))
4409 err
= enable_pll(id
, "pll_test");
4410 else if (!strcmp(cmd
, "disable"))
4411 err
= disable_pll(id
, "pll_test");
4414 clk_info("[%s]%s pll %d: result is %d\n", __func__
, cmd
, id
, err
);
4420 static const struct file_operations pll_test_fops
= {
4421 .owner
= THIS_MODULE
,
4422 .write
= pll_test_write
,
4423 .open
= pll_test_open
,
4425 .llseek
= seq_lseek
,
4426 .release
= seq_release
4430 static int pll_fsel_show(struct seq_file
*s
, void *v
)
4434 unsigned int value
[3];
4437 for (i
= 0; i
< NR_PLLS
; i
++) {
4438 name
= pll_get_name(i
);
4440 cnt
= pll_dump_regs(i
, value
);
4442 seq_printf(s
, "[%d][%-7s]=[0x%08x%08x]\n", i
, name
, value
[0], value
[1]);
4444 seq_printf(s
, "[%d][%-7s]=[0x%08x]\n", i
, name
, value
[0]);
4446 seq_printf(s
, "[%d][%-7s]=[-1]\n", i
, name
);
4449 seq_printf(s
, "\n********** pll_fsel help **********\n");
4450 seq_printf(s
, "adjust pll frequency: echo id freq > /proc/clkmgr/pll_fsel\n");
4456 static int pll_fsel_open(struct inode
*inode
, struct file
*file
)
4458 return single_open(file
, pll_fsel_show
, NULL
);
4462 static int pll_fsel_write(struct file
*file
, const char *buffer
, size_t count
, loff_t
*data
)
4470 len
= (count
< (sizeof(desc
) - 1)) ? count
: (sizeof(desc
) - 1);
4471 if (copy_from_user(desc
, buffer
, len
))
4476 if (sscanf(desc
, "%d %x", &id
, &value
) == 2)
4477 pll_fsel(id
, value
);
4483 static const struct file_operations pll_fsel_fops
= {
4484 .owner
= THIS_MODULE
,
4485 .write
= pll_fsel_write
,
4486 .open
= pll_fsel_open
,
4488 .llseek
= seq_lseek
,
4489 .release
= seq_release
4493 #ifdef CONFIG_CLKMGR_STAT
4496 static int pll_stat_show(struct seq_file
*s
, void *v
)
4499 struct list_head
*pos
;
4500 struct stat_node
*node
;
4503 seq_printf(s
, "\n********** pll stat dump **********\n");
4504 for (i
= 0; i
< NR_PLLS
; i
++) {
4506 seq_printf(s
, "[%d][%-7s]state=%u, cnt=%u", i
, pll
->name
,
4507 pll
->state
, pll
->cnt
);
4508 list_for_each(pos
, &pll
->head
) {
4509 node
= list_entry(pos
, struct stat_node
, link
);
4510 seq_printf(s
, "\t(%s,%u,%u)", node
->name
, node
->cnt_on
, node
->cnt_off
);
4512 seq_printf(s
, "\n");
4515 seq_printf(s
, "\n********** pll_dump help **********\n");
4521 static int pll_stat_open(struct inode
*inode
, struct file
*file
)
4523 return single_open(file
, pll_stat_show
, NULL
);
4527 static const struct file_operations pll_stat_fops
= {
4528 .owner
= THIS_MODULE
,
4529 .open
= pll_stat_open
,
4531 .llseek
= seq_lseek
,
4532 .release
= seq_release
4536 #endif /* CONFIG_CLKMGR_STAT */
4539 static int subsys_test_show(struct seq_file
*s
, void *v
)
4543 unsigned int value
= 0, sta
, sta_s
;
4546 sta
= clk_readl(SPM_PWR_STATUS
);
4547 sta_s
= clk_readl(SPM_PWR_STATUS_S
);
4549 seq_printf(s
, "********** subsys register dump **********\n");
4550 for (i
= 0; i
< NR_SYSS
; i
++) {
4551 name
= subsys_get_name(i
);
4552 state
= subsys_is_on(i
);
4553 subsys_dump_regs(i
, &value
);
4554 seq_printf(s
, "[%d][%-8s]=[0x%08x], state(%u)\n", i
, name
, value
, state
);
4556 seq_printf(s
, "SPM_PWR_STATUS=0x%08x, SPM_PWR_STATUS_S=0x%08x\n", sta
, sta_s
);
4558 seq_printf(s
, "\n********** subsys_test help **********\n");
4559 seq_printf(s
, "enable subsys: echo enable id > /proc/clkmgr/subsys_test\n");
4560 seq_printf(s
, "disable subsys: echo disable id [force_off] > /proc/clkmgr/subsys_test\n");
4566 static int subsys_test_open(struct inode
*inode
, struct file
*file
)
4568 return single_open(file
, subsys_test_show
, NULL
);
4572 static int subsys_test_write(struct file
*file
, const char *buffer
, size_t count
, loff_t
*data
)
4582 len
= (count
< (sizeof(desc
) - 1)) ? count
: (sizeof(desc
) - 1);
4583 if (copy_from_user(desc
, buffer
, len
))
4588 if (sscanf(desc
, "%s %d %d", cmd
, &id
, &force_off
) == 3) {
4589 if (!strcmp(cmd
, "disable"))
4590 err
= disable_subsys_force(id
, "test");
4591 } else if (sscanf(desc
, "%s %d", cmd
, &id
) == 2) {
4592 if (!strcmp(cmd
, "enable"))
4593 err
= enable_subsys(id
, "test");
4594 else if (!strcmp(cmd
, "disable"))
4595 err
= disable_subsys(id
, "test");
4598 clk_info("[%s]%s subsys %d: result is %d\n", __func__
, cmd
, id
, err
);
4604 static const struct file_operations subsys_test_fops
= {
4605 .owner
= THIS_MODULE
,
4606 .write
= subsys_test_write
,
4607 .open
= subsys_test_open
,
4609 .llseek
= seq_lseek
,
4610 .release
= seq_release
4614 #ifdef CONFIG_CLKMGR_STAT
4617 static int subsys_stat_show(struct seq_file
*s
, void *v
)
4620 struct list_head
*pos
;
4621 struct stat_node
*node
;
4624 seq_printf(s
, "\n********** subsys stat dump **********\n");
4625 for (i
= 0; i
< NR_SYSS
; i
++) {
4627 seq_printf(s
, "[%d][%-7s]state=%u", i
, sys
->name
, sys
->state
);
4628 list_for_each(pos
, &sys
->head
) {
4629 node
= list_entry(pos
, struct stat_node
, link
);
4630 seq_printf(s
, "\t(%s,%u,%u)", node
->name
, node
->cnt_on
, node
->cnt_off
);
4632 seq_printf(s
, "\n");
4635 seq_printf(s
, "\n********** subsys_dump help **********\n");
4641 static int subsys_stat_open(struct inode
*inode
, struct file
*file
)
4643 return single_open(file
, subsys_stat_show
, NULL
);
4647 static const struct file_operations subsys_stat_fops
= {
4648 .owner
= THIS_MODULE
,
4649 .open
= subsys_stat_open
,
4651 .llseek
= seq_lseek
,
4652 .release
= seq_release
4662 #define MAX_MUX_CLKSRC 12
4671 static const char * const ABIST_CLK_NAME
[] = {
4672 [ABIST_AD_MAIN_H546M_CK
] = "AD_MAIN_H546M_CK",
4673 [ABIST_AD_MAIN_H364M_CK
] = "AD_MAIN_H364M_CK",
4674 [ABIST_AD_MAIN_H218P4M_CK
] = "AD_MAIN_H218P4M_CK",
4675 [ABIST_AD_MAIN_H156M_CK
] = "AD_MAIN_H156M_CK",
4676 [ABIST_AD_UNIV_624M_CK
] = "AD_UNIV_624M_CK",
4677 [ABIST_AD_UNIV_416M_CK
] = "AD_UNIV_416M_CK",
4678 [ABIST_AD_UNIV_249P6M_CK
] = "AD_UNIV_249P6M_CK",
4679 [ABIST_AD_UNIV_178P3M_CK
] = "AD_UNIV_178P3M_CK",
4680 [ABIST_AD_UNIV_48M_CK
] = "AD_UNIV_48M_CK",
4681 [ABIST_AD_USB_48M_CK
] = "AD_USB_48M_CK",
4682 [ABIST_AD_MMPLL_CK
] = "AD_MMPLL_CK",
4683 [ABIST_AD_MSDCPLL_CK
] = "AD_MSDCPLL_CK",
4684 [ABIST_AD_DPICLK
] = "AD_DPICLK",
4685 [ABIST_CLKPH_MCK_O
] = "clkph_mck_o",
4686 [ABIST_AD_MEMPLL2_CKOUT0_PRE_ISO
] = "AD_MEMPLL2_CKOUT0_PRE_ISO",
4687 [ABIST_AD_MCUPLL1_H481M_CK
] = "AD_MCUPLL1_H481M_CK",
4688 [ABIST_AD_MDPLL1_416M_CK
] = "AD_MDPLL1_416M_CK",
4689 [ABIST_AD_WPLL_CK
] = "AD_WPLL_CK",
4690 [ABIST_AD_WHPLL_CK
] = "AD_WHPLL_CK",
4691 [ABIST_RTC32K_CK_I
] = "rtc32k_ck_i",
4692 [ABIST_AD_SYS_26M_CK
] = "AD_SYS_26M_CK",
4693 [ABIST_AD_VENCPLL_CK
] = "AD_VENCPLL_CK",
4694 [ABIST_AD_MIPI_26M_CK
] = "AD_MIPI_26M_CK",
4695 [ABIST_AD_MEM_26M_CK
] = "AD_MEM_26M_CK",
4696 [ABIST_AD_PLLGP_TST_CK
] = "AD_PLLGP_TST_CK",
4697 [ABIST_AD_DSI0_LNTC_DSICLK
] = "AD_DSI0_LNTC_DSICLK",
4698 [ABIST_AD_MPPLL_TST_CK
] = "AD_MPPLL_TST_CK",
4699 [ABIST_ARMPLL_OCC_MON
] = "armpll_occ_mon",
4700 [ABIST_AD_MEM2MIPI_26M_CK
] = "AD_MEM2MIPI_26M_CK",
4701 [ABIST_AD_MEMPLL_MONCLK
] = "AD_MEMPLL_MONCLK",
4702 [ABIST_AD_MEMPLL2_MONCLK
] = "AD_MEMPLL2_MONCLK",
4703 [ABIST_AD_MEMPLL3_MONCLK
] = "AD_MEMPLL3_MONCLK",
4704 [ABIST_AD_MEMPLL4_MONCLK
] = "AD_MEMPLL4_MONCLK",
4705 [ABIST_AD_MEMPLL_REFCLK
] = "AD_MEMPLL_REFCLK",
4706 [ABIST_AD_MEMPLL_FBCLK
] = "AD_MEMPLL_FBCLK",
4707 [ABIST_AD_MEMPLL2_REFCLK
] = "AD_MEMPLL2_REFCLK",
4708 [ABIST_AD_MEMPLL2_FBCLK
] = "AD_MEMPLL2_FBCLK",
4709 [ABIST_AD_MEMPLL3_REFCLK
] = "AD_MEMPLL3_REFCLK",
4710 [ABIST_AD_MEMPLL3_FBCLK
] = "AD_MEMPLL3_FBCLK",
4711 [ABIST_AD_MEMPLL4_REFCLK
] = "AD_MEMPLL4_REFCLK",
4712 [ABIST_AD_MEMPLL4_FBCLK
] = "AD_MEMPLL4_FBCLK",
4713 [ABIST_AD_MEMPLL_TSTDIV2_CK
] = "AD_MEMPLL_TSTDIV2_CK",
4714 [ABIST_AD_LVDSPLL_CK
] = "AD_LVDSPLL_CK",
4715 [ABIST_AD_LVDSTX_MONCLK
] = "AD_LVDSTX_MONCLK",
4716 [ABIST_AD_HDMITX_MONCLK
] = "AD_HDMITX_MONCLK",
4717 [ABIST_AD_USB20_C240M
] = "AD_USB20_C240M",
4718 [ABIST_AD_USB20_C240M_1P
] = "AD_USB20_C240M_1P",
4719 [ABIST_AD_MONREF_CK
] = "AD_MONREF_CK",
4720 [ABIST_AD_MONFBK_CK
] = "AD_MONFBK_CK",
4721 [ABIST_AD_TVDPLL_CK
] = "AD_TVDPLL_CK",
4722 [ABIST_AD_AUDPLL_CK
] = "AD_AUDPLL_CK",
4723 [ABIST_AD_LVDSPLL_ETH_CK
] = "AD_LVDSPLL_ETH_CK",
4727 static const char * const CKGEN_CLK_NAME
[] = {
4728 [CKGEN_HF_FAXI_CK
] = "hf_faxi_ck",
4729 [CKGEN_HD_FAXI_CK
] = "hd_faxi_ck",
4730 [CKGEN_HF_FNFI2X_CK
] = "hf_fnfi2x_ck",
4731 [CKGEN_HF_FDDRPHYCFG_CK
] = "hf_fddrphycfg_ck",
4732 [CKGEN_HF_FMM_CK
] = "hf_fmm_ck",
4733 [CKGEN_F_FPWM_CK
] = "f_fpwm_ck",
4734 [CKGEN_HF_FVDEC_CK
] = "hf_fvdec_ck",
4735 [CKGEN_HF_FMFG_CK
] = "hf_fmfg_ck",
4736 [CKGEN_HF_FCAMTG_CK
] = "hf_fcamtg_ck",
4737 [CKGEN_F_FUART_CK
] = "f_fuart_ck",
4738 [CKGEN_HF_FSPI_CK
] = "hf_fspi_ck",
4739 [CKGEN_F_FUSB20_CK
] = "f_fusb20_ck",
4740 [CKGEN_HF_FMSDC30_0_CK
] = "hf_fmsdc30_0_ck",
4741 [CKGEN_HF_FMSDC30_1_CK
] = "hf_fmsdc30_1_ck",
4742 [CKGEN_HF_FMSDC30_2_CK
] = "hf_fmsdc30_2_ck",
4743 [CKGEN_HF_FAUDIO_CK
] = "hf_faudio_ck",
4744 [CKGEN_HF_FAUD_INTBUS_CK
] = "hf_faud_intbus_ck",
4745 [CKGEN_HF_FPMICSPI_CK
] = "hf_fpmicspi_ck",
4746 [CKGEN_F_FRTC_CK
] = "f_frtc_ck",
4747 [CKGEN_F_F26M_CK
] = "f_f26m_ck",
4748 [CKGEN_F_F32K_MD1_CK
] = "f_f32k_md1_ck",
4749 [CKGEN_F_FRTC_CONN_CK
] = "f_frtc_conn_ck",
4750 [CKGEN_HF_FETH_50M_CK
] = "hf_feth_50m_ck",
4751 [CKGEN_HD_HAXI_NLI_CK
] = "hd_haxi_nli_ck",
4752 [CKGEN_HD_QAXIDCM_CK
] = "hd_qaxidcm_ck",
4753 [CKGEN_F_FFPC_CK
] = "f_ffpc_ck",
4754 [CKGEN_HF_FDPI0_CK
] = "hf_fdpi0_ck",
4755 [CKGEN_F_FCKBUS_CK_SCAN
] = "f_fckbus_ck_scan",
4756 [CKGEN_F_FCKRTC_CK_SCAN
] = "f_fckrtc_ck_scan",
4757 [CKGEN_HF_FDPILVDS_CK
] = "hf_fdpilvds_ck",
4761 enum mux_clksrc_id
{
4829 enum CKGEN_CLK ckgen_clk
;
4830 enum mux_clksrc_id clksrc
[MAX_MUX_CLKSRC
];
4834 static const char * const clksrc_name
[] = {
4835 [external_32k
] = "32k_external",
4836 [internal_32k
] = "32k_internal",
4837 [audpll
] = "audpll",
4838 [audpll_d16
] = "audpll_d16",
4839 [audpll_d24
] = "audpll_d24",
4840 [audpll_d4
] = "audpll_d4",
4841 [audpll_d8
] = "audpll_d8",
4842 [clk26m
] = "clk26m",
4843 [dmpll_ck
] = "dmpll_ck",
4844 [dmpll_d2
] = "dmpll_d2",
4845 [dmpll_d4
] = "dmpll_d4",
4846 [dmpll_x2_ck
] = "dmpll_x2_ck",
4847 [f_f26m_ck
] = "f_f26m_ck",
4848 [fpc_ck
] = "fpc_ck",
4849 [hdmipll
] = "hdmipll",
4850 [hdmipll_d2
] = "hdmipll_d2",
4851 [hdmipll_d3
] = "hdmipll_d3",
4852 [lvdspll
] = "lvdspll",
4853 [lvdspll_d2
] = "lvdspll_d2",
4854 [lvdspll_d4
] = "lvdspll_d4",
4855 [lvdspll_d8
] = "lvdspll_d8",
4856 [lvdspll_eth
] = "lvdspll_eth",
4857 [mipipll
] = "mipipll",
4858 [mipipll_d2
] = "mipipll_d2",
4859 [mipipll_d4
] = "mipipll_d4",
4860 [mmpll_ck
] = "mmpll_ck",
4861 [mmpll_d2
] = "mmpll_d2",
4862 [msdcpll_ck
] = "msdcpll_ck",
4863 [msdcpll_d2
] = "msdcpll_d2",
4864 [syspll1_d16
] = "syspll1_d16",
4865 [syspll1_d2
] = "syspll1_d2",
4866 [syspll1_d4
] = "syspll1_d4",
4867 [syspll1_d8
] = "syspll1_d8",
4868 [syspll2_d2
] = "syspll2_d2",
4869 [syspll2_d4
] = "syspll2_d4",
4870 [syspll2_d8
] = "syspll2_d8",
4871 [syspll3_d2
] = "syspll3_d2",
4872 [syspll3_d4
] = "syspll3_d4",
4873 [syspll4_d2
] = "syspll4_d2",
4874 [syspll4_d4
] = "syspll4_d4",
4875 [syspll_d3
] = "syspll_d3",
4876 [syspll_d5
] = "syspll_d5",
4877 [syspll_d7
] = "syspll_d7",
4878 [tvdpll
] = "tvdpll",
4879 [tvdpll_d2
] = "tvdpll_d2",
4880 [tvdpll_d4
] = "tvdpll_d4",
4881 [univpll1_d2
] = "univpll1_d2",
4882 [univpll1_d4
] = "univpll1_d4",
4883 [univpll1_d8
] = "univpll1_d8",
4884 [univpll2_d2
] = "univpll2_d2",
4885 [univpll2_d4
] = "univpll2_d4",
4886 [univpll2_d8
] = "univpll2_d8",
4887 [univpll3_d2
] = "univpll3_d2",
4888 [univpll3_d4
] = "univpll3_d4",
4889 [univpll3_d8
] = "univpll3_d8",
4890 [univpll_d26
] = "univpll_d26",
4891 [univpll_d3
] = "univpll_d3",
4892 [univpll_d5
] = "univpll_d5",
4893 [vencpll_ck
] = "vencpll_ck",
4897 static struct mux_t g_mux
[] = {
4898 [MT_MUX_MM
] = {.ckgen_clk
= CKGEN_HF_FMM_CK
,
4910 [MT_MUX_DDRPHYCFG
] = {.ckgen_clk
= CKGEN_HF_FDDRPHYCFG_CK
,
4922 [MT_MUX_AXI
] = {.ckgen_clk
= CKGEN_HF_FAXI_CK
,
4934 [MT_MUX_CAMTG
] = {.ckgen_clk
= CKGEN_HF_FCAMTG_CK
,
4945 [MT_MUX_MFG
] = {.ckgen_clk
= CKGEN_HF_FMFG_CK
,
4957 [MT_MUX_VDEC
] = {.ckgen_clk
= CKGEN_HF_FVDEC_CK
,
4970 [MT_MUX_PWM
] = {.ckgen_clk
= CKGEN_F_FPWM_CK
,
4978 [MT_MUX_MSDC30_0
] = {.ckgen_clk
= CKGEN_HF_FMSDC30_0_CK
,
4988 [MT_MUX_USB20
] = {.ckgen_clk
= CKGEN_F_FUSB20_CK
,
4995 [MT_MUX_SPI
] = {.ckgen_clk
= CKGEN_HF_FSPI_CK
,
5004 [MT_MUX_UART
] = {.ckgen_clk
= CKGEN_F_FUART_CK
,
5010 [MT_MUX_AUDINTBUS
] = {.ckgen_clk
= CKGEN_HF_FAUD_INTBUS_CK
,
5020 [MT_MUX_AUDIO
] = {.ckgen_clk
= CKGEN_HF_FAUDIO_CK
,
5026 [MT_MUX_MSDC30_2
] = {.ckgen_clk
= CKGEN_HF_FMSDC30_2_CK
,
5036 [MT_MUX_MSDC30_1
] = {.ckgen_clk
= CKGEN_HF_FMSDC30_1_CK
,
5054 [MT_MUX_DPI0
] = {.ckgen_clk
= CKGEN_HF_FDPI0_CK
,
5074 [MT_MUX_PMICSPI
] = {.ckgen_clk
= CKGEN_HF_FPMICSPI_CK
,
5089 [MT_MUX_DPILVDS
] = {.ckgen_clk
= CKGEN_HF_FDPILVDS_CK
,
5133 [MT_MUX_ETH_50M
] = {.ckgen_clk
= CKGEN_HF_FETH_50M_CK
,
5145 [MT_MUX_NFI2X
] = {.ckgen_clk
= CKGEN_HF_FNFI2X_CK
,
5157 [MT_MUX_RTC
] = {.ckgen_clk
= CKGEN_F_FRTC_CK
,
5168 static void seq_printf_mux(struct seq_file
*s
, int mux_id
)
5174 const char *mux_clksrc
;
5176 struct clkmux
*mux
= id_to_mux(mux_id
);
5180 reg_value
= clk_readl(mux
->base_addr
);
5181 mux_value
= (reg_value
& mux
->sel_mask
) >> mux
->offset
;
5182 mux_pdn
= reg_value
& mux
->pdn_mask
;
5183 mux_en
= mux_pdn
? "off" : "ON";
5184 mux_clksrc
= clksrc_name
[g_mux
[mux_id
].clksrc
[mux_value
]];
5186 seq_printf(s
, "[ %2d, %2d, %3s, %-16s, %2d: %-12s ]\n",
5187 mux_id
, mux
->cnt
, mux_en
, mux
->name
, mux_value
, mux_clksrc
);
5191 #endif /* CLKMGR_8127 */
5194 static int mux_test_show(struct seq_file
*s
, void *v
)
5198 for (i
= 0; i
< NR_MUXS
; i
++)
5199 seq_printf_mux(s
, i
);
5200 #endif /* CLKMGR_8127 */
5202 seq_printf(s
, "********** mux register dump *********\n");
5203 seq_printf(s
, "[CLK_CFG_0] =0x%08x\n", clk_readl(CLK_CFG_0
));
5204 seq_printf(s
, "[CLK_CFG_1] =0x%08x\n", clk_readl(CLK_CFG_1
));
5205 seq_printf(s
, "[CLK_CFG_2] =0x%08x\n", clk_readl(CLK_CFG_2
));
5206 seq_printf(s
, "[CLK_CFG_3] =0x%08x\n", clk_readl(CLK_CFG_3
));
5207 seq_printf(s
, "[CLK_CFG_4] =0x%08x\n", clk_readl(CLK_CFG_4
));
5208 seq_printf(s
, "[CLK_CFG_5] =0x%08x\n", clk_readl(CLK_CFG_5
));
5209 seq_printf(s
, "[CLK_CFG_6] =0x%08x\n", clk_readl(CLK_CFG_6
));
5210 seq_printf(s
, "[CLK_CFG_8] =0x%08x\n", clk_readl(CLK_CFG_8
));
5211 seq_printf(s
, "[CLK_CFG_9] =0x%08x\n", clk_readl(CLK_CFG_9
));
5212 seq_printf(s
, "[CLK_CFG_10]=0x%08x\n", clk_readl(CLK_CFG_10
));
5213 seq_printf(s
, "[CLK_CFG_11]=0x%08x\n", clk_readl(CLK_CFG_11
));
5215 seq_printf(s
, "\n********** mux_test help *********\n");
5216 seq_printf(s
, "clkmux : echo clkmux mux_id val [mod_name] > /proc/clkmgr/mux_test\n");
5217 seq_printf(s
, "enable mux: echo enable mux_id [mod_name] > /proc/clkmgr/mux_test\n");
5218 seq_printf(s
, "disable mux: echo disable mux_id [mod_name] > /proc/clkmgr/mux_test\n");
5224 static int mux_test_open(struct inode
*inode
, struct file
*file
)
5226 return single_open(file
, mux_test_show
, NULL
);
5233 static int mux_test_write(struct file
*file
, const char *buffer
, size_t count
, loff_t
*data
)
5243 len
= (count
< (sizeof(desc
) - 1)) ? count
: (sizeof(desc
) - 1);
5245 if (copy_from_user(desc
, buffer
, len
))
5250 if (sscanf(desc
, "%s %d %d %s", cmd
, &mux_id
, &val
, mod_name
) == 4) {
5251 if (!strcmp(cmd
, "clkmux"))
5252 clkmux_sel(mux_id
, val
, mod_name
);
5253 } else if (sscanf(desc
, "%s %d %s", cmd
, &mux_id
, mod_name
) == 3) {
5254 if (!strcmp(cmd
, "enable"))
5255 enable_mux(mux_id
, mod_name
);
5256 else if (!strcmp(cmd
, "disable"))
5257 disable_mux(mux_id
, mod_name
);
5258 } else if (sscanf(desc
, "%s %d", cmd
, &mux_id
) == 2) {
5259 if (!strcmp(cmd
, "enable"))
5260 enable_mux(mux_id
, "mux_test");
5261 else if (!strcmp(cmd
, "disable"))
5262 disable_mux(mux_id
, "mux_test");
5269 #endif /* CLKMGR_8127 */
5272 static const struct file_operations mux_test_fops
= {
5273 .owner
= THIS_MODULE
,
5274 .write
= mux_test_write
,
5275 .open
= mux_test_open
,
5277 .llseek
= seq_lseek
,
5278 .release
= seq_release
5282 #ifdef CONFIG_CLKMGR_STAT
5285 static int mux_stat_show(struct seq_file
*s
, void *v
)
5288 struct list_head
*pos
;
5289 struct stat_node
*node
;
5292 seq_printf(s
, "********** mux stat dump **********\n");
5293 for (i
= 0; i
< NR_MUXS
; i
++) {
5296 seq_printf(s
, "[%02d][%-14s]cnt=%u", i
, mux
->name
, mux
->cnt
);
5298 list_for_each(pos
, &mux
->head
) {
5299 node
= list_entry(pos
, struct stat_node
, link
);
5300 seq_printf(s
, "\t(%s,%u,%u)", node
->name
, node
->cnt_on
, node
->cnt_off
);
5302 seq_printf(s
, "\n");
5305 seq_printf(s
, "\n********** mux_dump help **********\n");
5311 static int mux_stat_open(struct inode
*inode
, struct file
*file
)
5313 return single_open(file
, mux_stat_show
, NULL
);
5317 static const struct file_operations mux_stat_fops
= {
5318 .owner
= THIS_MODULE
,
5319 .open
= mux_stat_open
,
5321 .llseek
= seq_lseek
,
5322 .release
= seq_release
5329 static int clk_test_read(char *page
, char **start
, off_t off
,
5330 int count
, int *eof
, void *data
)
5337 unsigned int value
[2];
5340 p
+= sprintf(p
, "********** clk register dump **********\n");
5342 for (i
= 0; i
< NR_GRPS
; i
++) {
5343 name
= grp_get_name(i
);
5344 cnt
= grp_dump_regs(i
, value
);
5346 p
+= sprintf(p
, "[%02d][%-8s]=[0x%08x]\n", i
, name
, value
[0]);
5348 p
+= sprintf(p
, "[%02d][%-8s]=[0x%08x][0x%08x]\n", i
, name
, value
[0], value
[1]);
5351 p
+= sprintf(p
, "\n********** clk_test help **********\n");
5352 p
+= sprintf(p
, "enable clk: echo enable id [mod_name] > /proc/clkmgr/clk_test\n");
5353 p
+= sprintf(p
, "disable clk: echo disable id [mod_name] > /proc/clkmgr/clk_test\n");
5354 p
+= sprintf(p
, "read state: echo id > /proc/clkmgr/clk_test\n");
5356 *start
= page
+ off
;
5365 return len
< count
? len
: count
;
5368 static int clk_test_write(struct file
*file
, const char *buffer
,
5369 size_t count
, loff_t
*data
)
5379 len
= (count
< (sizeof(desc
) - 1)) ? count
: (sizeof(desc
) - 1);
5380 if (copy_from_user(desc
, buffer
, len
))
5385 if (sscanf(desc
, "%s %d %s", cmd
, &id
, mod_name
) == 3) {
5386 if (!strcmp(cmd
, "enable"))
5387 err
= enable_clock(id
, mod_name
);
5388 else if (!strcmp(cmd
, "disable"))
5389 err
= disable_clock(id
, mod_name
);
5390 } else if (sscanf(desc
, "%s %d", cmd
, &id
) == 2) {
5391 if (!strcmp(cmd
, "enable"))
5392 err
= enable_clock(id
, "pll_test");
5393 else if (!strcmp(cmd
, "disable"))
5394 err
= disable_clock(id
, "pll_test");
5395 } else if (sscanf(desc
, "%d", &id
) == 1)
5396 clk_info("clock %d is %s\n", id
, clock_is_on(id
) ? "on" : "off");
5404 static void *clk_test_seq_start(struct seq_file
*s
, loff_t
*pos
)
5408 if (*pos
>= NR_CLKS
+ 1)
5411 spos
= kmalloc(sizeof(loff_t
), GFP_KERNEL
);
5420 static void *clk_test_seq_next(struct seq_file
*s
, void *v
, loff_t
*pos
)
5422 loff_t
*spos
= (loff_t
*)v
;
5428 while (i
< NR_CLKS
&& clks
[++i
].name
== NULL
)
5435 if (*pos
>= NR_CLKS
+ 1)
5442 static void clk_test_seq_stop(struct seq_file
*s
, void *v
)
5448 static int clk_test_seq_show(struct seq_file
*s
, void *v
)
5450 loff_t
*spos
= (loff_t
*)v
;
5452 struct cg_clk
*clk
= &clks
[i
];
5455 seq_printf(s
, "[ %3lld,%3d,%4s, 0x%08X, %-29s, %-29s, %-8s, %-16s ]\n",
5458 clk
->state
? "ON" : "off",
5460 clk
->name
? clk
->name
: "",
5461 clk
->parent
? clk
->parent
->name
: "",
5462 clk
->grp
? clk
->grp
->name
: "",
5463 clk
->mux
? clk
->mux
->name
: "");
5465 const int PS
= 1280;
5469 clk_test_read(page
, &start
, 0, PS
, &eof
, NULL
);
5477 static const struct seq_operations clk_test_seq_ops
= {
5478 .start
= clk_test_seq_start
,
5479 .next
= clk_test_seq_next
,
5480 .stop
= clk_test_seq_stop
,
5481 .show
= clk_test_seq_show
5485 static int clk_test_open(struct inode
*inode
, struct file
*file
)
5487 return seq_open(file
, &clk_test_seq_ops
);
5491 static const struct file_operations clk_test_fops
= {
5492 .owner
= THIS_MODULE
,
5493 .write
= clk_test_write
,
5494 .open
= clk_test_open
,
5496 .llseek
= seq_lseek
,
5497 .release
= seq_release
5501 #endif /* CLKMGR_8127 */
5507 static void set_fmeter_divider(uint32_t k1
)
5509 uint32_t v
= k1
<< 24 | 0xFF << 16 | k1
<< 8 | k1
;
5510 clk_writel(CLK_MISC_CFG_1
, v
);
5514 static uint32_t fmeter_freq(enum FMETER_TYPE type
, int k1
, int clk
)
5519 uint32_t clk_cfg_reg
= (type
== CKGEN
) ? CLK_CFG_9
: CLK_CFG_8
;
5520 uint32_t cksw_mask
= (type
== CKGEN
) ? BITMASK(20 : 16) : BITMASK(13 : 8);
5521 uint32_t cksw_val
= (type
== CKGEN
) ? BITS(20 : 16, clk
) : BITS(13 : 8, clk
);
5522 uint32_t tri_bit
= (type
== CKGEN
) ? BIT(4) : BIT(0);
5523 uint32_t cnt_reg
= (type
== CKGEN
) ? CLK26CALI_2
: CLK26CALI_1
;
5524 uint32_t clk_misc_cfg_1
;
5525 uint32_t clk_cfg_val
;
5528 clk_setl(CLK26CALI_0
, BIT(7)); /* enable fmeter_en */
5530 clk_misc_cfg_1
= clk_readl(CLK_MISC_CFG_1
); /* backup CLK_MISC_CFG_1 value */
5531 set_fmeter_divider(k1
); /* set divider (0 = /1) */
5533 clk_cfg_val
= clk_readl(clk_cfg_reg
); /* backup clk_cfg_reg value */
5534 clk_writel_mask(clk_cfg_reg
, cksw_mask
, cksw_val
); /* select cksw */
5536 clk_setl(CLK26CALI_0
, tri_bit
); /* start fmeter */
5539 for (i
= 100; i
> 0 && clk_readl(CLK26CALI_0
) & tri_bit
; i
--)
5542 if (clk_readl(CLK26CALI_0
) & tri_bit
) {
5545 uint32_t cnt
= clk_readl(cnt_reg
) & 0xFFFF;
5546 freq
= (cnt
* 26000) * (k1
+ 1) / 1024; /* (KHz) ; freq = counter * 26M / 1024 */
5549 /* restore register settings */
5550 clk_writel(clk_cfg_reg
, clk_cfg_val
);
5551 clk_writel(CLK_MISC_CFG_1
, clk_misc_cfg_1
);
5557 static uint32_t measure_stable_fmeter_freq(enum FMETER_TYPE type
, int k1
, int clk
)
5559 const int diff_threshold
= 10;
5560 uint32_t last_freq
= 0;
5561 uint32_t freq
= fmeter_freq(type
, k1
, clk
);
5562 uint32_t maxfreq
= max(freq
, last_freq
);
5564 while (maxfreq
> 0 && ABS_DIFF(freq
, last_freq
) * 100 / maxfreq
> diff_threshold
) {
5566 freq
= fmeter_freq(type
, k1
, clk
);
5567 maxfreq
= max(freq
, last_freq
);
5574 uint32_t measure_abist_freq(enum ABIST_CLK clk
)
5576 return measure_stable_fmeter_freq(ABIST
, 0, clk
);
5578 EXPORT_SYMBOL(measure_abist_freq
);
5581 uint32_t measure_ckgen_freq(enum CKGEN_CLK clk
)
5583 return measure_stable_fmeter_freq(CKGEN
, 0, clk
);
5585 EXPORT_SYMBOL(measure_ckgen_freq
);
5588 static void measure_abist_clock(enum ABIST_CLK clk
, struct seq_file
*s
)
5590 uint32_t freq
= measure_abist_freq(clk
);
5591 seq_printf(s
, "%2d: %-25s %7u\n", clk
, ABIST_CLK_NAME
[clk
], freq
);
5595 static void measure_ckgen_clock(enum CKGEN_CLK clk
, struct seq_file
*s
)
5597 uint32_t freq
= measure_ckgen_freq(clk
);
5598 seq_printf(s
, "%2d: %-25s %7u\n", clk
, CKGEN_CLK_NAME
[clk
], freq
);
5602 static int fmeter_show(struct seq_file
*s
, void *v
)
5604 enum ABIST_CLK abist_clks
[] = {
5605 ABIST_AD_MAIN_H546M_CK
,
5606 ABIST_AD_MAIN_H364M_CK
,
5607 ABIST_AD_MAIN_H218P4M_CK
,
5608 ABIST_AD_MAIN_H156M_CK
,
5609 ABIST_AD_UNIV_624M_CK
,
5610 ABIST_AD_UNIV_416M_CK
,
5611 ABIST_AD_UNIV_249P6M_CK
,
5612 ABIST_AD_UNIV_178P3M_CK
,
5613 ABIST_AD_UNIV_48M_CK
,
5614 ABIST_AD_USB_48M_CK
,
5616 ABIST_AD_MSDCPLL_CK
,
5619 ABIST_AD_MEMPLL2_CKOUT0_PRE_ISO
,
5620 ABIST_AD_MCUPLL1_H481M_CK
,
5621 ABIST_AD_MDPLL1_416M_CK
,
5625 ABIST_AD_SYS_26M_CK
,
5626 ABIST_AD_VENCPLL_CK
,
5627 ABIST_AD_MIPI_26M_CK
,
5628 ABIST_AD_MEM_26M_CK
,
5629 ABIST_AD_PLLGP_TST_CK
,
5630 ABIST_AD_DSI0_LNTC_DSICLK
,
5631 ABIST_AD_MPPLL_TST_CK
,
5632 ABIST_ARMPLL_OCC_MON
,
5633 ABIST_AD_MEM2MIPI_26M_CK
,
5634 ABIST_AD_MEMPLL_MONCLK
,
5635 ABIST_AD_MEMPLL2_MONCLK
,
5636 ABIST_AD_MEMPLL3_MONCLK
,
5637 ABIST_AD_MEMPLL4_MONCLK
,
5638 ABIST_AD_MEMPLL_REFCLK
,
5639 ABIST_AD_MEMPLL_FBCLK
,
5640 ABIST_AD_MEMPLL2_REFCLK
,
5641 ABIST_AD_MEMPLL2_FBCLK
,
5642 ABIST_AD_MEMPLL3_REFCLK
,
5643 ABIST_AD_MEMPLL3_FBCLK
,
5644 ABIST_AD_MEMPLL4_REFCLK
,
5645 ABIST_AD_MEMPLL4_FBCLK
,
5646 ABIST_AD_MEMPLL_TSTDIV2_CK
,
5647 ABIST_AD_LVDSPLL_CK
,
5648 ABIST_AD_LVDSTX_MONCLK
,
5649 ABIST_AD_HDMITX_MONCLK
,
5650 ABIST_AD_USB20_C240M
,
5651 ABIST_AD_USB20_C240M_1P
,
5656 ABIST_AD_LVDSPLL_ETH_CK
,
5659 enum CKGEN_CLK ckgen_clks
[] = {
5663 CKGEN_HF_FDDRPHYCFG_CK
,
5672 CKGEN_HF_FMSDC30_0_CK
,
5673 CKGEN_HF_FMSDC30_1_CK
,
5674 CKGEN_HF_FMSDC30_2_CK
,
5676 CKGEN_HF_FAUD_INTBUS_CK
,
5677 CKGEN_HF_FPMICSPI_CK
,
5680 CKGEN_F_F32K_MD1_CK
,
5681 CKGEN_F_FRTC_CONN_CK
,
5682 CKGEN_HF_FETH_50M_CK
,
5683 CKGEN_HD_HAXI_NLI_CK
,
5684 CKGEN_HD_QAXIDCM_CK
,
5687 CKGEN_F_FCKBUS_CK_SCAN
,
5688 CKGEN_F_FCKRTC_CK_SCAN
,
5689 CKGEN_HF_FDPILVDS_CK
,
5694 uint32_t old_pll_hp_con0
= clk_readl(PLL_HP_CON0
);
5695 clk_writel(PLL_HP_CON0
, 0x0); /* disable PLL hopping */
5697 seq_puts(s
, "abist:\n");
5699 for (i
= 0; i
< ARRAY_SIZE(abist_clks
); i
++)
5700 measure_abist_clock(abist_clks
[i
], s
);
5702 seq_puts(s
, "ckgen:\n");
5704 for (i
= 0; i
< ARRAY_SIZE(ckgen_clks
); i
++)
5705 measure_ckgen_clock(ckgen_clks
[i
], s
);
5707 /* restore old setting */
5708 clk_writel(PLL_HP_CON0
, old_pll_hp_con0
);
5714 static int fmeter_open(struct inode
*inode
, struct file
*file
)
5716 return single_open(file
, fmeter_show
, NULL
);
5720 static const struct file_operations fmeter_fops
= {
5721 .owner
= THIS_MODULE
,
5722 .open
= fmeter_open
,
5724 .llseek
= seq_lseek
,
5725 .release
= single_release
,
5729 #endif /* CLKMGR_8127 */
5732 #ifdef CONFIG_CLKMGR_STAT
5735 static int clk_stat_show(struct seq_file
*s
, void *v
)
5738 struct list_head
*pos
;
5739 struct stat_node
*node
;
5743 seq_printf(s
, "\n********** clk stat dump **********\n");
5744 for (i
= 0; i
< NR_CLKS
; i
++) {
5748 seq_printf(s
, "\n*****[%02d][%-8s]*****\n", grp
, grp_get_name(grp
));
5751 if (!clk
|| !clk
->grp
|| !clk
->ops
->check_validity(clk
))
5754 skip
= (clk
->cnt
== 0) && (clk
->state
== 0) && list_empty(&clk
->head
);
5758 seq_printf(s
, "[%02d]state=%u, cnt=%u", offset
, clk
->state
, clk
->cnt
);
5759 list_for_each(pos
, &clk
->head
) {
5760 node
= list_entry(pos
, struct stat_node
, link
);
5761 seq_printf(s
, "\t(%s,%u,%u)", node
->name
, node
->cnt_on
, node
->cnt_off
);
5763 seq_printf(s
, "\n");
5770 static int clk_stat_open(struct inode
*inode
, struct file
*file
)
5772 return single_open(file
, clk_stat_show
, NULL
);
5776 static const struct file_operations clk_stat_fops
= {
5777 .owner
= THIS_MODULE
,
5778 .open
= clk_stat_open
,
5780 .llseek
= seq_lseek
,
5781 .release
= seq_release
5788 static int clk_force_on_show(struct seq_file
*s
, void *v
)
5793 seq_printf(s
, "********** clk force on info dump **********\n");
5794 for (i
= 0; i
< NR_CLKS
; i
++) {
5796 if (clk
->force_on
) {
5797 seq_printf(s
, "clock %d (0x%08x @ %s) is force on\n", i
,
5798 clk
->mask
, clk
->grp
->name
);
5802 seq_printf(s
, "\n********** clk_force_on help **********\n");
5803 seq_printf(s
, "set clk force on: echo set id > /proc/clkmgr/clk_force_on\n");
5804 seq_printf(s
, "clr clk force on: echo clr id > /proc/clkmgr/clk_force_on\n");
5810 static int clk_force_on_open(struct inode
*inode
, struct file
*file
)
5812 return single_open(file
, clk_force_on_show
, NULL
);
5816 static int clk_force_on_write(struct file
*file
, const char *buffer
, size_t count
, loff_t
*data
)
5824 len
= (count
< (sizeof(desc
) - 1)) ? count
: (sizeof(desc
) - 1);
5825 if (copy_from_user(desc
, buffer
, len
))
5830 if (sscanf(desc
, "%s %d", cmd
, &id
) == 2) {
5831 if (!strcmp(cmd
, "set"))
5832 clk_set_force_on(id
);
5833 else if (!strcmp(cmd
, "clr"))
5834 clk_clr_force_on(id
);
5841 static const struct file_operations clk_force_on_fops
= {
5842 .owner
= THIS_MODULE
,
5843 .write
= clk_force_on_write
,
5844 .open
= clk_force_on_open
,
5846 .llseek
= seq_lseek
,
5847 .release
= seq_release
5851 static int udelay_test_show(struct seq_file
*s
, void *v
)
5853 seq_printf(s
, "\n********** udelay_test help **********\n");
5854 seq_printf(s
, "test udelay: echo delay > /proc/clkmgr/udelay_test\n");
5860 static int udelay_test_open(struct inode
*inode
, struct file
*file
)
5862 return single_open(file
, udelay_test_show
, NULL
);
5866 static int udelay_test_write(struct file
*file
, const char *buffer
, size_t count
, loff_t
*data
)
5872 unsigned int pre
, pos
;
5874 len
= (count
< (sizeof(desc
) - 1)) ? count
: (sizeof(desc
) - 1);
5875 if (copy_from_user(desc
, buffer
, len
))
5880 if (sscanf(desc
, "%u", &delay
) == 1) {
5881 pre
= clk_readl(0xF0008028);
5883 pos
= clk_readl(0xF0008028);
5884 clk_info("udelay(%u) test: pre=0x%08x, pos=0x%08x, delta=%u\n",
5885 delay
, pre
, pos
, pos
-pre
);
5892 static const struct file_operations udelay_test_fops
= {
5893 .owner
= THIS_MODULE
,
5894 .write
= udelay_test_write
,
5895 .open
= udelay_test_open
,
5897 .llseek
= seq_lseek
,
5898 .release
= seq_release
5902 void mt_clkmgr_debug_init(void)
5904 struct proc_dir_entry
*entry
;
5905 struct proc_dir_entry
*clkmgr_dir
;
5907 clkmgr_dir
= proc_mkdir("clkmgr", NULL
);
5909 clk_err("[%s]: fail to mkdir /proc/clkmgr\n", __func__
);
5913 entry
= proc_create("pll_test", 00640, clkmgr_dir
, &pll_test_fops
);
5914 entry
= proc_create("pll_fsel", 00640, clkmgr_dir
, &pll_fsel_fops
);
5916 #ifdef CONFIG_CLKMGR_STAT
5917 entry
= proc_create("pll_stat", 00440, clkmgr_dir
, &pll_stat_fops
);
5920 entry
= proc_create("subsys_test", 00640, clkmgr_dir
, &subsys_test_fops
);
5922 #ifdef CONFIG_CLKMGR_STAT
5923 entry
= proc_create("subsys_stat", 00440, clkmgr_dir
, &subsys_stat_fops
);
5926 entry
= proc_create("mux_test", 00640, clkmgr_dir
, &mux_test_fops
);
5928 #ifdef CONFIG_CLKMGR_STAT
5929 entry
= proc_create("mux_stat", 00440, clkmgr_dir
, &mux_stat_fops
);
5932 entry
= proc_create("clk_test", 00640, clkmgr_dir
, &clk_test_fops
);
5934 #ifdef CONFIG_CLKMGR_STAT
5935 entry
= proc_create("clk_stat", 00440, clkmgr_dir
, &clk_stat_fops
);
5938 entry
= proc_create("clk_force_on", 00640, clkmgr_dir
, &clk_force_on_fops
);
5939 entry
= proc_create("udelay_test", 00640, clkmgr_dir
, &udelay_test_fops
);
5942 entry
= proc_create("fmeter", 00640, clkmgr_dir
, &fmeter_fops
);
5943 #endif /* CLKMGR_8127 */
5947 /***********************************
5949 ************************************/
5950 #ifdef CONFIG_HAS_EARLYSUSPEND
5951 static void clkmgr_early_suspend(struct early_suspend
*h
)
5953 clk_info("[%s]: Dump Top MUX register, CLK_CFG_0=0x%x, CLK_CFG_1=0x%x, CLK_CFG_2=0x%x, CLK_CFG_3=0x%x\n",
5954 __func__
, clk_readl(CLK_CFG_0
), clk_readl(CLK_CFG_1
), clk_readl(CLK_CFG_2
), clk_readl(CLK_CFG_3
));
5958 static void clkmgr_late_resume(struct early_suspend
*h
)
5960 clk_info("[%s]: Dump Top MUX register, CLK_CFG_0=0x%x, CLK_CFG_1=0x%x, CLK_CFG_2=0x%x, CLK_CFG_3=0x%x\n",
5961 __func__
, clk_readl(CLK_CFG_0
), clk_readl(CLK_CFG_1
), clk_readl(CLK_CFG_2
), clk_readl(CLK_CFG_3
));
5966 static struct early_suspend mt_clkmgr_early_suspend_handler
= {
5967 .level
= EARLY_SUSPEND_LEVEL_DISABLE_FB
+ 250,
5968 .suspend
= clkmgr_early_suspend
,
5969 .resume
= clkmgr_late_resume
,
5971 #endif /* CONFIG_HAS_EARLYSUSPEND */
5973 struct platform_device CLK_helper_device
= {
5979 int CLK_pm_restore_noirq(struct device
*device
)
5983 sys
= &syss
[SYS_DIS
];
5984 sys
->state
= sys
->ops
->get_state(sys
);
5986 muxs
[MT_MUX_MM
].cnt
= 1;
5987 plls
[VENCPLL
].cnt
= 1;
5989 clk_set_force_on_locked(&clks
[MT_CG_DISP0_SMI_LARB0
]);
5990 clk_set_force_on_locked(&clks
[MT_CG_DISP0_SMI_COMMON
]);
5992 clk_info("CLK_pm_restore_noirq\n");
5997 static const struct dev_pm_ops CLK_helper_pm_ops
= {
5998 .restore_noirq
= CLK_pm_restore_noirq
,
6001 static struct platform_driver CLK_helper_driver
= {
6005 .pm
= &CLK_helper_pm_ops
,
6007 .owner
= THIS_MODULE
,
6011 static int mt_clkmgr_debug_bringup_init(void)
6015 #if defined(CONFIG_CLKMGR_BRINGUP) || defined(CONFIG_MTK_LDVT)
6016 mt_clkmgr_bringup_init();
6019 mt_clkmgr_debug_init();
6021 #ifdef CONFIG_HAS_EARLYSUSPEND
6022 register_early_suspend(&mt_clkmgr_early_suspend_handler
);
6025 ret
= platform_device_register(&CLK_helper_device
);
6027 clk_warn("CLK_helper_device register fail(%d)\n", ret
);
6031 ret
= platform_driver_register(&CLK_helper_driver
);
6033 clk_warn("CLK_helper_driver register fail(%d)\n", ret
);
6039 static int __init
mt_clkmgr_late_init(void)
6044 module_init(mt_clkmgr_debug_bringup_init
);
6045 late_initcall(mt_clkmgr_late_init
);
6048 /*************CLKM****************/
6049 void CLKM_32K(bool flag
)
6051 unsigned long flags
;
6056 clk_setl(CLK_CFG_10
, 0x00000002); /* CLK_CKMON1_SEL use 2:rtc32k_ck_i */
6059 clk_clrl(CLK_CFG_10
, 0x00000002);
6061 clkmgr_unlock(flags
);
6064 EXPORT_SYMBOL(CLKM_32K
);
6067 int CLK_Monitor(enum ckmon_sel ckmon
, enum monitor_clk_sel sel
, int div
)
6069 unsigned long flags
;
6070 unsigned int ckmon_shift
= 0;
6073 if (div
> 255 || ckmon
== 0) {
6074 clk_info("CLK_Monitor error parameter\n");
6082 else if (ckmon
== 2)
6084 else if (ckmon
== 3)
6087 temp
= clk_readl(CLK_CFG_10
);
6088 temp
= temp
& (~(0xf << ckmon_shift
));
6089 temp
= temp
| ((sel
& 0xf) << ckmon_shift
);
6090 clk_writel(CLK_CFG_10
, temp
);
6092 temp
= clk_readl(CLK_CFG_11
);
6093 temp
= temp
& (~(0xff << ckmon_shift
));
6094 temp
= temp
| ((div
& 0xff) << ckmon_shift
);
6095 clk_writel(CLK_CFG_11
, temp
);
6097 clk_info("CLK_Monitor Reg: CLK_CFG_10=0x%x, CLK_CFG_11=0x%x\n",
6098 clk_readl(CLK_CFG_10
), clk_readl(CLK_CFG_11
));
6100 clkmgr_unlock(flags
);
6103 EXPORT_SYMBOL(CLK_Monitor
);
6109 int CLK_Monitor_0(enum ckmon_sel ckmon
, enum monitor_clk_sel_0 sel
, int div
)
6111 unsigned long flags
;
6114 if (div
> 255 || ckmon
> 0) {
6115 clk_info("CLK_Monitor_0 error parameter\n");
6121 temp
= clk_readl(CLK26CALI_0
);
6122 clk_writel(CLK26CALI_0
, temp
| 0x80);
6124 clk_writel(CLK_CFG_8
, sel
<< 8);
6126 temp
= clk_readl(CLK_MISC_CFG_1
);
6127 clk_writel(CLK_MISC_CFG_1
, div
& 0xff);
6129 clk_info("CLK_Monitor_0 Reg: CLK26CALI_0=0x%08x, CLK_CFG_8=0x%08x, CLK_MISC_CFG_1=0x%08x\n",
6130 clk_readl(CLK26CALI_0
), clk_readl(CLK_CFG_8
), clk_readl(CLK_MISC_CFG_1
));
6132 clkmgr_unlock(flags
);
6135 EXPORT_SYMBOL(CLK_Monitor_0
);
6138 #endif /* CLKMGR_CLKM0 */