6 #define MTK_MAU_MAJOR_NUMBER 190
8 #define MTK_IOW(num, dtype) _IOW('O', num, dtype)
9 #define MTK_IOR(num, dtype) _IOR('O', num, dtype)
10 #define MTK_IOWR(num, dtype) _IOWR('O', num, dtype)
11 #define MTK_IO(num) _IO('O', num)
13 // --------------------------------------------------------------------------
14 #define MTK_CONFIG_MM_MAU MTK_IOW(10, unsigned long)
15 #define MTK_CONFIG_MM_MPU MTK_IOW(11, unsigned long)
21 MAU0_MASK_ROT_DMA0_OUT0,
22 MAU0_MASK_ROT_DMA1_OUT0,
23 MAU0_MASK_TV_ROT_OUT0,
28 MAU0_MASK_R_DMA0_OUT0,
29 MAU0_MASK_R_DMA0_OUT1,
30 MAU0_MASK_R_DMA0_OUT2,
33 MAU0_MASK_JPGDMA_R, // 15
34 MAU0_MASK_JPGDMA_W, // 15
35 MAU0_MASK_ROT_DMA0_OUT1,// 15
36 MAU0_MASK_ROT_DMA0_OUT2,// 15
37 MAU0_MASK_ROT_DMA1_OUT1,// 15
38 MAU0_MASK_ROT_DMA1_OUT2,// 15
39 MAU0_MASK_TV_ROT_OUT1, // no use
40 MAU0_MASK_TV_ROT_OUT2, // no use
41 MAU0_MASK_R_DMA0_OUT3, // no use
42 MAU0_MASK_JPG_DEC1, // 15
46 MAU1_MASK_RSV_0 = MAU0_MASK_ALL,
47 MAU1_MASK_OVL_MSK, // 1
50 MAU1_MASK_ROT_DMA2_OUT0,
51 MAU1_MASK_ROT_DMA3_OUT0,
52 MAU1_MASK_ROT_DMA4_OUT0,
56 MAU1_MASK_R_DMA1_OUT0,
57 MAU1_MASK_R_DMA1_OUT1,
58 MAU1_MASK_R_DMA1_OUT2,
63 MAU1_MASK_ROT_DMA2_OUT1, //20
64 MAU1_MASK_ROT_DMA2_OUT2, //20
65 MAU1_MASK_ROT_DMA3_OUT1, //20
66 MAU1_MASK_ROT_DMA3_OUT2, //20
67 MAU1_MASK_ROT_DMA4_OUT1, //20
68 MAU1_MASK_ROT_DMA4_OUT2, //20
69 MAU1_MASK_GREQ_BLKW, //17
70 MAU1_MASK_GREQ_BLKR, //18
71 MAU1_MASK_TVC_PFH, //no use
72 MAU1_MASK_TVC_RESZ, //no use
73 MAU1_MASK_R_DMA1_OUT3, //no use
78 MAU2_MASK_RSV_0 = MAU1_MASK_ALL,
89 MAU3_MASK_RSV_0 = MAU2_MASK_ALL,
95 MAU_MASK_ALL = MAU3_MASK_ALL
103 MAU0_MASK_ROT_DMA0_OUT0
,
104 MAU0_MASK_ROT_DMA1_OUT0
,
105 MAU0_MASK_TV_ROT_OUT0
,
110 MAU0_MASK_R_DMA0_OUT0
,
111 MAU0_MASK_R_DMA0_OUT1
,
112 MAU0_MASK_R_DMA0_OUT2
,
115 MAU0_MASK_JPGDMA_R
, // 15
116 MAU0_MASK_JPGDMA_W
, // 15
117 MAU0_MASK_ROT_DMA0_OUT1
,// 15
118 MAU0_MASK_ROT_DMA0_OUT2
,// 15
119 MAU0_MASK_ROT_DMA1_OUT1
,// 15
120 MAU0_MASK_ROT_DMA1_OUT2
,// 15
121 MAU0_MASK_TV_ROT_OUT1
, // no use
122 MAU0_MASK_TV_ROT_OUT2
, // no use
123 MAU0_MASK_R_DMA0_OUT3
, // no use
124 MAU0_MASK_JPG_DEC1
, // 15
131 MAU1_MASK_OVL_MSK
, // 1
134 MAU1_MASK_ROT_DMA2_OUT0
,
135 MAU1_MASK_ROT_DMA3_OUT0
,
136 MAU1_MASK_ROT_DMA4_OUT0
,
140 MAU1_MASK_R_DMA1_OUT0
,
141 MAU1_MASK_R_DMA1_OUT1
,
142 MAU1_MASK_R_DMA1_OUT2
,
147 MAU1_MASK_ROT_DMA2_OUT1
, //20
148 MAU1_MASK_ROT_DMA2_OUT2
, //20
149 MAU1_MASK_ROT_DMA3_OUT1
, //20
150 MAU1_MASK_ROT_DMA3_OUT2
, //20
151 MAU1_MASK_ROT_DMA4_OUT1
, //20
152 MAU1_MASK_ROT_DMA4_OUT2
, //20
153 MAU1_MASK_GREQ_BLKW
, //17
154 MAU1_MASK_GREQ_BLKR
, //18
155 MAU1_MASK_TVC_PFH
, //no use
156 MAU1_MASK_TVC_RESZ
, //no use
157 MAU1_MASK_R_DMA1_OUT3
, //no use
167 MAU2_MASK_VENC_BSDMA
,
171 MAU2_MASK_VENC_POST0
,
172 MAU2_MASK_VENC_POST1
,
193 MAU_PA
, //phsical address
194 MAU_MVA
//m4u virtual addrss
210 MTK_MAU_ENTRY EntryID
; // Entry ID 0~2
213 unsigned int InvalidMasterLARB0
; // one bit represent one master, 1: allow, 0: not allow, usd by MAU and MPU
214 unsigned int InvalidMasterLARB1
; // one bit represent one master, 1: allow, 0: not allow, only used by MPU
215 unsigned int InvalidMasterLARB2
;
216 unsigned int InvalidMasterLARB3
;
217 unsigned int ReadEn
; // check read transaction, 1:enable, 0:disable
218 unsigned int WriteEn
; // check write transaction, 1:enable, 0:disable
219 unsigned int StartAddr
; // start address
220 unsigned int EndAddr
; // end address
242 int MAU_Config(MTK_MAU_CONFIG
* pMauConf
);
243 void MAU_PrintStatus(char* buf
, unsigned int buf_len
, unsigned int* num
);
244 void MAU_DumpReg(MTK_MAU_ID mauID
);
245 void MAU_LogSwitch(bool enable
);
246 void MAU_BackupReg(MTK_MAU_ID mauID
);
247 void MAU_RestoreReg(MTK_MAU_ID mauID
);
248 int MAU_get_port_with_m4u(unsigned int start_addr
, unsigned int end_addr
);
250 int MAU0_PowerOn(void);
251 int MAU0_PowerOff(void);
252 int MAU1_PowerOn(void);
253 int MAU1_PowerOff(void);
254 int MAU2_PowerOn(void);
255 int MAU2_PowerOff(void);
256 int MAU3_PowerOn(void);
257 int MAU3_PowerOff(void);