arch/arm/mach-mt8127/include/mach/mt_smi.h

   1 #ifndef _MTK_MAU_H_
   2 #define _MTK_MAU_H_
   3
   4 #define MTK_SMI_MAJOR_NUMBER 190
   5
   6 #define MTK_IOW(num, dtype)     _IOW('O', num, dtype)
   7 #define MTK_IOR(num, dtype)     _IOR('O', num, dtype)
   8 #define MTK_IOWR(num, dtype)    _IOWR('O', num, dtype)
   9 #define MTK_IO(num)             _IO('O', num)
  10
  11 // --------------------------------------------------------------------------
  12 #define MTK_CONFIG_MM_MAU       MTK_IOW(10, unsigned long)
  13
  14
  15 typedef struct
  16 {
  17     int larb;               //0~4: the larb you want to monitor
  18     int entry;          //0~2: the mau entry to use
  19         unsigned int port_msk;  //port mask to be monitored
  20     int virt;        // 1: monitor va (this port is using m4u);  0: monitor pa (this port is not using m4u)
  21         int monitor_read;     // monitor read transaction 1-enable, 0-disable
  22         int monitor_write;    //monitor write transaction 1-enable, 0-disable
  23         unsigned int start;         //start address to monitor
  24         unsigned int end;       //end address to monitor
  25 } MTK_MAU_CONFIG;
  26
  27
  28 int mau_config(MTK_MAU_CONFIG* pMauConf);
  29 int mau_dump_status(int larb);
  30
  31
  32 //---------------------------------------------------------------------------
  33 typedef enum
  34 {
  35     SMI_BWC_SCEN_NORMAL,
  36     SMI_BWC_SCEN_VR,
  37     SMI_BWC_SCEN_SWDEC_VP,
  38     SMI_BWC_SCEN_VP,
  39     SMI_BWC_SCEN_VR_SLOW,
  40     SMI_BWC_SCEN_MM_GPU,
  41     SMI_BWC_SCEN_WFD,
  42     SMI_BWC_SCEN_VENC,
  43     SMI_BWC_SCEN_CNT
  44 } MTK_SMI_BWC_SCEN;
  45
  46 typedef struct
  47 {
  48     MTK_SMI_BWC_SCEN    scenario;
  49     int                 b_on_off; //0 : exit this scenario , 1 : enter this scenario
  50 } MTK_SMI_BWC_CONFIG;
  51
  52 typedef struct
  53 {
  54     unsigned int*       hwc_max_pixel; //0 : exit this scenario , 1 : enter this scenario
  55 } MTK_SMI_BWC_STATE;
  56
  57 typedef struct
  58 {
  59     unsigned int       address;
  60     unsigned int       value;
  61 } MTK_SMI_BWC_REGISTER_SET;
  62
  63 typedef struct
  64 {
  65     unsigned int       address;
  66     unsigned int*      return_address; //0 : exit this scenario , 1 : enter this scenario
  67 } MTK_SMI_BWC_REGISTER_GET;
  68
  69 #define MTK_IOC_SPC_CONFIG          MTK_IOW(20, unsigned long)
  70 #define MTK_IOC_SPC_DUMP_REG        MTK_IOW(21, unsigned long)
  71 #define MTK_IOC_SPC_DUMP_STA        MTK_IOW(22, unsigned long)
  72 #define MTK_IOC_SPC_CMD             MTK_IOW(23, unsigned long)
  73 #define MTK_IOC_SMI_BWC_CONFIG      MTK_IOW(24, MTK_SMI_BWC_CONFIG)
  74 #define MTK_IOC_SMI_BWC_STATE       MTK_IOWR(25, MTK_SMI_BWC_STATE)
  75 #define MTK_IOC_SMI_BWC_REGISTER_SET    MTK_IOWR(26, MTK_SMI_BWC_REGISTER_SET)
  76 #define MTK_IOC_SMI_BWC_REGISTER_GET    MTK_IOWR(27, MTK_SMI_BWC_REGISTER_GET)
  77
  78
  79
  80 typedef enum {
  81     SPC_PROT_NO_PROT = 0,
  82     SPC_PROT_SEC_RW_ONLY,
  83     SPC_PROT_SEC_RW_NONSEC_R,
  84     SPC_PROT_NO_ACCESS,
  85
  86 }SPC_PROT_T;
  87
  88
  89 typedef struct
  90 {
  91     SPC_PROT_T domain_0_prot;
  92     SPC_PROT_T domain_1_prot;
  93     SPC_PROT_T domain_2_prot;
  94     SPC_PROT_T domain_3_prot;
  95         unsigned int start;         //start address to monitor
  96         unsigned int end;       //end address to monitor
  97 } MTK_SPC_CONFIG;
  98
  99 void spc_config(MTK_SPC_CONFIG* pCfg);
 100 unsigned int spc_status_check(void);
 101 unsigned int spc_dump_reg(void);
 102 unsigned int spc_register_isr(void* dev);
 103 unsigned int spc_clear_irq(void);
 104 int spc_test(int code);
 105 int MTK_SPC_Init(void* dev);
 106
 107
 108 #endif
 109