arch/arm/mach-mt8127/include/mach/mt_pwm_hal.h

   1 /*******************************************************************************
   2 * mt6575_pwm.h PWM Drvier
   3 *
   4 * Copyright (c) 2010, Media Teck.inc
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public Licence,
   8 * version 2, as publish by the Free Software Foundation.
   9 *
  10 * This program is distributed and in hope it will be useful, but WITHOUT
  11 * ANY WARRNTY; without even the implied warranty of MERCHANTABITLITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13 * more details.
  14 *
  15 *
  16 ********************************************************************************
  17 * Author : Chagnlei Gao (changlei.gao@mediatek.com)
  18 ********************************************************************************
  19 */
  20
  21 #ifndef __MT_PWM_HAL_H__
  22 #define __MT_PWM_HAL_H__
  23
  24 #include <mach/mt_reg_base.h>
  25 #include <mach/mt_typedefs.h>
  26 #include <mach/mt_clkmgr.h>
  27 #include <mach/mt_gpio.h>
  28 #include <mach/irqs.h>
  29 #include <mach/upmu_common.h>
  30 #include <mach/sync_write.h>
  31
  32 /**********************************
  33 * Global enum data
  34 ***********************************/
  35 enum PWN_NO{
  36         PWM_MIN,
  37         PWM1 = PWM_MIN,
  38         PWM2,
  39         PWM3,
  40         PWM4,
  41         PWM5,
  42         PWM_NUM,
  43         PWM_MAX=PWM_NUM
  44 };
  45
  46 enum TEST_SEL_BIT{
  47         TEST_SEL_FALSE,
  48         TEST_SEL_TRUE
  49 };
  50
  51 enum PWM_CON_MODE_BIT{
  52         PERIOD,
  53         RAND
  54 };
  55
  56 enum PWM_CON_SRCSEL_BIT{
  57         PWM_FIFO,
  58         MEMORY
  59 };
  60
  61 enum PWM_CON_IDLE_BIT{
  62         IDLE_FALSE,
  63         IDLE_TRUE,
  64         IDLE_MAX
  65 };
  66
  67 enum  PWM_CON_GUARD_BIT{
  68         GUARD_FALSE,
  69         GUARD_TRUE,
  70         GUARD_MAX
  71 };
  72
  73 enum OLD_MODE_BIT{
  74         OLDMODE_DISABLE,
  75         OLDMODE_ENABLE
  76 };
  77
  78 enum PWM_BUF_VALID_BIT{
  79         BUF0_VALID,
  80         BUF0_EN_VALID,
  81         BUF1_VALID,
  82         BUF1_EN_VALID,
  83         BUF_EN_MAX
  84 };
  85
  86 enum CLOCK_SRC{
  87         CLK_BLOCK,
  88         CLK_BLOCK_BY_1625_OR_32K
  89 };
  90
  91 enum PWM_CLK_DIV{
  92         CLK_DIV_MIN,
  93         CLK_DIV1 = CLK_DIV_MIN,
  94         CLK_DIV2,
  95         CLK_DIV4,
  96         CLK_DIV8,
  97         CLK_DIV16,
  98         CLK_DIV32,
  99         CLK_DIV64,
 100         CLK_DIV128,
 101         CLK_DIV_MAX
 102 };
 103
 104 enum PWM_INT_ENABLE_BITS{
 105         PWM1_INT_FINISH_EN,
 106         PWM1_INT_UNDERFLOW_EN,
 107         PWM2_INT_FINISH_EN,
 108         PWM2_INT_UNDERFLOW_EN,
 109         PWM3_INT_FINISH_EN,
 110         PWM3_INT_UNDERFLOW_EN,
 111         PWM4_INT_FINISH_EN,
 112         PWM4_INT_UNDERFLOW_EN,
 113         PWM5_INT_FINISH_EN,
 114         PWM5_INT_UNDERFLOW_EN,
 115         PWM_INT_ENABLE_BITS_MAX,
 116 };
 117
 118 enum PWM_INT_STATUS_BITS{
 119         PWM1_INT_FINISH_ST,
 120         PWM1_INT_UNDERFLOW_ST,
 121         PWM2_INT_FINISH_ST,
 122         PWM2_INT_UNDERFLOW_ST,
 123         PWM3_INT_FINISH_ST,
 124         PWM3_INT_UNDERFLOW_ST,
 125         PWM4_INT_FINISH_ST,
 126         PWM4_INT_UNDERFLOW_ST,
 127         PWM5_INT_FINISH_ST,
 128         PWM5_INT_UNDERFLOW_ST,
 129         PWM_INT_STATUS_BITS_MAX,
 130 };
 131
 132 enum PWM_INT_ACK_BITS{
 133         PWM1_INT_FINISH_ACK,
 134         PWM1_INT_UNDERFLOW_ACK,
 135         PWM2_INT_FINISH_ACK,
 136         PWM2_INT_UNDERFLOW_ACK,
 137         PWM3_INT_FINISH_ACK,
 138         PWM3_INT_UNDERFLOW_ACK,
 139         PWM4_INT_FINISH_ACK,
 140         PWM4_INT_UNDERFLOW_ACK,
 141         PWM5_INT_FINISH_ACK,
 142         PWM5_INT_UNDERFLOW_ACK,
 143         PWM_INT_ACK_BITS_MAX,
 144 };
 145
 146 enum PWM_CLOCK_SRC_ENUM{
 147         PWM_CLK_SRC_MIN,
 148         PWM_CLK_OLD_MODE_BLOCK = PWM_CLK_SRC_MIN,
 149         PWM_CLK_OLD_MODE_32K,
 150         PWM_CLK_NEW_MODE_BLOCK,
 151         PWM_CLK_NEW_MODE_BLOCK_DIV_BY_1625,
 152         PWM_CLK_SRC_NUM,
 153         PWM_CLK_SRC_INVALID,
 154 };
 155
 156 enum PWM_MODE_ENUM{
 157         PWM_MODE_MIN,
 158         PWM_MODE_OLD = PWM_MODE_MIN,
 159         PWM_MODE_FIFO,
 160         PWM_MODE_MEMORY,
 161         PWM_MODE_RANDOM,
 162         PWM_MODE_DELAY,
 163         PWM_MODE_INVALID,
 164 };
 165
 166 #define PWM_NEW_MODE_DUTY_TOTAL_BITS 64
 167
 168 void mt_set_pwm_3dlcm_enable_hal(BOOL enable);
 169 void mt_set_pwm_3dlcm_inv_hal(U32 pwm_no, BOOL inv);
 170 void mt_set_pwm_3dlcm_base_hal(U32 pwm_no);
 171
 172 void mt_pwm_26M_clk_enable_hal(U32 enable);
 173
 174 #endif