arch/arm/mach-mt8127/include/mach/irqs.h

   1 #ifndef __IRQS_H
   2 #define __IRQS_H
   3
   4 #include "mt_irq.h"
   5
   6 #define FIQ_START 0
   7 #define CPU_BRINGUP_SGI 1
   8 #define FIQ_SMP_CALL_SGI 13
   9 #define FIQ_DBG_SGI 14
  10 #define NR_IRQS NR_MT_IRQ_LINE
  11 #define MT_EDGE_SENSITIVE 0
  12 #define MT_LEVEL_SENSITIVE 1
  13 #define MT_POLARITY_LOW   0
  14 #define MT_POLARITY_HIGH  1
  15
  16 #if !defined(__ASSEMBLY__)
  17
  18 enum {
  19     IRQ_MASK_HEADER = 0xF1F1F1F1,
  20     IRQ_MASK_FOOTER = 0xF2F2F2F2
  21 };
  22
  23 struct mtk_irq_mask
  24 {
  25     unsigned int header;   /* for error checking */
  26     __u32 mask0;
  27     __u32 mask1;
  28     __u32 mask2;
  29     __u32 mask3;
  30     __u32 mask4;
  31     __u32 mask5;
  32     __u32 mask6;
  33     __u32 mask7;
  34     __u32 mask8;
  35     unsigned int footer;   /* for error checking */
  36 };
  37
  38 typedef void (*fiq_isr_handler)(void *arg, void *regs, void *svc_sp);
  39
  40 extern void mt_init_irq(void);
  41 extern int mt_irq_is_active(const unsigned int irq);
  42 extern int request_fiq(int irq, fiq_isr_handler handler, unsigned long irq_flags, void *arg);
  43 #if defined(CONFIG_FIQ_GLUE)
  44 extern void trigger_sw_irq(int irq);
  45 extern int mt_enable_fiq(int irq);
  46 extern int mt_disable_fiq(int irq);
  47 #else
  48 #define trigger_sw_irq(__irq) (0)
  49 #define mt_enable_fiq(__irq) (0)
  50 #define mt_disable_fiq(__irq) (0)
  51 #endif
  52 extern void mt_enable_ppi(int irq);
  53
  54 #endif  /* !__ASSEMBLY__ */
  55
  56 #endif