arch/arm/mach-mt8127/include/mach/camera_isp.h

   1 #ifndef _MT_ISP_H
   2 #define _MT_ISP_H
   3
   4 #include <linux/ioctl.h>
   5
   6 /*******************************************************************************
   7 *
   8 ********************************************************************************/
   9 #define ISP_DEV_MAJOR_NUMBER    251
  10 #define ISP_MAGIC               'k'
  11 /*******************************************************************************
  12 *
  13 ********************************************************************************/
  14 //CAM_CTL_INT_STATUS
  15 #define ISP_IRQ_INT_STATUS_VS1_ST               ((unsigned int)1 << 0)
  16 #define ISP_IRQ_INT_STATUS_TG1_ST1              ((unsigned int)1 << 1)
  17 #define ISP_IRQ_INT_STATUS_TG1_ST2              ((unsigned int)1 << 2)
  18 #define ISP_IRQ_INT_STATUS_EXPDON1_ST           ((unsigned int)1 << 3)
  19 #define ISP_IRQ_INT_STATUS_TG1_ERR_ST           ((unsigned int)1 << 4)
  20 //#define ISP_IRQ_INT_STATUS_VS2_ST               ((unsigned int)1 << 5)
  21 //#define ISP_IRQ_INT_STATUS_TG2_ST1              ((unsigned int)1 << 6)
  22 //#define ISP_IRQ_INT_STATUS_TG2_ST2              ((unsigned int)1 << 7)
  23 //#define ISP_IRQ_INT_STATUS_EXPDON2_ST           ((unsigned int)1 << 8)
  24 //#define ISP_IRQ_INT_STATUS_TG2_ERR_ST           ((unsigned int)1 << 9)
  25 #define ISP_IRQ_INT_STATUS_PASS1_TG1_DON_ST     ((unsigned int)1 << 10)
  26 //#define ISP_IRQ_INT_STATUS_PASS1_TG2_DON_ST     ((unsigned int)1 << 11)
  27 #define ISP_IRQ_INT_STATUS_SOF1_INT_ST          ((unsigned int)1 << 12)
  28 #define ISP_IRQ_INT_STATUS_CQ_ERR_ST            ((unsigned int)1 << 13)
  29 #define ISP_IRQ_INT_STATUS_PASS2_DON_ST         ((unsigned int)1 << 14)
  30 #define ISP_IRQ_INT_STATUS_TPIPE_DON_ST         ((unsigned int)1 << 15)
  31 #define ISP_IRQ_INT_STATUS_AF_DON_ST            ((unsigned int)1 << 16)
  32 #define ISP_IRQ_INT_STATUS_FLK_DON_ST           ((unsigned int)1 << 17)
  33 //#define ISP_IRQ_INT_STATUS_FMT_DON_ST           ((unsigned int)1 << 18)
  34 #define ISP_IRQ_INT_STATUS_CQ_DON_ST            ((unsigned int)1 << 19)
  35 #define ISP_IRQ_INT_STATUS_IMGO_ERR_ST          ((unsigned int)1 << 20)
  36 #define ISP_IRQ_INT_STATUS_AAO_ERR_ST           ((unsigned int)1 << 21)
  37 //#define ISP_IRQ_INT_STATUS_LCSO_ERR_ST          ((unsigned int)1 << 22)
  38 #define ISP_IRQ_INT_STATUS_IMG2O_ERR_ST         ((unsigned int)1 << 23)
  39 #define ISP_IRQ_INT_STATUS_ESFKO_ERR_ST         ((unsigned int)1 << 24)
  40 #define ISP_IRQ_INT_STATUS_FLK_ERR_ST           ((unsigned int)1 << 25)
  41 #define ISP_IRQ_INT_STATUS_LSC_ERR_ST           ((unsigned int)1 << 26)
  42 #define ISP_IRQ_INT_STATUS_LSC2_ERR_ST          ((unsigned int)1 << 27)
  43 #define ISP_IRQ_INT_STATUS_BPC_ERR_ST           ((unsigned int)1 << 28)
  44 //#define ISP_IRQ_INT_STATUS_LCE_ERR_ST           ((unsigned int)1 << 29)
  45 #define ISP_IRQ_INT_STATUS_DMA_ERR_ST           ((unsigned int)1 << 30)
  46 //CAM_CTL_DMA_INT
  47 #define ISP_IRQ_DMA_INT_IMGO_DONE_ST            ((unsigned int)1 << 0)
  48 #define ISP_IRQ_DMA_INT_IMG2O_DONE_ST           ((unsigned int)1 << 1)
  49 #define ISP_IRQ_DMA_INT_AAO_DONE_ST             ((unsigned int)1 << 2)
  50 //#define ISP_IRQ_DMA_INT_LCSO_DONE_ST            ((unsigned int)1 << 3)
  51 #define ISP_IRQ_DMA_INT_ESFKO_DONE_ST           ((unsigned int)1 << 4)
  52 //#define ISP_IRQ_DMA_INT_DISPO_DONE_ST           ((unsigned int)1 << 5)
  53 //#define ISP_IRQ_DMA_INT_VIDO_DONE_ST            ((unsigned int)1 << 6)
  54 //#define ISP_IRQ_DMA_INT_VRZO_DONE_ST            ((unsigned int)1 << 7)
  55 #define ISP_IRQ_DMA_INT_CQ0_ERR_ST              ((unsigned int)1 << 8)
  56 #define ISP_IRQ_DMA_INT_CQ0_DONE_ST             ((unsigned int)1 << 9)
  57 //#define ISP_IRQ_DMA_INT_SOF2_INT_ST             ((unsigned int)1 << 10)
  58 //#define ISP_IRQ_DMA_INT_BUF_OVL_ST              ((unsigned int)1 << 11)
  59 #define ISP_IRQ_DMA_INT_TG1_GBERR_ST            ((unsigned int)1 << 12)
  60 //#define ISP_IRQ_DMA_INT_TG2_GBERR_ST            ((unsigned int)1 << 13)
  61 #define ISP_IRQ_DMA_INT_CQ0C_DONE_ST            ((unsigned int)1 << 14)
  62 #define ISP_IRQ_DMA_INT_CQ0B_DONE_ST            ((unsigned int)1 << 15)
  63 //CAM_CTL_INTB_STATUS
  64 #define ISP_IRQ_INTB_STATUS_CQ_ERR_ST           ((unsigned int)1 << 13)
  65 #define ISP_IRQ_INTB_STATUS_PASS2_DON_ST        ((unsigned int)1 << 14)
  66 #define ISP_IRQ_INTB_STATUS_TPIPE_DON_ST        ((unsigned int)1 << 15)
  67 #define ISP_IRQ_INTB_STATUS_CQ_DON_ST           ((unsigned int)1 << 19)
  68 #define ISP_IRQ_INTB_STATUS_IMGO_ERR_ST         ((unsigned int)1 << 20)
  69 #define ISP_IRQ_INTB_STATUS_LCSO_ERR_ST         ((unsigned int)1 << 22)
  70 #define ISP_IRQ_INTB_STATUS_IMG2O_ERR_ST        ((unsigned int)1 << 23)
  71 #define ISP_IRQ_INTB_STATUS_LSC_ERR_ST          ((unsigned int)1 << 26)
  72 #define ISP_IRQ_INTB_STATUS_BPC_ERR_ST          ((unsigned int)1 << 28)
  73 #define ISP_IRQ_INTB_STATUS_LCE_ERR_ST          ((unsigned int)1 << 29)
  74 #define ISP_IRQ_INTB_STATUS_DMA_ERR_ST          ((unsigned int)1 << 30)
  75 #define ISP_IRQ_INTB_STATUS_INT_WCLR_ST         ((unsigned int)1 << 31)
  76
  77 //CAM_CTL_DMAB_INT
  78 #define ISP_IRQ_DMAB_INT_IMGO_DONE_ST           ((unsigned int)1 << 0)
  79 #define ISP_IRQ_DMAB_INT_IMG2O_DONE_ST          ((unsigned int)1 << 1)
  80 #define ISP_IRQ_DMAB_INT_AAO_DONE_ST            ((unsigned int)1 << 2)
  81 #define ISP_IRQ_DMAB_INT_LCSO_DONE_ST           ((unsigned int)1 << 3)
  82 #define ISP_IRQ_DMAB_INT_ESFKO_DONE_ST          ((unsigned int)1 << 4)
  83 #define ISP_IRQ_DMAB_INT_DISPO_DONE_ST          ((unsigned int)1 << 5)
  84 #define ISP_IRQ_DMAB_INT_VIDO_DONE_ST           ((unsigned int)1 << 6)
  85 //#define ISP_IRQ_DMAB_INT_VRZO_DONE_ST           ((unsigned int)1 << 7)
  86 //#define ISP_IRQ_DMAB_INT_NR3O_DONE_ST           ((unsigned int)1 << 8)
  87 //#define ISP_IRQ_DMAB_INT_NR3O_ERR_ST            ((unsigned int)1 << 9)
  88 //CAM_CTL_INTC_STATUS
  89 #define ISP_IRQ_INTC_STATUS_CQ_ERR_ST           ((unsigned int)1 << 13)
  90 #define ISP_IRQ_INTC_STATUS_PASS2_DON_ST        ((unsigned int)1 << 14)
  91 #define ISP_IRQ_INTC_STATUS_TPIPE_DON_ST        ((unsigned int)1 << 15)
  92 #define ISP_IRQ_INTC_STATUS_CQ_DON_ST           ((unsigned int)1 << 19)
  93 #define ISP_IRQ_INTC_STATUS_IMGO_ERR_ST         ((unsigned int)1 << 20)
  94 #define ISP_IRQ_INTC_STATUS_LCSO_ERR_ST         ((unsigned int)1 << 22)
  95 #define ISP_IRQ_INTC_STATUS_IMG2O_ERR_ST        ((unsigned int)1 << 23)
  96 #define ISP_IRQ_INTC_STATUS_LSC_ERR_ST          ((unsigned int)1 << 26)
  97 #define ISP_IRQ_INTC_STATUS_BPC_ERR_ST          ((unsigned int)1 << 28)
  98 #define ISP_IRQ_INTC_STATUS_LCE_ERR_ST          ((unsigned int)1 << 29)
  99 #define ISP_IRQ_INTC_STATUS_DMA_ERR_ST          ((unsigned int)1 << 30)
 100 //CAM_CTL_DMAC_INT
 101 #define ISP_IRQ_DMAC_INT_IMGO_DONE_ST           ((unsigned int)1 << 0)
 102 #define ISP_IRQ_DMAC_INT_IMG2O_DONE_ST          ((unsigned int)1 << 1)
 103 #define ISP_IRQ_DMAC_INT_AAO_DONE_ST            ((unsigned int)1 << 2)
 104 #define ISP_IRQ_DMAC_INT_LCSO_DONE_ST           ((unsigned int)1 << 3)
 105 #define ISP_IRQ_DMAC_INT_ESFKO_DONE_ST          ((unsigned int)1 << 4)
 106 #define ISP_IRQ_DMAC_INT_DISPO_DONE_ST          ((unsigned int)1 << 5)
 107 #define ISP_IRQ_DMAC_INT_VIDO_DONE_ST           ((unsigned int)1 << 6)
 108 //#define ISP_IRQ_DMAC_INT_VRZO_DONE_ST           ((unsigned int)1 << 7)
 109 //#define ISP_IRQ_DMAC_INT_NR3O_DONE_ST           ((unsigned int)1 << 8)
 110 //#define ISP_IRQ_DMAC_INT_NR3O_ERR_ST            ((unsigned int)1 << 9)
 111 //CAM_CTL_INT_STATUSX
 112 #define ISP_IRQ_INTX_STATUS_VS1_ST              ((unsigned int)1 << 0)
 113 #define ISP_IRQ_INTX_STATUS_TG1_ST1             ((unsigned int)1 << 1)
 114 #define ISP_IRQ_INTX_STATUS_TG1_ST2             ((unsigned int)1 << 2)
 115 #define ISP_IRQ_INTX_STATUS_EXPDON1_ST          ((unsigned int)1 << 3)
 116 #define ISP_IRQ_INTX_STATUS_TG1_ERR_ST          ((unsigned int)1 << 4)
 117 #define ISP_IRQ_INTX_STATUS_VS2_ST              ((unsigned int)1 << 5)
 118 #define ISP_IRQ_INTX_STATUS_TG2_ST1             ((unsigned int)1 << 6)
 119 #define ISP_IRQ_INTX_STATUS_TG2_ST2             ((unsigned int)1 << 7)
 120 #define ISP_IRQ_INTX_STATUS_EXPDON2_ST          ((unsigned int)1 << 8)
 121 #define ISP_IRQ_INTX_STATUS_TG2_ERR_ST          ((unsigned int)1 << 9)
 122 #define ISP_IRQ_INTX_STATUS_PASS1_TG1_DON_ST    ((unsigned int)1 << 10)
 123 #define ISP_IRQ_INTX_STATUS_PASS1_TG2_DON_ST    ((unsigned int)1 << 11)
 124 //#define ISP_IRQ_INTX_STATUS_VEC_DON_ST          ((unsigned int)1 << 12)
 125 #define ISP_IRQ_INTX_STATUS_CQ_ERR_ST           ((unsigned int)1 << 13)
 126 #define ISP_IRQ_INTX_STATUS_PASS2_DON_ST        ((unsigned int)1 << 14)
 127 #define ISP_IRQ_INTX_STATUS_TPIPE_DON_ST        ((unsigned int)1 << 15)
 128 #define ISP_IRQ_INTX_STATUS_AF_DON_ST           ((unsigned int)1 << 16)
 129 #define ISP_IRQ_INTX_STATUS_FLK_DON_ST          ((unsigned int)1 << 17)
 130 #define ISP_IRQ_INTX_STATUS_FMT_DON_ST          ((unsigned int)1 << 18)
 131 #define ISP_IRQ_INTX_STATUS_CQ_DON_ST           ((unsigned int)1 << 19)
 132 #define ISP_IRQ_INTX_STATUS_IMGO_ERR_ST         ((unsigned int)1 << 20)
 133 #define ISP_IRQ_INTX_STATUS_AAO_ERR_ST          ((unsigned int)1 << 21)
 134 #define ISP_IRQ_INTX_STATUS_LCSO_ERR_ST         ((unsigned int)1 << 22)
 135 #define ISP_IRQ_INTX_STATUS_IMG2O_ERR_ST        ((unsigned int)1 << 23)
 136 #define ISP_IRQ_INTX_STATUS_ESFKO_ERR_ST        ((unsigned int)1 << 24)
 137 #define ISP_IRQ_INTX_STATUS_FLK_ERR_ST          ((unsigned int)1 << 25)
 138 #define ISP_IRQ_INTX_STATUS_LSC_ERR_ST          ((unsigned int)1 << 26)
 139 //#define ISP_IRQ_INTX_STATUS_LSC2_ERR_ST         ((unsigned int)1 << 27)
 140 #define ISP_IRQ_INTX_STATUS_BPC_ERR_ST          ((unsigned int)1 << 28)
 141 #define ISP_IRQ_INTX_STATUS_LCE_ERR_ST          ((unsigned int)1 << 29)
 142 #define ISP_IRQ_INTX_STATUS_DMA_ERR_ST          ((unsigned int)1 << 30)
 143 //CAM_CTL_DMA_INTX
 144 #define ISP_IRQ_DMAX_INT_IMGO_DONE_ST           ((unsigned int)1 << 0)
 145 #define ISP_IRQ_DMAX_INT_IMG2O_DONE_ST          ((unsigned int)1 << 1)
 146 #define ISP_IRQ_DMAX_INT_AAO_DONE_ST            ((unsigned int)1 << 2)
 147 #define ISP_IRQ_DMAX_INT_LCSO_DONE_ST           ((unsigned int)1 << 3)
 148 #define ISP_IRQ_DMAX_INT_ESFKO_DONE_ST          ((unsigned int)1 << 4)
 149 #define ISP_IRQ_DMAX_INT_DISPO_DONE_ST          ((unsigned int)1 << 5)
 150 #define ISP_IRQ_DMAX_INT_VIDO_DONE_ST           ((unsigned int)1 << 6)
 151 #define ISP_IRQ_DMAX_INT_VRZO_DONE_ST           ((unsigned int)1 << 7)
 152 #define ISP_IRQ_DMAX_INT_NR3O_DONE_ST           ((unsigned int)1 << 8)
 153 #define ISP_IRQ_DMAX_INT_NR3O_ERR_ST            ((unsigned int)1 << 9)
 154 #define ISP_IRQ_DMAX_INT_CQ_ERR_ST              ((unsigned int)1 << 10)
 155 #define ISP_IRQ_DMAX_INT_BUF_OVL_ST             ((unsigned int)1 << 11)
 156 #define ISP_IRQ_DMAX_INT_TG1_GBERR_ST           ((unsigned int)1 << 12)
 157 #define ISP_IRQ_DMAX_INT_TG2_GBERR_ST           ((unsigned int)1 << 13)
 158
 159 /*******************************************************************************
 160 *
 161 ********************************************************************************/
 162 typedef enum
 163 {
 164     ISP_IRQ_CLEAR_NONE,
 165     ISP_IRQ_CLEAR_WAIT,
 166     ISP_IRQ_CLEAR_ALL
 167 }ISP_IRQ_CLEAR_ENUM;
 168
 169 typedef enum
 170 {
 171     ISP_IRQ_TYPE_INT,
 172     ISP_IRQ_TYPE_DMA,
 173     ISP_IRQ_TYPE_INTB,
 174     ISP_IRQ_TYPE_DMAB,
 175     ISP_IRQ_TYPE_INTC,
 176     ISP_IRQ_TYPE_DMAC,
 177     ISP_IRQ_TYPE_INTX,
 178     ISP_IRQ_TYPE_DMAX,
 179     ISP_IRQ_TYPE_AMOUNT
 180 }ISP_IRQ_TYPE_ENUM;
 181
 182 typedef struct
 183 {
 184     ISP_IRQ_CLEAR_ENUM  Clear;
 185     ISP_IRQ_TYPE_ENUM   Type;
 186     unsigned int       Status;
 187     unsigned int       Timeout;
 188 }ISP_WAIT_IRQ_STRUCT;
 189
 190 typedef struct
 191 {
 192     ISP_IRQ_TYPE_ENUM   Type;
 193     unsigned int       Status;
 194 }ISP_READ_IRQ_STRUCT;
 195
 196 typedef struct
 197 {
 198     ISP_IRQ_TYPE_ENUM   Type;
 199     unsigned int       Status;
 200 }ISP_CLEAR_IRQ_STRUCT;
 201
 202 typedef enum
 203 {
 204     ISP_HOLD_TIME_VD,
 205     ISP_HOLD_TIME_EXPDONE
 206 }ISP_HOLD_TIME_ENUM;
 207
 208 typedef struct
 209 {
 210     unsigned int Addr;   // register's addr
 211     unsigned int Val;    // register's value
 212 }ISP_REG_STRUCT;
 213
 214 typedef struct
 215 {
 216     unsigned int Data;   // pointer to ISP_REG_STRUCT
 217     unsigned int Count;  // count
 218 }ISP_REG_IO_STRUCT;
 219
 220 typedef void (*pIspCallback)(void);
 221
 222 typedef enum
 223 {
 224     //Work queue. It is interruptible, so there can be "Sleep" in work queue function.
 225     ISP_CALLBACK_WORKQUEUE_VD,
 226     ISP_CALLBACK_WORKQUEUE_EXPDONE,
 227     ISP_CALLBACK_WORKQUEUE_SENINF,
 228     //Tasklet. It is uninterrupted, so there can NOT be "Sleep" in tasklet function.
 229     ISP_CALLBACK_TASKLET_VD,
 230     ISP_CALLBACK_TASKLET_EXPDONE,
 231     ISP_CALLBACK_TASKLET_SENINF,
 232     ISP_CALLBACK_AMOUNT
 233 }ISP_CALLBACK_ENUM;
 234
 235 typedef struct
 236 {
 237     ISP_CALLBACK_ENUM   Type;
 238     pIspCallback        Func;
 239 }ISP_CALLBACK_STRUCT;
 240
 241 //
 242 // length of the two memory areas
 243 #define RT_BUF_TBL_NPAGES 16
 244 #define ISP_RT_BUF_SIZE 16
 245 //#define ISP_RT_CQ0C_BUF_SIZE (ISP_RT_BUF_SIZE>>2)
 246 #define ISP_RT_CQ0C_BUF_SIZE (6)    //special for 6582
 247
 248
 249 //
 250 typedef enum
 251 {
 252     _imgi_  = 0,
 253     _imgci_,    // 1
 254     _vipi_ ,    // 2
 255     _vip2i_,    // 3
 256     _imgo_,     // 4
 257     _img2o_,    // 5
 258     _dispo_,    // 6
 259     _vido_,     // 7
 260     _fdo_,      // 8
 261     _lsci_,     // 9
 262     _lcei_,     // 10
 263     _rt_dma_max_
 264 }_isp_dma_enum_;
 265 //
 266 typedef struct {
 267     unsigned int   memID;
 268     unsigned int   size;
 269     unsigned int   base_vAddr;
 270     unsigned int   base_pAddr;
 271     unsigned int   timeStampS;
 272     unsigned int   timeStampUs;
 273     unsigned int   bFilled;
 274 }ISP_RT_BUF_INFO_STRUCT;
 275 //
 276 typedef struct  {
 277     unsigned int           count;
 278     ISP_RT_BUF_INFO_STRUCT  data[ISP_RT_BUF_SIZE];
 279 }ISP_DEQUE_BUF_INFO_STRUCT;
 280 //
 281 typedef struct  {
 282     unsigned int           start;          //current DMA accessing buffer
 283     unsigned int           total_count;    //total buffer number.Include Filled and empty
 284     unsigned int           empty_count;    //total empty buffer number include current DMA accessing buffer
 285     unsigned int           pre_empty_count;//previous total empty buffer number include current DMA accessing buffer
 286     unsigned int           active;
 287     ISP_RT_BUF_INFO_STRUCT  data[ISP_RT_BUF_SIZE];
 288 }ISP_RT_RING_BUF_INFO_STRUCT;
 289 //
 290 typedef enum
 291 {
 292     ISP_RT_BUF_CTRL_ENQUE,          // 0
 293     ISP_RT_BUF_CTRL_EXCHANGE_ENQUE, // 1
 294     ISP_RT_BUF_CTRL_DEQUE,          // 2
 295     ISP_RT_BUF_CTRL_IS_RDY,         // 3
 296     ISP_RT_BUF_CTRL_GET_SIZE,       // 4
 297     ISP_RT_BUF_CTRL_CLEAR,          // 5
 298     ISP_RT_BUF_CTRL_MAX
 299 }ISP_RT_BUF_CTRL_ENUM;
 300 //
 301 typedef enum
 302 {
 303     ISP_RTBC_STATE_INIT, // 0
 304     ISP_RTBC_STATE_SOF,
 305     ISP_RTBC_STATE_DONE,
 306     ISP_RTBC_STATE_MAX
 307 }ISP_RTBC_STATE_ENUM;
 308 //
 309 typedef enum
 310 {
 311     ISP_RTBC_BUF_EMPTY, // 0
 312     ISP_RTBC_BUF_FILLED,// 1
 313     ISP_RTBC_BUF_LOCKED,// 2
 314 }ISP_RTBC_BUF_STATE_ENUM;
 315 //
 316 typedef struct  {
 317     ISP_RTBC_STATE_ENUM state;
 318     unsigned long dropCnt;
 319     ISP_RT_RING_BUF_INFO_STRUCT  ring_buf[_rt_dma_max_];
 320 }ISP_RT_BUF_STRUCT;
 321 //
 322 typedef struct  {
 323     ISP_RT_BUF_CTRL_ENUM    ctrl;
 324     _isp_dma_enum_          buf_id;
 325     unsigned int            data_ptr;
 326     unsigned int            ex_data_ptr; //exchanged buffer
 327 }ISP_BUFFER_CTRL_STRUCT;
 328 //
 329 //reference count
 330 #define _use_kernel_ref_cnt_
 331 //
 332 typedef enum
 333 {
 334     ISP_REF_CNT_GET,    // 0
 335     ISP_REF_CNT_INC,    // 1
 336     ISP_REF_CNT_DEC,    // 2
 337     ISP_REF_CNT_DEC_AND_RESET_IF_LAST_ONE,    // 3
 338     ISP_REF_CNT_MAX
 339 }ISP_REF_CNT_CTRL_ENUM;
 340 //
 341 typedef enum
 342 {
 343     ISP_REF_CNT_ID_IMEM,        // 0
 344     ISP_REF_CNT_ID_ISP_FUNC,    // 1
 345     ISP_REF_CNT_ID_GLOBAL_PIPE, // 2
 346     ISP_REF_CNT_ID_MAX,
 347 }ISP_REF_CNT_ID_ENUM;
 348 //
 349 typedef struct  {
 350     ISP_REF_CNT_CTRL_ENUM   ctrl;
 351     ISP_REF_CNT_ID_ENUM     id;
 352     unsigned long           data_ptr;
 353 }ISP_REF_CNT_CTRL_STRUCT;
 354
 355
 356 /********************************************************************************************
 357  pass1 real time buffer control use cq0c
 358 ********************************************************************************************/
 359 //
 360 #define _rtbc_use_cq0c_
 361
 362 #if defined(_rtbc_use_cq0c_)
 363 //
 364 typedef volatile union _CQ_RTBC_FBC_
 365 {
 366     volatile struct
 367     {
 368         unsigned long FBC_CNT                   : 4;
 369         unsigned long DROP_INT_EN               : 1;
 370         unsigned long rsv_5                     : 6;
 371         unsigned long RCNT_INC                  : 1;
 372         unsigned long rsv_12                    : 2;
 373         unsigned long FBC_EN                    : 1;
 374         unsigned long LOCK_EN                   : 1;
 375         unsigned long FB_NUM                    : 4;
 376         unsigned long RCNT                      : 4;
 377         unsigned long WCNT                      : 4;
 378         unsigned long DROP_CNT                  : 4;
 379     } Bits;
 380     unsigned long Reg_val;
 381 }CQ_RTBC_FBC;
 382
 383 typedef struct _cq_cmd_st_
 384 {
 385     unsigned long inst;
 386     unsigned long data_ptr_pa;
 387 }CQ_CMD_ST;
 388 /*
 389 typedef struct _cq_cmd_rtbc_st_
 390 {
 391     CQ_CMD_ST imgo;
 392     CQ_CMD_ST img2o;
 393     CQ_CMD_ST cq0ci;
 394     CQ_CMD_ST end;
 395 }CQ_CMD_RTBC_ST;
 396 */
 397 typedef struct _cq_info_rtbc_st_
 398 {
 399     CQ_CMD_ST imgo;
 400     CQ_CMD_ST img2o;
 401     CQ_CMD_ST next_cq0ci;
 402     CQ_CMD_ST end;
 403     unsigned long imgo_base_pAddr;
 404     unsigned long img2o_base_pAddr;
 405 }CQ_INFO_RTBC_ST;
 406 typedef struct _cq_ring_cmd_st_
 407 {
 408     CQ_INFO_RTBC_ST cq_rtbc;
 409     unsigned long next_pa;
 410     struct _cq_ring_cmd_st_ *pNext;
 411 }CQ_RING_CMD_ST;
 412 typedef struct _cq_rtbc_ring_st_
 413 {
 414     CQ_RING_CMD_ST rtbc_ring[ISP_RT_CQ0C_BUF_SIZE];
 415     unsigned long   imgo_ring_size;
 416     unsigned long   img2o_ring_size;
 417 }CQ_RTBC_RING_ST;
 418 #endif
 419 //
 420 /********************************************************************************************
 421
 422 ********************************************************************************************/
 423
 424
 425 /*******************************************************************************
 426 *
 427 ********************************************************************************/
 428 typedef enum
 429 {
 430     ISP_CMD_RESET,          //Reset
 431     ISP_CMD_RESET_BUF,
 432     ISP_CMD_READ_REG,       //Read register from driver
 433     ISP_CMD_WRITE_REG,      //Write register to driver
 434     ISP_CMD_HOLD_TIME,
 435     ISP_CMD_HOLD_REG,       //Hold reg write to hw, on/off
 436     ISP_CMD_WAIT_IRQ,       //Wait IRQ
 437     ISP_CMD_READ_IRQ,       //Read IRQ
 438     ISP_CMD_CLEAR_IRQ,      //Clear IRQ
 439     ISP_CMD_DUMP_REG,       //Dump ISP registers , for debug usage
 440     ISP_CMD_SET_USER_PID,   //for signal
 441     ISP_CMD_RT_BUF_CTRL,   //for pass buffer control
 442     ISP_CMD_REF_CNT,        //get imem reference count
 443     ISP_CMD_DEBUG_FLAG,      //Dump message level
 444     ISP_CMD_SENSOR_FREQ_CTRL      // sensor frequence control
 445 }ISP_CMD_ENUM;
 446 //
 447 #define ISP_RESET           _IO  (ISP_MAGIC, ISP_CMD_RESET)
 448 #define ISP_RESET_BUF       _IO  (ISP_MAGIC, ISP_CMD_RESET_BUF)
 449 #define ISP_READ_REGISTER   _IOWR(ISP_MAGIC, ISP_CMD_READ_REG,      ISP_REG_IO_STRUCT)
 450 #define ISP_WRITE_REGISTER  _IOWR(ISP_MAGIC, ISP_CMD_WRITE_REG,     ISP_REG_IO_STRUCT)
 451 #define ISP_HOLD_REG_TIME   _IOW (ISP_MAGIC, ISP_CMD_HOLD_TIME,     ISP_HOLD_TIME_ENUM)
 452 #define ISP_HOLD_REG        _IOW (ISP_MAGIC, ISP_CMD_HOLD_REG,      bool)
 453 #define ISP_WAIT_IRQ        _IOW (ISP_MAGIC, ISP_CMD_WAIT_IRQ,      ISP_WAIT_IRQ_STRUCT)
 454 #define ISP_READ_IRQ        _IOR (ISP_MAGIC, ISP_CMD_READ_IRQ,      ISP_READ_IRQ_STRUCT)
 455 #define ISP_CLEAR_IRQ       _IOW (ISP_MAGIC, ISP_CMD_CLEAR_IRQ,     ISP_CLEAR_IRQ_STRUCT)
 456 #define ISP_DUMP_REG        _IO  (ISP_MAGIC, ISP_CMD_DUMP_REG)
 457 #define ISP_SET_USER_PID    _IOW (ISP_MAGIC, ISP_CMD_SET_USER_PID,    unsigned long)
 458 #define ISP_BUFFER_CTRL     _IOWR(ISP_MAGIC, ISP_CMD_RT_BUF_CTRL,    ISP_BUFFER_CTRL_STRUCT)
 459 #define ISP_REF_CNT_CTRL    _IOWR(ISP_MAGIC, ISP_CMD_REF_CNT,       ISP_REF_CNT_CTRL_STRUCT)
 460 #define ISP_DEBUG_FLAG      _IOW (ISP_MAGIC, ISP_CMD_DEBUG_FLAG,    unsigned long)
 461 #define ISP_SENSOR_FREQ_CTRL  _IOW (ISP_MAGIC, ISP_CMD_SENSOR_FREQ_CTRL,    unsigned long)
 462
 463 //
 464 bool ISP_RegCallback(ISP_CALLBACK_STRUCT* pCallback);
 465 bool ISP_UnregCallback(ISP_CALLBACK_ENUM   Type);
 466 //
 467 #endif
 468