arch/arm/mach-imx/mach-mx21ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_device.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/physmap.h>
  20 #include <linux/gpio.h>
  21 #include <mach/common.h>
  22 #include <mach/hardware.h>
  23 #include <asm/mach-types.h>
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/time.h>
  26 #include <asm/mach/map.h>
  27 #include <mach/iomux-mx21.h>
  28 #include <mach/mxc_nand.h>
  29
  30 #include "devices-imx21.h"
  31
  32 /*
  33  * Memory-mapped I/O on MX21ADS base board
  34  */
  35 #define MX21ADS_MMIO_BASE_ADDR   0xf5000000
  36 #define MX21ADS_MMIO_SIZE        SZ_16M
  37
  38 #define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
  39                 (MX21ADS_MMIO_BASE_ADDR + (offset))
  40
  41 #define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
  42 #define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
  43 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
  44 #define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
  45 #define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
  46
  47 /* MX21ADS_IO_REG bit definitions */
  48 #define MX21ADS_IO_SD_WP        0x0001 /* read */
  49 #define MX21ADS_IO_TP6          0x0001 /* write */
  50 #define MX21ADS_IO_SW_SEL       0x0002 /* read */
  51 #define MX21ADS_IO_TP7          0x0002 /* write */
  52 #define MX21ADS_IO_RESET_E_UART 0x0004
  53 #define MX21ADS_IO_RESET_BASE   0x0008
  54 #define MX21ADS_IO_CSI_CTL2     0x0010
  55 #define MX21ADS_IO_CSI_CTL1     0x0020
  56 #define MX21ADS_IO_CSI_CTL0     0x0040
  57 #define MX21ADS_IO_UART1_EN     0x0080
  58 #define MX21ADS_IO_UART4_EN     0x0100
  59 #define MX21ADS_IO_LCDON        0x0200
  60 #define MX21ADS_IO_IRDA_EN      0x0400
  61 #define MX21ADS_IO_IRDA_FIR_SEL 0x0800
  62 #define MX21ADS_IO_IRDA_MD0_B   0x1000
  63 #define MX21ADS_IO_IRDA_MD1     0x2000
  64 #define MX21ADS_IO_LED4_ON      0x4000
  65 #define MX21ADS_IO_LED3_ON      0x8000
  66
  67 static const int mx21ads_pins[] __initconst = {
  68
  69         /* CS8900A */
  70         (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
  71
  72         /* UART1 */
  73         PE12_PF_UART1_TXD,
  74         PE13_PF_UART1_RXD,
  75         PE14_PF_UART1_CTS,
  76         PE15_PF_UART1_RTS,
  77
  78         /* UART3 (IrDA) - only TXD and RXD */
  79         PE8_PF_UART3_TXD,
  80         PE9_PF_UART3_RXD,
  81
  82         /* UART4 */
  83         PB26_AF_UART4_RTS,
  84         PB28_AF_UART4_TXD,
  85         PB29_AF_UART4_CTS,
  86         PB31_AF_UART4_RXD,
  87
  88         /* LCDC */
  89         PA5_PF_LSCLK,
  90         PA6_PF_LD0,
  91         PA7_PF_LD1,
  92         PA8_PF_LD2,
  93         PA9_PF_LD3,
  94         PA10_PF_LD4,
  95         PA11_PF_LD5,
  96         PA12_PF_LD6,
  97         PA13_PF_LD7,
  98         PA14_PF_LD8,
  99         PA15_PF_LD9,
 100         PA16_PF_LD10,
 101         PA17_PF_LD11,
 102         PA18_PF_LD12,
 103         PA19_PF_LD13,
 104         PA20_PF_LD14,
 105         PA21_PF_LD15,
 106         PA22_PF_LD16,
 107         PA24_PF_REV,     /* Sharp panel dedicated signal */
 108         PA25_PF_CLS,     /* Sharp panel dedicated signal */
 109         PA26_PF_PS,      /* Sharp panel dedicated signal */
 110         PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
 111         PA28_PF_HSYNC,
 112         PA29_PF_VSYNC,
 113         PA30_PF_CONTRAST,
 114         PA31_PF_OE_ACD,
 115
 116         /* MMC/SDHC */
 117         PE18_PF_SD1_D0,
 118         PE19_PF_SD1_D1,
 119         PE20_PF_SD1_D2,
 120         PE21_PF_SD1_D3,
 121         PE22_PF_SD1_CMD,
 122         PE23_PF_SD1_CLK,
 123
 124         /* NFC */
 125         PF0_PF_NRFB,
 126         PF1_PF_NFCE,
 127         PF2_PF_NFWP,
 128         PF3_PF_NFCLE,
 129         PF4_PF_NFALE,
 130         PF5_PF_NFRE,
 131         PF6_PF_NFWE,
 132         PF7_PF_NFIO0,
 133         PF8_PF_NFIO1,
 134         PF9_PF_NFIO2,
 135         PF10_PF_NFIO3,
 136         PF11_PF_NFIO4,
 137         PF12_PF_NFIO5,
 138         PF13_PF_NFIO6,
 139         PF14_PF_NFIO7,
 140 };
 141
 142 /* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
 143 static struct physmap_flash_data mx21ads_flash_data = {
 144         .width = 4,
 145 };
 146
 147 static struct resource mx21ads_flash_resource = {
 148         .start = MX21_CS0_BASE_ADDR,
 149         .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
 150         .flags = IORESOURCE_MEM,
 151 };
 152
 153 static struct platform_device mx21ads_nor_mtd_device = {
 154         .name = "physmap-flash",
 155         .id = 0,
 156         .dev = {
 157                 .platform_data = &mx21ads_flash_data,
 158         },
 159         .num_resources = 1,
 160         .resource = &mx21ads_flash_resource,
 161 };
 162
 163 static const struct imxuart_platform_data uart_pdata_rts __initconst = {
 164         .flags = IMXUART_HAVE_RTSCTS,
 165 };
 166
 167 static const struct imxuart_platform_data uart_pdata_norts __initconst = {
 168 };
 169
 170 static int mx21ads_fb_init(struct platform_device *pdev)
 171 {
 172         u16 tmp;
 173
 174         tmp = __raw_readw(MX21ADS_IO_REG);
 175         tmp |= MX21ADS_IO_LCDON;
 176         __raw_writew(tmp, MX21ADS_IO_REG);
 177         return 0;
 178 }
 179
 180 static void mx21ads_fb_exit(struct platform_device *pdev)
 181 {
 182         u16 tmp;
 183
 184         tmp = __raw_readw(MX21ADS_IO_REG);
 185         tmp &= ~MX21ADS_IO_LCDON;
 186         __raw_writew(tmp, MX21ADS_IO_REG);
 187 }
 188
 189 /*
 190  * Connected is a portrait Sharp-QVGA display
 191  * of type: LQ035Q7DB02
 192  */
 193 static struct imx_fb_videomode mx21ads_modes[] = {
 194         {
 195                 .mode = {
 196                         .name           = "Sharp-LQ035Q7",
 197                         .refresh        = 60,
 198                         .xres           = 240,
 199                         .yres           = 320,
 200                         .pixclock       = 188679, /* in ps (5.3MHz) */
 201                         .hsync_len      = 2,
 202                         .left_margin    = 6,
 203                         .right_margin   = 16,
 204                         .vsync_len      = 1,
 205                         .upper_margin   = 8,
 206                         .lower_margin   = 10,
 207                 },
 208                 .pcr            = 0xfb108bc7,
 209                 .bpp            = 16,
 210         },
 211 };
 212
 213 static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
 214         .mode = mx21ads_modes,
 215         .num_modes = ARRAY_SIZE(mx21ads_modes),
 216
 217         .pwmr           = 0x00a903ff,
 218         .lscr1          = 0x00120300,
 219         .dmacr          = 0x00020008,
 220
 221         .init = mx21ads_fb_init,
 222         .exit = mx21ads_fb_exit,
 223 };
 224
 225 static int mx21ads_sdhc_get_ro(struct device *dev)
 226 {
 227         return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
 228 }
 229
 230 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
 231         void *data)
 232 {
 233         return request_irq(IRQ_GPIOD(25), detect_irq,
 234                 IRQF_TRIGGER_FALLING, "mmc-detect", data);
 235 }
 236
 237 static void mx21ads_sdhc_exit(struct device *dev, void *data)
 238 {
 239         free_irq(IRQ_GPIOD(25), data);
 240 }
 241
 242 static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
 243         .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
 244         .get_ro = mx21ads_sdhc_get_ro,
 245         .init = mx21ads_sdhc_init,
 246         .exit = mx21ads_sdhc_exit,
 247 };
 248
 249 static const struct mxc_nand_platform_data
 250 mx21ads_nand_board_info __initconst = {
 251         .width = 1,
 252         .hw_ecc = 1,
 253 };
 254
 255 static struct map_desc mx21ads_io_desc[] __initdata = {
 256         /*
 257          * Memory-mapped I/O on MX21ADS Base board:
 258          *   - CS8900A Ethernet controller
 259          *   - ST16C2552CJ UART
 260          *   - CPU and Base board version
 261          *   - Base board I/O register
 262          */
 263         {
 264                 .virtual = MX21ADS_MMIO_BASE_ADDR,
 265                 .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
 266                 .length = MX21ADS_MMIO_SIZE,
 267                 .type = MT_DEVICE,
 268         },
 269 };
 270
 271 static void __init mx21ads_map_io(void)
 272 {
 273         mx21_map_io();
 274         iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
 275 }
 276
 277 static struct platform_device *platform_devices[] __initdata = {
 278         &mx21ads_nor_mtd_device,
 279 };
 280
 281 static void __init mx21ads_board_init(void)
 282 {
 283         mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
 284                         "mx21ads");
 285
 286         imx21_add_imx_uart0(&uart_pdata_rts);
 287         imx21_add_imx_uart2(&uart_pdata_norts);
 288         imx21_add_imx_uart3(&uart_pdata_rts);
 289         imx21_add_imx_fb(&mx21ads_fb_data);
 290         imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
 291         imx21_add_mxc_nand(&mx21ads_nand_board_info);
 292
 293         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 294 }
 295
 296 static void __init mx21ads_timer_init(void)
 297 {
 298         mx21_clocks_init(32768, 26000000);
 299 }
 300
 301 static struct sys_timer mx21ads_timer = {
 302         .init   = mx21ads_timer_init,
 303 };
 304
 305 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
 306         /* maintainer: Freescale Semiconductor, Inc. */
 307         .boot_params    = MX21_PHYS_OFFSET + 0x100,
 308         .map_io         = mx21ads_map_io,
 309         .init_irq       = mx21_init_irq,
 310         .init_machine   = mx21ads_board_init,
 311         .timer          = &mx21ads_timer,
 312 MACHINE_END