2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for EXYNOS
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqchip.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/sched.h>
20 #include <linux/serial_core.h>
22 #include <linux/of_fdt.h>
23 #include <linux/of_irq.h>
24 #include <linux/export.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip.h>
27 #include <linux/of_address.h>
28 #include <linux/clocksource.h>
29 #include <linux/clk-provider.h>
30 #include <linux/irqchip/arm-gic.h>
32 #include <asm/proc-fns.h>
33 #include <asm/exception.h>
34 #include <asm/hardware/cache-l2x0.h>
35 #include <asm/mach/map.h>
36 #include <asm/mach/irq.h>
37 #include <asm/cacheflush.h>
39 #include <mach/regs-irq.h>
40 #include <mach/regs-pmu.h>
41 #include <mach/regs-gpio.h>
42 #include <mach/irqs.h>
45 #include <plat/devs.h>
47 #include <plat/sdhci.h>
48 #include <plat/gpio-cfg.h>
49 #include <plat/adc-core.h>
50 #include <plat/fb-core.h>
51 #include <plat/fimc-core.h>
52 #include <plat/iic-core.h>
53 #include <plat/tv-core.h>
54 #include <plat/spi-core.h>
55 #include <plat/regs-serial.h>
58 #define L2_AUX_VAL 0x7C470001
59 #define L2_AUX_MASK 0xC200ffff
61 static const char name_exynos4210
[] = "EXYNOS4210";
62 static const char name_exynos4212
[] = "EXYNOS4212";
63 static const char name_exynos4412
[] = "EXYNOS4412";
64 static const char name_exynos5250
[] = "EXYNOS5250";
65 static const char name_exynos5440
[] = "EXYNOS5440";
67 static void exynos4_map_io(void);
68 static void exynos5_map_io(void);
69 static void exynos5440_map_io(void);
70 static void exynos4_init_uarts(struct s3c2410_uartcfg
*cfg
, int no
);
71 static int exynos_init(void);
73 unsigned long xxti_f
= 0, xusbxti_f
= 0;
75 static struct cpu_table cpu_ids
[] __initdata
= {
77 .idcode
= EXYNOS4210_CPU_ID
,
78 .idmask
= EXYNOS4_CPU_MASK
,
79 .map_io
= exynos4_map_io
,
80 .init_uarts
= exynos4_init_uarts
,
82 .name
= name_exynos4210
,
84 .idcode
= EXYNOS4212_CPU_ID
,
85 .idmask
= EXYNOS4_CPU_MASK
,
86 .map_io
= exynos4_map_io
,
87 .init_uarts
= exynos4_init_uarts
,
89 .name
= name_exynos4212
,
91 .idcode
= EXYNOS4412_CPU_ID
,
92 .idmask
= EXYNOS4_CPU_MASK
,
93 .map_io
= exynos4_map_io
,
94 .init_uarts
= exynos4_init_uarts
,
96 .name
= name_exynos4412
,
98 .idcode
= EXYNOS5250_SOC_ID
,
99 .idmask
= EXYNOS5_SOC_MASK
,
100 .map_io
= exynos5_map_io
,
102 .name
= name_exynos5250
,
104 .idcode
= EXYNOS5440_SOC_ID
,
105 .idmask
= EXYNOS5_SOC_MASK
,
106 .map_io
= exynos5440_map_io
,
108 .name
= name_exynos5440
,
112 /* Initial IO mappings */
114 static struct map_desc exynos_iodesc
[] __initdata
= {
116 .virtual = (unsigned long)S5P_VA_CHIPID
,
117 .pfn
= __phys_to_pfn(EXYNOS_PA_CHIPID
),
123 #ifdef CONFIG_ARCH_EXYNOS5
124 static struct map_desc exynos5440_iodesc
[] __initdata
= {
126 .virtual = (unsigned long)S5P_VA_CHIPID
,
127 .pfn
= __phys_to_pfn(EXYNOS5440_PA_CHIPID
),
134 static struct map_desc exynos4_iodesc
[] __initdata
= {
136 .virtual = (unsigned long)S3C_VA_SYS
,
137 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSCON
),
141 .virtual = (unsigned long)S3C_VA_TIMER
,
142 .pfn
= __phys_to_pfn(EXYNOS4_PA_TIMER
),
146 .virtual = (unsigned long)S3C_VA_WATCHDOG
,
147 .pfn
= __phys_to_pfn(EXYNOS4_PA_WATCHDOG
),
151 .virtual = (unsigned long)S5P_VA_SROMC
,
152 .pfn
= __phys_to_pfn(EXYNOS4_PA_SROMC
),
156 .virtual = (unsigned long)S5P_VA_SYSTIMER
,
157 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSTIMER
),
161 .virtual = (unsigned long)S5P_VA_PMU
,
162 .pfn
= __phys_to_pfn(EXYNOS4_PA_PMU
),
166 .virtual = (unsigned long)S5P_VA_COMBINER_BASE
,
167 .pfn
= __phys_to_pfn(EXYNOS4_PA_COMBINER
),
171 .virtual = (unsigned long)S5P_VA_GIC_CPU
,
172 .pfn
= __phys_to_pfn(EXYNOS4_PA_GIC_CPU
),
176 .virtual = (unsigned long)S5P_VA_GIC_DIST
,
177 .pfn
= __phys_to_pfn(EXYNOS4_PA_GIC_DIST
),
181 .virtual = (unsigned long)S3C_VA_UART
,
182 .pfn
= __phys_to_pfn(EXYNOS4_PA_UART
),
186 .virtual = (unsigned long)S5P_VA_CMU
,
187 .pfn
= __phys_to_pfn(EXYNOS4_PA_CMU
),
191 .virtual = (unsigned long)S5P_VA_COREPERI_BASE
,
192 .pfn
= __phys_to_pfn(EXYNOS4_PA_COREPERI
),
196 .virtual = (unsigned long)S5P_VA_L2CC
,
197 .pfn
= __phys_to_pfn(EXYNOS4_PA_L2CC
),
201 .virtual = (unsigned long)S5P_VA_DMC0
,
202 .pfn
= __phys_to_pfn(EXYNOS4_PA_DMC0
),
206 .virtual = (unsigned long)S5P_VA_DMC1
,
207 .pfn
= __phys_to_pfn(EXYNOS4_PA_DMC1
),
211 .virtual = (unsigned long)S3C_VA_USB_HSPHY
,
212 .pfn
= __phys_to_pfn(EXYNOS4_PA_HSPHY
),
218 static struct map_desc exynos4_iodesc0
[] __initdata
= {
220 .virtual = (unsigned long)S5P_VA_SYSRAM
,
221 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSRAM0
),
227 static struct map_desc exynos4_iodesc1
[] __initdata
= {
229 .virtual = (unsigned long)S5P_VA_SYSRAM
,
230 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSRAM1
),
236 static struct map_desc exynos5_iodesc
[] __initdata
= {
238 .virtual = (unsigned long)S3C_VA_SYS
,
239 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSCON
),
243 .virtual = (unsigned long)S3C_VA_TIMER
,
244 .pfn
= __phys_to_pfn(EXYNOS5_PA_TIMER
),
248 .virtual = (unsigned long)S3C_VA_WATCHDOG
,
249 .pfn
= __phys_to_pfn(EXYNOS5_PA_WATCHDOG
),
253 .virtual = (unsigned long)S5P_VA_SROMC
,
254 .pfn
= __phys_to_pfn(EXYNOS5_PA_SROMC
),
258 .virtual = (unsigned long)S5P_VA_SYSRAM
,
259 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSRAM
),
263 .virtual = (unsigned long)S5P_VA_CMU
,
264 .pfn
= __phys_to_pfn(EXYNOS5_PA_CMU
),
265 .length
= 144 * SZ_1K
,
268 .virtual = (unsigned long)S5P_VA_PMU
,
269 .pfn
= __phys_to_pfn(EXYNOS5_PA_PMU
),
273 .virtual = (unsigned long)S3C_VA_UART
,
274 .pfn
= __phys_to_pfn(EXYNOS5_PA_UART
),
280 static struct map_desc exynos5440_iodesc0
[] __initdata
= {
282 .virtual = (unsigned long)S3C_VA_UART
,
283 .pfn
= __phys_to_pfn(EXYNOS5440_PA_UART0
),
289 void exynos4_restart(char mode
, const char *cmd
)
291 __raw_writel(0x1, S5P_SWRESET
);
294 void exynos5_restart(char mode
, const char *cmd
)
296 struct device_node
*np
;
300 if (of_machine_is_compatible("samsung,exynos5250")) {
302 addr
= EXYNOS_SWRESET
;
303 } else if (of_machine_is_compatible("samsung,exynos5440")) {
304 np
= of_find_compatible_node(NULL
, NULL
, "samsung,exynos5440-clock");
305 addr
= of_iomap(np
, 0) + 0xcc;
306 val
= (0xfff << 20) | (0x1 << 16);
308 pr_err("%s: cannot support non-DT\n", __func__
);
312 __raw_writel(val
, addr
);
315 void __init
exynos_init_late(void)
317 if (of_machine_is_compatible("samsung,exynos5440"))
318 /* to be supported later */
321 exynos_pm_late_initcall();
327 * register the standard cpu IO areas
330 void __init
exynos_init_io(struct map_desc
*mach_desc
, int size
)
332 struct map_desc
*iodesc
= exynos_iodesc
;
333 int iodesc_sz
= ARRAY_SIZE(exynos_iodesc
);
334 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
335 unsigned long root
= of_get_flat_dt_root();
337 /* initialize the io descriptors we need for initialization */
338 if (of_flat_dt_is_compatible(root
, "samsung,exynos5440")) {
339 iodesc
= exynos5440_iodesc
;
340 iodesc_sz
= ARRAY_SIZE(exynos5440_iodesc
);
344 iotable_init(iodesc
, iodesc_sz
);
347 iotable_init(mach_desc
, size
);
349 /* detect cpu id and rev. */
350 s5p_init_cpu(S5P_VA_CHIPID
);
352 s3c_init_cpu(samsung_cpu_id
, cpu_ids
, ARRAY_SIZE(cpu_ids
));
355 static void __init
exynos4_map_io(void)
357 iotable_init(exynos4_iodesc
, ARRAY_SIZE(exynos4_iodesc
));
359 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0
)
360 iotable_init(exynos4_iodesc0
, ARRAY_SIZE(exynos4_iodesc0
));
362 iotable_init(exynos4_iodesc1
, ARRAY_SIZE(exynos4_iodesc1
));
364 /* initialize device information early */
365 exynos4_default_sdhci0();
366 exynos4_default_sdhci1();
367 exynos4_default_sdhci2();
368 exynos4_default_sdhci3();
370 s3c_adc_setname("samsung-adc-v3");
372 s3c_fimc_setname(0, "exynos4-fimc");
373 s3c_fimc_setname(1, "exynos4-fimc");
374 s3c_fimc_setname(2, "exynos4-fimc");
375 s3c_fimc_setname(3, "exynos4-fimc");
377 s3c_sdhci_setname(0, "exynos4-sdhci");
378 s3c_sdhci_setname(1, "exynos4-sdhci");
379 s3c_sdhci_setname(2, "exynos4-sdhci");
380 s3c_sdhci_setname(3, "exynos4-sdhci");
382 /* The I2C bus controllers are directly compatible with s3c2440 */
383 s3c_i2c0_setname("s3c2440-i2c");
384 s3c_i2c1_setname("s3c2440-i2c");
385 s3c_i2c2_setname("s3c2440-i2c");
387 s5p_fb_setname(0, "exynos4-fb");
388 s5p_hdmi_setname("exynos4-hdmi");
390 s3c64xx_spi_setname("exynos4210-spi");
393 static void __init
exynos5_map_io(void)
395 iotable_init(exynos5_iodesc
, ARRAY_SIZE(exynos5_iodesc
));
398 static void __init
exynos5440_map_io(void)
400 iotable_init(exynos5440_iodesc0
, ARRAY_SIZE(exynos5440_iodesc0
));
403 void __init
exynos_init_time(void)
405 if (of_have_populated_dt()) {
408 clocksource_of_init();
411 /* todo: remove after migrating legacy E4 platforms to dt */
412 #ifdef CONFIG_ARCH_EXYNOS4
413 exynos4_clk_init(NULL
);
414 exynos4_clk_register_fixed_ext(xxti_f
, xusbxti_f
);
420 void __init
exynos4_init_irq(void)
422 unsigned int gic_bank_offset
;
424 gic_bank_offset
= soc_is_exynos4412() ? 0x4000 : 0x8000;
426 if (!of_have_populated_dt())
427 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST
, S5P_VA_GIC_CPU
, gic_bank_offset
, NULL
);
433 if (!of_have_populated_dt())
434 combiner_init(S5P_VA_COMBINER_BASE
, NULL
);
437 * The parameters of s5p_init_irq() are for VIC init.
438 * Theses parameters should be NULL and 0 because EXYNOS4
439 * uses GIC instead of VIC.
441 s5p_init_irq(NULL
, 0);
444 void __init
exynos5_init_irq(void)
450 * The parameters of s5p_init_irq() are for VIC init.
451 * Theses parameters should be NULL and 0 because EXYNOS4
452 * uses GIC instead of VIC.
454 if (!of_machine_is_compatible("samsung,exynos5440"))
455 s5p_init_irq(NULL
, 0);
457 gic_arch_extn
.irq_set_wake
= s3c_irq_wake
;
460 struct bus_type exynos_subsys
= {
461 .name
= "exynos-core",
462 .dev_name
= "exynos-core",
465 static struct device exynos4_dev
= {
466 .bus
= &exynos_subsys
,
469 static int __init
exynos_core_init(void)
471 return subsys_system_register(&exynos_subsys
, NULL
);
473 core_initcall(exynos_core_init
);
475 #ifdef CONFIG_CACHE_L2X0
476 static int __init
exynos4_l2x0_cache_init(void)
480 if (soc_is_exynos5250() || soc_is_exynos5440())
483 ret
= l2x0_of_init(L2_AUX_VAL
, L2_AUX_MASK
);
485 l2x0_regs_phys
= virt_to_phys(&l2x0_saved_regs
);
486 clean_dcache_area(&l2x0_regs_phys
, sizeof(unsigned long));
490 if (!(__raw_readl(S5P_VA_L2CC
+ L2X0_CTRL
) & 0x1)) {
491 l2x0_saved_regs
.phy_base
= EXYNOS4_PA_L2CC
;
492 /* TAG, Data Latency Control: 2 cycles */
493 l2x0_saved_regs
.tag_latency
= 0x110;
495 if (soc_is_exynos4212() || soc_is_exynos4412())
496 l2x0_saved_regs
.data_latency
= 0x120;
498 l2x0_saved_regs
.data_latency
= 0x110;
500 l2x0_saved_regs
.prefetch_ctrl
= 0x30000007;
501 l2x0_saved_regs
.pwr_ctrl
=
502 (L2X0_DYNAMIC_CLK_GATING_EN
| L2X0_STNDBY_MODE_EN
);
504 l2x0_regs_phys
= virt_to_phys(&l2x0_saved_regs
);
506 __raw_writel(l2x0_saved_regs
.tag_latency
,
507 S5P_VA_L2CC
+ L2X0_TAG_LATENCY_CTRL
);
508 __raw_writel(l2x0_saved_regs
.data_latency
,
509 S5P_VA_L2CC
+ L2X0_DATA_LATENCY_CTRL
);
511 /* L2X0 Prefetch Control */
512 __raw_writel(l2x0_saved_regs
.prefetch_ctrl
,
513 S5P_VA_L2CC
+ L2X0_PREFETCH_CTRL
);
515 /* L2X0 Power Control */
516 __raw_writel(l2x0_saved_regs
.pwr_ctrl
,
517 S5P_VA_L2CC
+ L2X0_POWER_CTRL
);
519 clean_dcache_area(&l2x0_regs_phys
, sizeof(unsigned long));
520 clean_dcache_area(&l2x0_saved_regs
, sizeof(struct l2x0_regs
));
523 l2x0_init(S5P_VA_L2CC
, L2_AUX_VAL
, L2_AUX_MASK
);
526 early_initcall(exynos4_l2x0_cache_init
);
529 static int __init
exynos_init(void)
531 printk(KERN_INFO
"EXYNOS: Initializing architecture\n");
533 return device_register(&exynos4_dev
);
536 /* uart registration process */
538 static void __init
exynos4_init_uarts(struct s3c2410_uartcfg
*cfg
, int no
)
540 struct s3c2410_uartcfg
*tcfg
= cfg
;
543 for (ucnt
= 0; ucnt
< no
; ucnt
++, tcfg
++)
544 tcfg
->has_fracval
= 1;
546 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources
, cfg
, no
);
549 static void __iomem
*exynos_eint_base
;
551 static DEFINE_SPINLOCK(eint_lock
);
553 static unsigned int eint0_15_data
[16];
555 static inline int exynos4_irq_to_gpio(unsigned int irq
)
557 if (irq
< IRQ_EINT(0))
562 return EXYNOS4_GPX0(irq
);
566 return EXYNOS4_GPX1(irq
);
570 return EXYNOS4_GPX2(irq
);
574 return EXYNOS4_GPX3(irq
);
579 static inline int exynos5_irq_to_gpio(unsigned int irq
)
581 if (irq
< IRQ_EINT(0))
586 return EXYNOS5_GPX0(irq
);
590 return EXYNOS5_GPX1(irq
);
594 return EXYNOS5_GPX2(irq
);
598 return EXYNOS5_GPX3(irq
);
603 static unsigned int exynos4_eint0_15_src_int
[16] = {
622 static unsigned int exynos5_eint0_15_src_int
[16] = {
640 static inline void exynos_irq_eint_mask(struct irq_data
*data
)
644 spin_lock(&eint_lock
);
645 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, data
->irq
));
646 mask
|= EINT_OFFSET_BIT(data
->irq
);
647 __raw_writel(mask
, EINT_MASK(exynos_eint_base
, data
->irq
));
648 spin_unlock(&eint_lock
);
651 static void exynos_irq_eint_unmask(struct irq_data
*data
)
655 spin_lock(&eint_lock
);
656 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, data
->irq
));
657 mask
&= ~(EINT_OFFSET_BIT(data
->irq
));
658 __raw_writel(mask
, EINT_MASK(exynos_eint_base
, data
->irq
));
659 spin_unlock(&eint_lock
);
662 static inline void exynos_irq_eint_ack(struct irq_data
*data
)
664 __raw_writel(EINT_OFFSET_BIT(data
->irq
),
665 EINT_PEND(exynos_eint_base
, data
->irq
));
668 static void exynos_irq_eint_maskack(struct irq_data
*data
)
670 exynos_irq_eint_mask(data
);
671 exynos_irq_eint_ack(data
);
674 static int exynos_irq_eint_set_type(struct irq_data
*data
, unsigned int type
)
676 int offs
= EINT_OFFSET(data
->irq
);
682 case IRQ_TYPE_EDGE_RISING
:
683 newvalue
= S5P_IRQ_TYPE_EDGE_RISING
;
686 case IRQ_TYPE_EDGE_FALLING
:
687 newvalue
= S5P_IRQ_TYPE_EDGE_FALLING
;
690 case IRQ_TYPE_EDGE_BOTH
:
691 newvalue
= S5P_IRQ_TYPE_EDGE_BOTH
;
694 case IRQ_TYPE_LEVEL_LOW
:
695 newvalue
= S5P_IRQ_TYPE_LEVEL_LOW
;
698 case IRQ_TYPE_LEVEL_HIGH
:
699 newvalue
= S5P_IRQ_TYPE_LEVEL_HIGH
;
703 printk(KERN_ERR
"No such irq type %d", type
);
707 shift
= (offs
& 0x7) * 4;
710 spin_lock(&eint_lock
);
711 ctrl
= __raw_readl(EINT_CON(exynos_eint_base
, data
->irq
));
713 ctrl
|= newvalue
<< shift
;
714 __raw_writel(ctrl
, EINT_CON(exynos_eint_base
, data
->irq
));
715 spin_unlock(&eint_lock
);
717 if (soc_is_exynos5250())
718 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data
->irq
), S3C_GPIO_SFN(0xf));
720 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data
->irq
), S3C_GPIO_SFN(0xf));
725 static struct irq_chip exynos_irq_eint
= {
726 .name
= "exynos-eint",
727 .irq_mask
= exynos_irq_eint_mask
,
728 .irq_unmask
= exynos_irq_eint_unmask
,
729 .irq_mask_ack
= exynos_irq_eint_maskack
,
730 .irq_ack
= exynos_irq_eint_ack
,
731 .irq_set_type
= exynos_irq_eint_set_type
,
733 .irq_set_wake
= s3c_irqext_wake
,
738 * exynos4_irq_demux_eint
740 * This function demuxes the IRQ from from EINTs 16 to 31.
741 * It is designed to be inlined into the specific handler
742 * s5p_irq_demux_eintX_Y.
744 * Each EINT pend/mask registers handle eight of them.
746 static inline void exynos_irq_demux_eint(unsigned int start
)
750 u32 status
= __raw_readl(EINT_PEND(exynos_eint_base
, start
));
751 u32 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, start
));
757 irq
= fls(status
) - 1;
758 generic_handle_irq(irq
+ start
);
759 status
&= ~(1 << irq
);
763 static void exynos_irq_demux_eint16_31(unsigned int irq
, struct irq_desc
*desc
)
765 struct irq_chip
*chip
= irq_get_chip(irq
);
766 chained_irq_enter(chip
, desc
);
767 exynos_irq_demux_eint(IRQ_EINT(16));
768 exynos_irq_demux_eint(IRQ_EINT(24));
769 chained_irq_exit(chip
, desc
);
772 static void exynos_irq_eint0_15(unsigned int irq
, struct irq_desc
*desc
)
774 u32
*irq_data
= irq_get_handler_data(irq
);
775 struct irq_chip
*chip
= irq_get_chip(irq
);
777 chained_irq_enter(chip
, desc
);
778 generic_handle_irq(*irq_data
);
779 chained_irq_exit(chip
, desc
);
782 static int __init
exynos_init_irq_eint(void)
786 #ifdef CONFIG_PINCTRL_SAMSUNG
788 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
789 * functionality along with support for external gpio and wakeup
790 * interrupts. If the samsung pinctrl driver is enabled and includes
791 * the wakeup interrupt support, then the setting up external wakeup
792 * interrupts here can be skipped. This check here is temporary to
793 * allow exynos4 platforms that do not use Samsung pinctrl driver to
794 * co-exist with platforms that do. When all of the Samsung Exynos4
795 * platforms switch over to using the pinctrl driver, the wakeup
796 * interrupt support code here can be completely removed.
798 static const struct of_device_id exynos_pinctrl_ids
[] = {
799 { .compatible
= "samsung,exynos4210-pinctrl", },
800 { .compatible
= "samsung,exynos4x12-pinctrl", },
801 { .compatible
= "samsung,exynos5250-pinctrl", },
803 struct device_node
*pctrl_np
, *wkup_np
;
804 const char *wkup_compat
= "samsung,exynos4210-wakeup-eint";
806 for_each_matching_node(pctrl_np
, exynos_pinctrl_ids
) {
807 if (of_device_is_available(pctrl_np
)) {
808 wkup_np
= of_find_compatible_node(pctrl_np
, NULL
,
815 if (soc_is_exynos5440())
818 if (soc_is_exynos5250())
819 exynos_eint_base
= ioremap(EXYNOS5_PA_GPIO1
, SZ_4K
);
821 exynos_eint_base
= ioremap(EXYNOS4_PA_GPIO2
, SZ_4K
);
823 if (exynos_eint_base
== NULL
) {
824 pr_err("unable to ioremap for EINT base address\n");
828 for (irq
= 0 ; irq
<= 31 ; irq
++) {
829 irq_set_chip_and_handler(IRQ_EINT(irq
), &exynos_irq_eint
,
831 set_irq_flags(IRQ_EINT(irq
), IRQF_VALID
);
834 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31
, exynos_irq_demux_eint16_31
);
836 for (irq
= 0 ; irq
<= 15 ; irq
++) {
837 eint0_15_data
[irq
] = IRQ_EINT(irq
);
839 if (soc_is_exynos5250()) {
840 irq_set_handler_data(exynos5_eint0_15_src_int
[irq
],
841 &eint0_15_data
[irq
]);
842 irq_set_chained_handler(exynos5_eint0_15_src_int
[irq
],
843 exynos_irq_eint0_15
);
845 irq_set_handler_data(exynos4_eint0_15_src_int
[irq
],
846 &eint0_15_data
[irq
]);
847 irq_set_chained_handler(exynos4_eint0_15_src_int
[irq
],
848 exynos_irq_eint0_15
);
854 arch_initcall(exynos_init_irq_eint
);
856 static struct resource exynos4_pmu_resource
[] = {
857 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU
),
858 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1
),
859 #if defined(CONFIG_SOC_EXYNOS4412)
860 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2
),
861 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3
),
865 static struct platform_device exynos4_device_pmu
= {
867 .num_resources
= ARRAY_SIZE(exynos4_pmu_resource
),
868 .resource
= exynos4_pmu_resource
,
871 static int __init
exynos_armpmu_init(void)
873 if (!of_have_populated_dt()) {
874 if (soc_is_exynos4210() || soc_is_exynos4212())
875 exynos4_device_pmu
.num_resources
= 2;
876 platform_device_register(&exynos4_device_pmu
);
881 arch_initcall(exynos_armpmu_init
);