arch/arm/mach-at91/at91sam9261.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9261.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91sam9261.h>
  22 #include <mach/at91_pmc.h>
  23
  24 #include "at91_aic.h"
  25 #include "at91_rstc.h"
  26 #include "soc.h"
  27 #include "generic.h"
  28 #include "clock.h"
  29 #include "sam9_smc.h"
  30
  31 /* --------------------------------------------------------------------
  32  *  Clocks
  33  * -------------------------------------------------------------------- */
  34
  35 /*
  36  * The peripheral clocks.
  37  */
  38 static struct clk pioA_clk = {
  39         .name           = "pioA_clk",
  40         .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
  41         .type           = CLK_TYPE_PERIPHERAL,
  42 };
  43 static struct clk pioB_clk = {
  44         .name           = "pioB_clk",
  45         .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
  46         .type           = CLK_TYPE_PERIPHERAL,
  47 };
  48 static struct clk pioC_clk = {
  49         .name           = "pioC_clk",
  50         .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk usart0_clk = {
  54         .name           = "usart0_clk",
  55         .pmc_mask       = 1 << AT91SAM9261_ID_US0,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk usart1_clk = {
  59         .name           = "usart1_clk",
  60         .pmc_mask       = 1 << AT91SAM9261_ID_US1,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk usart2_clk = {
  64         .name           = "usart2_clk",
  65         .pmc_mask       = 1 << AT91SAM9261_ID_US2,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk mmc_clk = {
  69         .name           = "mci_clk",
  70         .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk udc_clk = {
  74         .name           = "udc_clk",
  75         .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk twi_clk = {
  79         .name           = "twi_clk",
  80         .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk spi0_clk = {
  84         .name           = "spi0_clk",
  85         .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk spi1_clk = {
  89         .name           = "spi1_clk",
  90         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk ssc0_clk = {
  94         .name           = "ssc0_clk",
  95         .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk ssc1_clk = {
  99         .name           = "ssc1_clk",
 100         .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk ssc2_clk = {
 104         .name           = "ssc2_clk",
 105         .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk tc0_clk = {
 109         .name           = "tc0_clk",
 110         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk tc1_clk = {
 114         .name           = "tc1_clk",
 115         .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk tc2_clk = {
 119         .name           = "tc2_clk",
 120         .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk ohci_clk = {
 124         .name           = "ohci_clk",
 125         .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk lcdc_clk = {
 129         .name           = "lcdc_clk",
 130         .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133
 134 /* HClocks */
 135 static struct clk hck0 = {
 136         .name           = "hck0",
 137         .pmc_mask       = AT91_PMC_HCK0,
 138         .type           = CLK_TYPE_SYSTEM,
 139         .id             = 0,
 140 };
 141 static struct clk hck1 = {
 142         .name           = "hck1",
 143         .pmc_mask       = AT91_PMC_HCK1,
 144         .type           = CLK_TYPE_SYSTEM,
 145         .id             = 1,
 146 };
 147
 148 static struct clk *periph_clocks[] __initdata = {
 149         &pioA_clk,
 150         &pioB_clk,
 151         &pioC_clk,
 152         &usart0_clk,
 153         &usart1_clk,
 154         &usart2_clk,
 155         &mmc_clk,
 156         &udc_clk,
 157         &twi_clk,
 158         &spi0_clk,
 159         &spi1_clk,
 160         &ssc0_clk,
 161         &ssc1_clk,
 162         &ssc2_clk,
 163         &tc0_clk,
 164         &tc1_clk,
 165         &tc2_clk,
 166         &ohci_clk,
 167         &lcdc_clk,
 168         // irq0 .. irq2
 169 };
 170
 171 static struct clk_lookup periph_clocks_lookups[] = {
 172         CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
 173         CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
 174         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 175         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 176         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 177         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 178         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 179         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
 180         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
 181         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
 182         CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
 183         CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
 184         CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
 185         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
 186         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
 187         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
 188         CLKDEV_CON_ID("pioA", &pioA_clk),
 189         CLKDEV_CON_ID("pioB", &pioB_clk),
 190         CLKDEV_CON_ID("pioC", &pioC_clk),
 191 };
 192
 193 static struct clk_lookup usart_clocks_lookups[] = {
 194         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 195         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 196         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 197         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 198 };
 199
 200 /*
 201  * The four programmable clocks.
 202  * You must configure pin multiplexing to bring these signals out.
 203  */
 204 static struct clk pck0 = {
 205         .name           = "pck0",
 206         .pmc_mask       = AT91_PMC_PCK0,
 207         .type           = CLK_TYPE_PROGRAMMABLE,
 208         .id             = 0,
 209 };
 210 static struct clk pck1 = {
 211         .name           = "pck1",
 212         .pmc_mask       = AT91_PMC_PCK1,
 213         .type           = CLK_TYPE_PROGRAMMABLE,
 214         .id             = 1,
 215 };
 216 static struct clk pck2 = {
 217         .name           = "pck2",
 218         .pmc_mask       = AT91_PMC_PCK2,
 219         .type           = CLK_TYPE_PROGRAMMABLE,
 220         .id             = 2,
 221 };
 222 static struct clk pck3 = {
 223         .name           = "pck3",
 224         .pmc_mask       = AT91_PMC_PCK3,
 225         .type           = CLK_TYPE_PROGRAMMABLE,
 226         .id             = 3,
 227 };
 228
 229 static void __init at91sam9261_register_clocks(void)
 230 {
 231         int i;
 232
 233         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 234                 clk_register(periph_clocks[i]);
 235
 236         clkdev_add_table(periph_clocks_lookups,
 237                          ARRAY_SIZE(periph_clocks_lookups));
 238         clkdev_add_table(usart_clocks_lookups,
 239                          ARRAY_SIZE(usart_clocks_lookups));
 240
 241         clk_register(&pck0);
 242         clk_register(&pck1);
 243         clk_register(&pck2);
 244         clk_register(&pck3);
 245
 246         clk_register(&hck0);
 247         clk_register(&hck1);
 248 }
 249
 250 /* --------------------------------------------------------------------
 251  *  GPIO
 252  * -------------------------------------------------------------------- */
 253
 254 static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
 255         {
 256                 .id             = AT91SAM9261_ID_PIOA,
 257                 .regbase        = AT91SAM9261_BASE_PIOA,
 258         }, {
 259                 .id             = AT91SAM9261_ID_PIOB,
 260                 .regbase        = AT91SAM9261_BASE_PIOB,
 261         }, {
 262                 .id             = AT91SAM9261_ID_PIOC,
 263                 .regbase        = AT91SAM9261_BASE_PIOC,
 264         }
 265 };
 266
 267 /* --------------------------------------------------------------------
 268  *  AT91SAM9261 processor initialization
 269  * -------------------------------------------------------------------- */
 270
 271 static void __init at91sam9261_map_io(void)
 272 {
 273         if (cpu_is_at91sam9g10())
 274                 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
 275         else
 276                 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 277 }
 278
 279 static void __init at91sam9261_ioremap_registers(void)
 280 {
 281         at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
 282         at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
 283         at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
 284         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
 285         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 286         at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 287 }
 288
 289 static void __init at91sam9261_initialize(void)
 290 {
 291         arm_pm_idle = at91sam9_idle;
 292         arm_pm_restart = at91sam9_alt_restart;
 293         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
 294                         | (1 << AT91SAM9261_ID_IRQ2);
 295
 296         /* Register GPIO subsystem */
 297         at91_gpio_init(at91sam9261_gpio, 3);
 298 }
 299
 300 /* --------------------------------------------------------------------
 301  *  Interrupt initialization
 302  * -------------------------------------------------------------------- */
 303
 304 /*
 305  * The default interrupt priority levels (0 = lowest, 7 = highest).
 306  */
 307 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 308         7,      /* Advanced Interrupt Controller */
 309         7,      /* System Peripherals */
 310         1,      /* Parallel IO Controller A */
 311         1,      /* Parallel IO Controller B */
 312         1,      /* Parallel IO Controller C */
 313         0,
 314         5,      /* USART 0 */
 315         5,      /* USART 1 */
 316         5,      /* USART 2 */
 317         0,      /* Multimedia Card Interface */
 318         2,      /* USB Device Port */
 319         6,      /* Two-Wire Interface */
 320         5,      /* Serial Peripheral Interface 0 */
 321         5,      /* Serial Peripheral Interface 1 */
 322         4,      /* Serial Synchronous Controller 0 */
 323         4,      /* Serial Synchronous Controller 1 */
 324         4,      /* Serial Synchronous Controller 2 */
 325         0,      /* Timer Counter 0 */
 326         0,      /* Timer Counter 1 */
 327         0,      /* Timer Counter 2 */
 328         2,      /* USB Host port */
 329         3,      /* LCD Controller */
 330         0,
 331         0,
 332         0,
 333         0,
 334         0,
 335         0,
 336         0,
 337         0,      /* Advanced Interrupt Controller */
 338         0,      /* Advanced Interrupt Controller */
 339         0,      /* Advanced Interrupt Controller */
 340 };
 341
 342 AT91_SOC_START(at91sam9261)
 343         .map_io = at91sam9261_map_io,
 344         .default_irq_priority = at91sam9261_default_irq_priority,
 345         .ioremap_registers = at91sam9261_ioremap_registers,
 346         .register_clocks = at91sam9261_register_clocks,
 347         .init = at91sam9261_initialize,
 348 AT91_SOC_END