import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / kernel / smp_tlb.c
1 /*
2 * linux/arch/arm/kernel/smp_tlb.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/preempt.h>
11 #include <linux/smp.h>
12
13 #include <asm/smp_plat.h>
14 #include <asm/tlbflush.h>
15 #include <asm/mmu_context.h>
16
17 /**********************************************************************/
18
19 /*
20 * TLB operations
21 */
22 struct tlb_args {
23 struct vm_area_struct *ta_vma;
24 unsigned long ta_start;
25 unsigned long ta_end;
26 };
27
28 static inline void ipi_flush_tlb_all(void *ignored)
29 {
30 local_flush_tlb_all();
31 }
32
33 static inline void ipi_flush_tlb_mm(void *arg)
34 {
35 struct mm_struct *mm = (struct mm_struct *)arg;
36
37 local_flush_tlb_mm(mm);
38 }
39
40 static inline void ipi_flush_tlb_page(void *arg)
41 {
42 struct tlb_args *ta = (struct tlb_args *)arg;
43
44 local_flush_tlb_page(ta->ta_vma, ta->ta_start);
45 }
46
47 static inline void ipi_flush_tlb_kernel_page(void *arg)
48 {
49 struct tlb_args *ta = (struct tlb_args *)arg;
50
51 local_flush_tlb_kernel_page(ta->ta_start);
52 }
53
54 static inline void ipi_flush_tlb_range(void *arg)
55 {
56 struct tlb_args *ta = (struct tlb_args *)arg;
57
58 local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
59 }
60
61 static inline void ipi_flush_tlb_kernel_range(void *arg)
62 {
63 struct tlb_args *ta = (struct tlb_args *)arg;
64
65 local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
66 }
67
68 static inline void ipi_flush_bp_all(void *ignored)
69 {
70 local_flush_bp_all();
71 }
72
73 #ifdef CONFIG_ARM_ERRATA_798181
74 bool (*erratum_a15_798181_handler)(void);
75
76 static bool erratum_a15_798181_partial(void)
77 {
78 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
79 dsb();
80 return false;
81 }
82
83 static bool erratum_a15_798181_broadcast(void)
84 {
85 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
86 dsb();
87 return true;
88 }
89
90 void erratum_a15_798181_init(void)
91 {
92 unsigned int midr = read_cpuid_id();
93 unsigned int revidr = read_cpuid(CPUID_REVIDR);
94
95 if (erratum_a15_798181_handler == erratum_a15_798181_broadcast)
96 return;
97
98 /* Cortex-A15 r0p0..r3p2 w/o ECO fix affected */
99 if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2 ||
100 (revidr & 0x210) == 0x210) {
101 return;
102 }
103 if (revidr & 0x10)
104 erratum_a15_798181_handler = erratum_a15_798181_partial;
105 else
106 erratum_a15_798181_handler = erratum_a15_798181_broadcast;
107 }
108 #endif
109
110 static void ipi_flush_tlb_a15_erratum(void *arg)
111 {
112 dmb();
113 }
114
115 static void broadcast_tlb_a15_erratum(void)
116 {
117 if (!erratum_a15_798181())
118 return;
119
120 smp_call_function(ipi_flush_tlb_a15_erratum, NULL, 1);
121 }
122
123 static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
124 {
125 int this_cpu;
126 cpumask_t mask = { CPU_BITS_NONE };
127
128 if (!erratum_a15_798181())
129 return;
130
131 this_cpu = get_cpu();
132 a15_erratum_get_cpumask(this_cpu, mm, &mask);
133 smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
134 put_cpu();
135 }
136
137 void flush_tlb_all(void)
138 {
139 if (tlb_ops_need_broadcast())
140 on_each_cpu(ipi_flush_tlb_all, NULL, 1);
141 else
142 local_flush_tlb_all();
143 broadcast_tlb_a15_erratum();
144 }
145
146 void flush_tlb_mm(struct mm_struct *mm)
147 {
148 if (tlb_ops_need_broadcast())
149 on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
150 else
151 local_flush_tlb_mm(mm);
152 broadcast_tlb_mm_a15_erratum(mm);
153 }
154
155 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
156 {
157 if (tlb_ops_need_broadcast()) {
158 struct tlb_args ta;
159 ta.ta_vma = vma;
160 ta.ta_start = uaddr;
161 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page,
162 &ta, 1);
163 } else
164 local_flush_tlb_page(vma, uaddr);
165 broadcast_tlb_mm_a15_erratum(vma->vm_mm);
166 }
167
168 void flush_tlb_kernel_page(unsigned long kaddr)
169 {
170 if (tlb_ops_need_broadcast()) {
171 struct tlb_args ta;
172 ta.ta_start = kaddr;
173 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
174 } else
175 local_flush_tlb_kernel_page(kaddr);
176 broadcast_tlb_a15_erratum();
177 }
178
179 void flush_tlb_range(struct vm_area_struct *vma,
180 unsigned long start, unsigned long end)
181 {
182 if (tlb_ops_need_broadcast()) {
183 struct tlb_args ta;
184 ta.ta_vma = vma;
185 ta.ta_start = start;
186 ta.ta_end = end;
187 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range,
188 &ta, 1);
189 } else
190 local_flush_tlb_range(vma, start, end);
191 broadcast_tlb_mm_a15_erratum(vma->vm_mm);
192 }
193
194 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
195 {
196 if (tlb_ops_need_broadcast()) {
197 struct tlb_args ta;
198 ta.ta_start = start;
199 ta.ta_end = end;
200 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
201 } else
202 local_flush_tlb_kernel_range(start, end);
203 broadcast_tlb_a15_erratum();
204 }
205
206 void flush_bp_all(void)
207 {
208 if (tlb_ops_need_broadcast())
209 on_each_cpu(ipi_flush_bp_all, NULL, 1);
210 else
211 local_flush_bp_all();
212 }