arch/arm/kernel/head.S

   1 /*
   2  *  linux/arch/arm/kernel/head.S
   3  *
   4  *  Copyright (C) 1994-2002 Russell King
   5  *  Copyright (c) 2003 ARM Limited
   6  *  All Rights Reserved
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  *  Kernel startup code for all 32-bit CPUs
  13  */
  14 #include <linux/linkage.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/assembler.h>
  18 #include <asm/cp15.h>
  19 #include <asm/domain.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/asm-offsets.h>
  22 #include <asm/memory.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/pgtable.h>
  25
  26 #ifdef CONFIG_DEBUG_LL
  27 #include <mach/debug-macro.S>
  28 #endif
  29
  30 /*
  31  * swapper_pg_dir is the virtual address of the initial page table.
  32  * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
  33  * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
  34  * the least significant 16 bits to be 0x8000, but we could probably
  35  * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
  36  */
  37 #define KERNEL_RAM_VADDR        (PAGE_OFFSET + TEXT_OFFSET)
  38 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
  39 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
  40 #endif
  41
  42 #ifdef CONFIG_ARM_LPAE
  43         /* LPAE requires an additional page for the PGD */
  44 #define PG_DIR_SIZE     0x5000
  45 #define PMD_ORDER       3
  46 #else
  47 #define PG_DIR_SIZE     0x4000
  48 #define PMD_ORDER       2
  49 #endif
  50
  51         .globl  swapper_pg_dir
  52         .equ    swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
  53
  54         .macro  pgtbl, rd, phys
  55         add     \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
  56         .endm
  57
  58 /*
  59  * Kernel startup entry point.
  60  * ---------------------------
  61  *
  62  * This is normally called from the decompressor code.  The requirements
  63  * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
  64  * r1 = machine nr, r2 = atags or dtb pointer.
  65  *
  66  * This code is mostly position independent, so if you link the kernel at
  67  * 0xc0008000, you call this at __pa(0xc0008000).
  68  *
  69  * See linux/arch/arm/tools/mach-types for the complete list of machine
  70  * numbers for r1.
  71  *
  72  * We're trying to keep crap to a minimum; DO NOT add any machine specific
  73  * crap here - that's what the boot loader (or in extreme, well justified
  74  * circumstances, zImage) is for.
  75  */
  76         .arm
  77
  78         __HEAD
  79 ENTRY(stext)
  80
  81  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
  82  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
  83  THUMB( .thumb                  )       @ switch to Thumb now.
  84  THUMB(1:                       )
  85
  86         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
  87                                                 @ and irqs disabled
  88         mrc     p15, 0, r9, c0, c0              @ get processor id
  89         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
  90         movs    r10, r5                         @ invalid processor (r5=0)?
  91  THUMB( it      eq )            @ force fixup-able long branch encoding
  92         beq     __error_p                       @ yes, error 'p'
  93
  94 #ifdef CONFIG_ARM_LPAE
  95         mrc     p15, 0, r3, c0, c1, 4           @ read ID_MMFR0
  96         and     r3, r3, #0xf                    @ extract VMSA support
  97         cmp     r3, #5                          @ long-descriptor translation table format?
  98  THUMB( it      lo )                            @ force fixup-able long branch encoding
  99         blo     __error_p                       @ only classic page table format
 100 #endif
 101
 102 #ifndef CONFIG_XIP_KERNEL
 103         adr     r3, 2f
 104         ldmia   r3, {r4, r8}
 105         sub     r4, r3, r4                      @ (PHYS_OFFSET - PAGE_OFFSET)
 106         add     r8, r8, r4                      @ PHYS_OFFSET
 107 #else
 108         ldr     r8, =PHYS_OFFSET                @ always constant in this case
 109 #endif
 110
 111         /*
 112          * r1 = machine no, r2 = atags or dtb,
 113          * r8 = phys_offset, r9 = cpuid, r10 = procinfo
 114          */
 115         bl      __vet_atags
 116 #ifdef CONFIG_SMP_ON_UP
 117         bl      __fixup_smp
 118 #endif
 119 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 120         bl      __fixup_pv_table
 121 #endif
 122         bl      __create_page_tables
 123
 124         /*
 125          * The following calls CPU specific code in a position independent
 126          * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
 127          * xxx_proc_info structure selected by __lookup_processor_type
 128          * above.  On return, the CPU will be ready for the MMU to be
 129          * turned on, and r0 will hold the CPU control register value.
 130          */
 131         ldr     r13, =__mmap_switched           @ address to jump to after
 132                                                 @ mmu has been enabled
 133         adr     lr, BSYM(1f)                    @ return (PIC) address
 134         mov     r8, r4                          @ set TTBR1 to swapper_pg_dir
 135  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
 136  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 137  THUMB( mov     pc, r12                         )
 138 1:      b       __enable_mmu
 139 ENDPROC(stext)
 140         .ltorg
 141 #ifndef CONFIG_XIP_KERNEL
 142 2:      .long   .
 143         .long   PAGE_OFFSET
 144 #endif
 145
 146 /*
 147  * Setup the initial page tables.  We only setup the barest
 148  * amount which are required to get the kernel running, which
 149  * generally means mapping in the kernel code.
 150  *
 151  * r8 = phys_offset, r9 = cpuid, r10 = procinfo
 152  *
 153  * Returns:
 154  *  r0, r3, r5-r7 corrupted
 155  *  r4 = physical page table address
 156  */
 157 __create_page_tables:
 158         pgtbl   r4, r8                          @ page table address
 159
 160         /*
 161          * Clear the swapper page table
 162          */
 163         mov     r0, r4
 164         mov     r3, #0
 165         add     r6, r0, #PG_DIR_SIZE
 166 1:      str     r3, [r0], #4
 167         str     r3, [r0], #4
 168         str     r3, [r0], #4
 169         str     r3, [r0], #4
 170         teq     r0, r6
 171         bne     1b
 172
 173 #ifdef CONFIG_ARM_LPAE
 174         /*
 175          * Build the PGD table (first level) to point to the PMD table. A PGD
 176          * entry is 64-bit wide.
 177          */
 178         mov     r0, r4
 179         add     r3, r4, #0x1000                 @ first PMD table address
 180         orr     r3, r3, #3                      @ PGD block type
 181         mov     r6, #4                          @ PTRS_PER_PGD
 182         mov     r7, #1 << (55 - 32)             @ L_PGD_SWAPPER
 183 1:      str     r3, [r0], #4                    @ set bottom PGD entry bits
 184         str     r7, [r0], #4                    @ set top PGD entry bits
 185         add     r3, r3, #0x1000                 @ next PMD table
 186         subs    r6, r6, #1
 187         bne     1b
 188
 189         add     r4, r4, #0x1000                 @ point to the PMD tables
 190 #endif
 191
 192         ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 193
 194         /*
 195          * Create identity mapping to cater for __enable_mmu.
 196          * This identity mapping will be removed by paging_init().
 197          */
 198         adr     r0, __turn_mmu_on_loc
 199         ldmia   r0, {r3, r5, r6}
 200         sub     r0, r0, r3                      @ virt->phys offset
 201         add     r5, r5, r0                      @ phys __turn_mmu_on
 202         add     r6, r6, r0                      @ phys __turn_mmu_on_end
 203         mov     r5, r5, lsr #SECTION_SHIFT
 204         mov     r6, r6, lsr #SECTION_SHIFT
 205
 206 1:      orr     r3, r7, r5, lsl #SECTION_SHIFT  @ flags + kernel base
 207         str     r3, [r4, r5, lsl #PMD_ORDER]    @ identity mapping
 208         cmp     r5, r6
 209         addlo   r5, r5, #1                      @ next section
 210         blo     1b
 211
 212         /*
 213          * Map our RAM from the start to the end of the kernel .bss section.
 214          */
 215         add     r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
 216         ldr     r6, =(_end - 1)
 217         orr     r3, r8, r7
 218         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 219 1:      str     r3, [r0], #1 << PMD_ORDER
 220         add     r3, r3, #1 << SECTION_SHIFT
 221         cmp     r0, r6
 222         bls     1b
 223
 224 #ifdef CONFIG_XIP_KERNEL
 225         /*
 226          * Map the kernel image separately as it is not located in RAM.
 227          */
 228 #define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
 229         mov     r3, pc
 230         mov     r3, r3, lsr #SECTION_SHIFT
 231         orr     r3, r7, r3, lsl #SECTION_SHIFT
 232         add     r0, r4,  #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
 233         str     r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
 234         ldr     r6, =(_edata_loc - 1)
 235         add     r0, r0, #1 << PMD_ORDER
 236         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 237 1:      cmp     r0, r6
 238         add     r3, r3, #1 << SECTION_SHIFT
 239         strls   r3, [r0], #1 << PMD_ORDER
 240         bls     1b
 241 #endif
 242
 243         /*
 244          * Then map boot params address in r2 if specified.
 245          */
 246         mov     r0, r2, lsr #SECTION_SHIFT
 247         movs    r0, r0, lsl #SECTION_SHIFT
 248         subne   r3, r0, r8
 249         addne   r3, r3, #PAGE_OFFSET
 250         addne   r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
 251         orrne   r6, r7, r0
 252         strne   r6, [r3]
 253
 254 #ifdef CONFIG_DEBUG_LL
 255 #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
 256         /*
 257          * Map in IO space for serial debugging.
 258          * This allows debug messages to be output
 259          * via a serial console before paging_init.
 260          */
 261         addruart r7, r3, r0
 262
 263         mov     r3, r3, lsr #SECTION_SHIFT
 264         mov     r3, r3, lsl #PMD_ORDER
 265
 266         add     r0, r4, r3
 267         mov     r3, r7, lsr #SECTION_SHIFT
 268         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 269         orr     r3, r7, r3, lsl #SECTION_SHIFT
 270 #ifdef CONFIG_ARM_LPAE
 271         mov     r7, #1 << (54 - 32)             @ XN
 272 #else
 273         orr     r3, r3, #PMD_SECT_XN
 274 #endif
 275         str     r3, [r0], #4
 276 #ifdef CONFIG_ARM_LPAE
 277         str     r7, [r0], #4
 278 #endif
 279
 280 #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
 281         /* we don't need any serial debugging mappings */
 282         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 283 #endif
 284
 285 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
 286         /*
 287          * If we're using the NetWinder or CATS, we also need to map
 288          * in the 16550-type serial port for the debug messages
 289          */
 290         add     r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
 291         orr     r3, r7, #0x7c000000
 292         str     r3, [r0]
 293 #endif
 294 #ifdef CONFIG_ARCH_RPC
 295         /*
 296          * Map in screen at 0x02000000 & SCREEN2_BASE
 297          * Similar reasons here - for debug.  This is
 298          * only for Acorn RiscPC architectures.
 299          */
 300         add     r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
 301         orr     r3, r7, #0x02000000
 302         str     r3, [r0]
 303         add     r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
 304         str     r3, [r0]
 305 #endif
 306 #endif
 307 #ifdef CONFIG_ARM_LPAE
 308         sub     r4, r4, #0x1000         @ point to the PGD table
 309 #endif
 310         mov     pc, lr
 311 ENDPROC(__create_page_tables)
 312         .ltorg
 313         .align
 314 __turn_mmu_on_loc:
 315         .long   .
 316         .long   __turn_mmu_on
 317         .long   __turn_mmu_on_end
 318
 319 #if defined(CONFIG_SMP)
 320         __CPUINIT
 321 ENTRY(secondary_startup)
 322         /*
 323          * Common entry point for secondary CPUs.
 324          *
 325          * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
 326          * the processor type - there is no need to check the machine type
 327          * as it has already been validated by the primary processor.
 328          */
 329         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
 330         mrc     p15, 0, r9, c0, c0              @ get processor id
 331         bl      __lookup_processor_type
 332         movs    r10, r5                         @ invalid processor?
 333         moveq   r0, #'p'                        @ yes, error 'p'
 334  THUMB( it      eq )            @ force fixup-able long branch encoding
 335         beq     __error_p
 336
 337         /*
 338          * Use the page tables supplied from  __cpu_up.
 339          */
 340         adr     r4, __secondary_data
 341         ldmia   r4, {r5, r7, r12}               @ address to jump to after
 342         sub     lr, r4, r5                      @ mmu has been enabled
 343         ldr     r4, [r7, lr]                    @ get secondary_data.pgdir
 344         add     r7, r7, #4
 345         ldr     r8, [r7, lr]                    @ get secondary_data.swapper_pg_dir
 346         adr     lr, BSYM(__enable_mmu)          @ return address
 347         mov     r13, r12                        @ __secondary_switched address
 348  ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
 349                                                   @ (return control reg)
 350  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 351  THUMB( mov     pc, r12                         )
 352 ENDPROC(secondary_startup)
 353
 354         /*
 355          * r6  = &secondary_data
 356          */
 357 ENTRY(__secondary_switched)
 358         ldr     sp, [r7, #4]                    @ get secondary_data.stack
 359         mov     fp, #0
 360         b       secondary_start_kernel
 361 ENDPROC(__secondary_switched)
 362
 363         .align
 364
 365         .type   __secondary_data, %object
 366 __secondary_data:
 367         .long   .
 368         .long   secondary_data
 369         .long   __secondary_switched
 370 #endif /* defined(CONFIG_SMP) */
 371
 372
 373
 374 /*
 375  * Setup common bits before finally enabling the MMU.  Essentially
 376  * this is just loading the page table pointer and domain access
 377  * registers.
 378  *
 379  *  r0  = cp#15 control register
 380  *  r1  = machine ID
 381  *  r2  = atags or dtb pointer
 382  *  r4  = page table pointer
 383  *  r9  = processor ID
 384  *  r13 = *virtual* address to jump to upon completion
 385  */
 386 __enable_mmu:
 387 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
 388         orr     r0, r0, #CR_A
 389 #else
 390         bic     r0, r0, #CR_A
 391 #endif
 392 #ifdef CONFIG_CPU_DCACHE_DISABLE
 393         bic     r0, r0, #CR_C
 394 #endif
 395 #ifdef CONFIG_CPU_BPREDICT_DISABLE
 396         bic     r0, r0, #CR_Z
 397 #endif
 398 #ifdef CONFIG_CPU_ICACHE_DISABLE
 399         bic     r0, r0, #CR_I
 400 #endif
 401 #ifdef CONFIG_ARM_LPAE
 402         mov     r5, #0
 403         mcrr    p15, 0, r4, r5, c2              @ load TTBR0
 404 #else
 405         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
 406                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
 407                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
 408                       domain_val(DOMAIN_IO, DOMAIN_CLIENT))
 409         mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
 410         mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
 411 #endif
 412         b       __turn_mmu_on
 413 ENDPROC(__enable_mmu)
 414
 415 /*
 416  * Enable the MMU.  This completely changes the structure of the visible
 417  * memory space.  You will not be able to trace execution through this.
 418  * If you have an enquiry about this, *please* check the linux-arm-kernel
 419  * mailing list archives BEFORE sending another post to the list.
 420  *
 421  *  r0  = cp#15 control register
 422  *  r1  = machine ID
 423  *  r2  = atags or dtb pointer
 424  *  r9  = processor ID
 425  *  r13 = *virtual* address to jump to upon completion
 426  *
 427  * other registers depend on the function called upon completion
 428  */
 429         .align  5
 430         .pushsection    .idmap.text, "ax"
 431 ENTRY(__turn_mmu_on)
 432         mov     r0, r0
 433         instr_sync
 434         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 435         mrc     p15, 0, r3, c0, c0, 0           @ read id reg
 436         instr_sync
 437         mov     r3, r3
 438         mov     r3, r13
 439         mov     pc, r3
 440 __turn_mmu_on_end:
 441 ENDPROC(__turn_mmu_on)
 442         .popsection
 443
 444
 445 #ifdef CONFIG_SMP_ON_UP
 446         __INIT
 447 __fixup_smp:
 448         and     r3, r9, #0x000f0000     @ architecture version
 449         teq     r3, #0x000f0000         @ CPU ID supported?
 450         bne     __fixup_smp_on_up       @ no, assume UP
 451
 452         bic     r3, r9, #0x00ff0000
 453         bic     r3, r3, #0x0000000f     @ mask 0xff00fff0
 454         mov     r4, #0x41000000
 455         orr     r4, r4, #0x0000b000
 456         orr     r4, r4, #0x00000020     @ val 0x4100b020
 457         teq     r3, r4                  @ ARM 11MPCore?
 458         moveq   pc, lr                  @ yes, assume SMP
 459
 460         mrc     p15, 0, r0, c0, c0, 5   @ read MPIDR
 461         and     r0, r0, #0xc0000000     @ multiprocessing extensions and
 462         teq     r0, #0x80000000         @ not part of a uniprocessor system?
 463         moveq   pc, lr                  @ yes, assume SMP
 464
 465 __fixup_smp_on_up:
 466         adr     r0, 1f
 467         ldmia   r0, {r3 - r5}
 468         sub     r3, r0, r3
 469         add     r4, r4, r3
 470         add     r5, r5, r3
 471         b       __do_fixup_smp_on_up
 472 ENDPROC(__fixup_smp)
 473
 474         .align
 475 1:      .word   .
 476         .word   __smpalt_begin
 477         .word   __smpalt_end
 478
 479         .pushsection .data
 480         .globl  smp_on_up
 481 smp_on_up:
 482         ALT_SMP(.long   1)
 483         ALT_UP(.long    0)
 484         .popsection
 485 #endif
 486
 487         .text
 488 __do_fixup_smp_on_up:
 489         cmp     r4, r5
 490         movhs   pc, lr
 491         ldmia   r4!, {r0, r6}
 492  ARM(   str     r6, [r0, r3]    )
 493  THUMB( add     r0, r0, r3      )
 494 #ifdef __ARMEB__
 495  THUMB( mov     r6, r6, ror #16 )       @ Convert word order for big-endian.
 496 #endif
 497  THUMB( strh    r6, [r0], #2    )       @ For Thumb-2, store as two halfwords
 498  THUMB( mov     r6, r6, lsr #16 )       @ to be robust against misaligned r3.
 499  THUMB( strh    r6, [r0]        )
 500         b       __do_fixup_smp_on_up
 501 ENDPROC(__do_fixup_smp_on_up)
 502
 503 ENTRY(fixup_smp)
 504         stmfd   sp!, {r4 - r6, lr}
 505         mov     r4, r0
 506         add     r5, r0, r1
 507         mov     r3, #0
 508         bl      __do_fixup_smp_on_up
 509         ldmfd   sp!, {r4 - r6, pc}
 510 ENDPROC(fixup_smp)
 511
 512 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 513
 514 /* __fixup_pv_table - patch the stub instructions with the delta between
 515  * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
 516  * can be expressed by an immediate shifter operand. The stub instruction
 517  * has a form of '(add|sub) rd, rn, #imm'.
 518  */
 519         __HEAD
 520 __fixup_pv_table:
 521         adr     r0, 1f
 522         ldmia   r0, {r3-r5, r7}
 523         sub     r3, r0, r3      @ PHYS_OFFSET - PAGE_OFFSET
 524         add     r4, r4, r3      @ adjust table start address
 525         add     r5, r5, r3      @ adjust table end address
 526         add     r7, r7, r3      @ adjust __pv_phys_offset address
 527         str     r8, [r7]        @ save computed PHYS_OFFSET to __pv_phys_offset
 528         mov     r6, r3, lsr #24 @ constant for add/sub instructions
 529         teq     r3, r6, lsl #24 @ must be 16MiB aligned
 530 THUMB(  it      ne              @ cross section branch )
 531         bne     __error
 532         str     r6, [r7, #4]    @ save to __pv_offset
 533         b       __fixup_a_pv_table
 534 ENDPROC(__fixup_pv_table)
 535
 536         .align
 537 1:      .long   .
 538         .long   __pv_table_begin
 539         .long   __pv_table_end
 540 2:      .long   __pv_phys_offset
 541
 542         .text
 543 __fixup_a_pv_table:
 544 #ifdef CONFIG_THUMB2_KERNEL
 545         lsls    r6, #24
 546         beq     2f
 547         clz     r7, r6
 548         lsr     r6, #24
 549         lsl     r6, r7
 550         bic     r6, #0x0080
 551         lsrs    r7, #1
 552         orrcs   r6, #0x0080
 553         orr     r6, r6, r7, lsl #12
 554         orr     r6, #0x4000
 555         b       2f
 556 1:      add     r7, r3
 557         ldrh    ip, [r7, #2]
 558         and     ip, 0x8f00
 559         orr     ip, r6  @ mask in offset bits 31-24
 560         strh    ip, [r7, #2]
 561 2:      cmp     r4, r5
 562         ldrcc   r7, [r4], #4    @ use branch for delay slot
 563         bcc     1b
 564         bx      lr
 565 #else
 566         b       2f
 567 1:      ldr     ip, [r7, r3]
 568         bic     ip, ip, #0x000000ff
 569         orr     ip, ip, r6      @ mask in offset bits 31-24
 570         str     ip, [r7, r3]
 571 2:      cmp     r4, r5
 572         ldrcc   r7, [r4], #4    @ use branch for delay slot
 573         bcc     1b
 574         mov     pc, lr
 575 #endif
 576 ENDPROC(__fixup_a_pv_table)
 577
 578 ENTRY(fixup_pv_table)
 579         stmfd   sp!, {r4 - r7, lr}
 580         ldr     r2, 2f                  @ get address of __pv_phys_offset
 581         mov     r3, #0                  @ no offset
 582         mov     r4, r0                  @ r0 = table start
 583         add     r5, r0, r1              @ r1 = table size
 584         ldr     r6, [r2, #4]            @ get __pv_offset
 585         bl      __fixup_a_pv_table
 586         ldmfd   sp!, {r4 - r7, pc}
 587 ENDPROC(fixup_pv_table)
 588
 589         .align
 590 2:      .long   __pv_phys_offset
 591
 592         .data
 593         .globl  __pv_phys_offset
 594         .type   __pv_phys_offset, %object
 595 __pv_phys_offset:
 596         .long   0
 597         .size   __pv_phys_offset, . - __pv_phys_offset
 598 __pv_offset:
 599         .long   0
 600 #endif
 601
 602 #include "head-common.S"