arch/arm/kernel/head.S

   1 /*
   2  *  linux/arch/arm/kernel/head.S
   3  *
   4  *  Copyright (C) 1994-2002 Russell King
   5  *  Copyright (c) 2003 ARM Limited
   6  *  All Rights Reserved
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  *  Kernel startup code for all 32-bit CPUs
  13  */
  14 #include <linux/linkage.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/assembler.h>
  18 #include <asm/cp15.h>
  19 #include <asm/domain.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/asm-offsets.h>
  22 #include <asm/memory.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/pgtable.h>
  25
  26 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
  27 #include CONFIG_DEBUG_LL_INCLUDE
  28 #endif
  29
  30 /*
  31  * swapper_pg_dir is the virtual address of the initial page table.
  32  * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
  33  * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
  34  * the least significant 16 bits to be 0x8000, but we could probably
  35  * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
  36  */
  37 #define KERNEL_RAM_VADDR        (PAGE_OFFSET + TEXT_OFFSET)
  38 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
  39 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
  40 #endif
  41
  42 #ifdef CONFIG_ARM_LPAE
  43         /* LPAE requires an additional page for the PGD */
  44 #define PG_DIR_SIZE     0x5000
  45 #define PMD_ORDER       3
  46 #else
  47 #define PG_DIR_SIZE     0x4000
  48 #define PMD_ORDER       2
  49 #endif
  50
  51         .globl  swapper_pg_dir
  52         .equ    swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
  53
  54         .macro  pgtbl, rd, phys
  55         add     \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
  56         .endm
  57
  58 /*
  59  * Kernel startup entry point.
  60  * ---------------------------
  61  *
  62  * This is normally called from the decompressor code.  The requirements
  63  * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
  64  * r1 = machine nr, r2 = atags or dtb pointer.
  65  *
  66  * This code is mostly position independent, so if you link the kernel at
  67  * 0xc0008000, you call this at __pa(0xc0008000).
  68  *
  69  * See linux/arch/arm/tools/mach-types for the complete list of machine
  70  * numbers for r1.
  71  *
  72  * We're trying to keep crap to a minimum; DO NOT add any machine specific
  73  * crap here - that's what the boot loader (or in extreme, well justified
  74  * circumstances, zImage) is for.
  75  */
  76         .arm
  77
  78         __HEAD
  79 ENTRY(stext)
  80
  81  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
  82  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
  83  THUMB( .thumb                  )       @ switch to Thumb now.
  84  THUMB(1:                       )
  85
  86 #ifdef CONFIG_ARM_VIRT_EXT
  87         bl      __hyp_stub_install
  88 #endif
  89         @ ensure svc mode and all interrupts masked
  90         safe_svcmode_maskall r9
  91
  92         mrc     p15, 0, r9, c0, c0              @ get processor id
  93         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
  94         movs    r10, r5                         @ invalid processor (r5=0)?
  95  THUMB( it      eq )            @ force fixup-able long branch encoding
  96         beq     __error_p                       @ yes, error 'p'
  97
  98 #ifdef CONFIG_ARM_LPAE
  99         mrc     p15, 0, r3, c0, c1, 4           @ read ID_MMFR0
 100         and     r3, r3, #0xf                    @ extract VMSA support
 101         cmp     r3, #5                          @ long-descriptor translation table format?
 102  THUMB( it      lo )                            @ force fixup-able long branch encoding
 103         blo     __error_p                       @ only classic page table format
 104 #endif
 105
 106 #ifndef CONFIG_XIP_KERNEL
 107         adr     r3, 2f
 108         ldmia   r3, {r4, r8}
 109         sub     r4, r3, r4                      @ (PHYS_OFFSET - PAGE_OFFSET)
 110         add     r8, r8, r4                      @ PHYS_OFFSET
 111 #else
 112         ldr     r8, =PHYS_OFFSET                @ always constant in this case
 113 #endif
 114
 115         /*
 116          * r1 = machine no, r2 = atags or dtb,
 117          * r8 = phys_offset, r9 = cpuid, r10 = procinfo
 118          */
 119         bl      __vet_atags
 120 #ifdef CONFIG_SMP_ON_UP
 121         bl      __fixup_smp
 122 #endif
 123 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 124         bl      __fixup_pv_table
 125 #endif
 126         bl      __create_page_tables
 127
 128         /*
 129          * The following calls CPU specific code in a position independent
 130          * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
 131          * xxx_proc_info structure selected by __lookup_processor_type
 132          * above.  On return, the CPU will be ready for the MMU to be
 133          * turned on, and r0 will hold the CPU control register value.
 134          */
 135         ldr     r13, =__mmap_switched           @ address to jump to after
 136                                                 @ mmu has been enabled
 137         adr     lr, BSYM(1f)                    @ return (PIC) address
 138         mov     r8, r4                          @ set TTBR1 to swapper_pg_dir
 139  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
 140  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 141  THUMB( mov     pc, r12                         )
 142 1:      b       __enable_mmu
 143 ENDPROC(stext)
 144         .ltorg
 145 #ifndef CONFIG_XIP_KERNEL
 146 2:      .long   .
 147         .long   PAGE_OFFSET
 148 #endif
 149
 150 /*
 151  * Setup the initial page tables.  We only setup the barest
 152  * amount which are required to get the kernel running, which
 153  * generally means mapping in the kernel code.
 154  *
 155  * r8 = phys_offset, r9 = cpuid, r10 = procinfo
 156  *
 157  * Returns:
 158  *  r0, r3, r5-r7 corrupted
 159  *  r4 = physical page table address
 160  */
 161 __create_page_tables:
 162         pgtbl   r4, r8                          @ page table address
 163
 164         /*
 165          * Clear the swapper page table
 166          */
 167         mov     r0, r4
 168         mov     r3, #0
 169         add     r6, r0, #PG_DIR_SIZE
 170 1:      str     r3, [r0], #4
 171         str     r3, [r0], #4
 172         str     r3, [r0], #4
 173         str     r3, [r0], #4
 174         teq     r0, r6
 175         bne     1b
 176
 177 #ifdef CONFIG_ARM_LPAE
 178         /*
 179          * Build the PGD table (first level) to point to the PMD table. A PGD
 180          * entry is 64-bit wide.
 181          */
 182         mov     r0, r4
 183         add     r3, r4, #0x1000                 @ first PMD table address
 184         orr     r3, r3, #3                      @ PGD block type
 185         mov     r6, #4                          @ PTRS_PER_PGD
 186         mov     r7, #1 << (55 - 32)             @ L_PGD_SWAPPER
 187 1:
 188 #ifdef CONFIG_CPU_ENDIAN_BE8
 189         str     r7, [r0], #4                    @ set top PGD entry bits
 190         str     r3, [r0], #4                    @ set bottom PGD entry bits
 191 #else
 192         str     r3, [r0], #4                    @ set bottom PGD entry bits
 193         str     r7, [r0], #4                    @ set top PGD entry bits
 194 #endif
 195         add     r3, r3, #0x1000                 @ next PMD table
 196         subs    r6, r6, #1
 197         bne     1b
 198
 199         add     r4, r4, #0x1000                 @ point to the PMD tables
 200 #ifdef CONFIG_CPU_ENDIAN_BE8
 201         add     r4, r4, #4                      @ we only write the bottom word
 202 #endif
 203 #endif
 204
 205         ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 206
 207         /*
 208          * Create identity mapping to cater for __enable_mmu.
 209          * This identity mapping will be removed by paging_init().
 210          */
 211         adr     r0, __turn_mmu_on_loc
 212         ldmia   r0, {r3, r5, r6}
 213         sub     r0, r0, r3                      @ virt->phys offset
 214         add     r5, r5, r0                      @ phys __turn_mmu_on
 215         add     r6, r6, r0                      @ phys __turn_mmu_on_end
 216         mov     r5, r5, lsr #SECTION_SHIFT
 217         mov     r6, r6, lsr #SECTION_SHIFT
 218
 219 1:      orr     r3, r7, r5, lsl #SECTION_SHIFT  @ flags + kernel base
 220         str     r3, [r4, r5, lsl #PMD_ORDER]    @ identity mapping
 221         cmp     r5, r6
 222         addlo   r5, r5, #1                      @ next section
 223         blo     1b
 224
 225         /*
 226          * Map our RAM from the start to the end of the kernel .bss section.
 227          */
 228         add     r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
 229         ldr     r6, =(_end - 1)
 230         orr     r3, r8, r7
 231         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 232 1:      str     r3, [r0], #1 << PMD_ORDER
 233         add     r3, r3, #1 << SECTION_SHIFT
 234         cmp     r0, r6
 235         bls     1b
 236
 237 #ifdef CONFIG_XIP_KERNEL
 238         /*
 239          * Map the kernel image separately as it is not located in RAM.
 240          */
 241 #define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
 242         mov     r3, pc
 243         mov     r3, r3, lsr #SECTION_SHIFT
 244         orr     r3, r7, r3, lsl #SECTION_SHIFT
 245         add     r0, r4,  #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
 246         str     r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
 247         ldr     r6, =(_edata_loc - 1)
 248         add     r0, r0, #1 << PMD_ORDER
 249         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 250 1:      cmp     r0, r6
 251         add     r3, r3, #1 << SECTION_SHIFT
 252         strls   r3, [r0], #1 << PMD_ORDER
 253         bls     1b
 254 #endif
 255
 256         /*
 257          * Then map boot params address in r2 if specified.
 258          * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
 259          */
 260         mov     r0, r2, lsr #SECTION_SHIFT
 261         movs    r0, r0, lsl #SECTION_SHIFT
 262         subne   r3, r0, r8
 263         addne   r3, r3, #PAGE_OFFSET
 264         addne   r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
 265         orrne   r6, r7, r0
 266         strne   r6, [r3], #1 << PMD_ORDER
 267         addne   r6, r6, #1 << SECTION_SHIFT
 268         strne   r6, [r3]
 269
 270 #if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
 271         sub     r4, r4, #4                      @ Fixup page table pointer
 272                                                 @ for 64-bit descriptors
 273 #endif
 274
 275 #ifdef CONFIG_DEBUG_LL
 276 #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
 277         /*
 278          * Map in IO space for serial debugging.
 279          * This allows debug messages to be output
 280          * via a serial console before paging_init.
 281          */
 282         addruart r7, r3, r0
 283
 284         mov     r3, r3, lsr #SECTION_SHIFT
 285         mov     r3, r3, lsl #PMD_ORDER
 286
 287         add     r0, r4, r3
 288         mov     r3, r7, lsr #SECTION_SHIFT
 289         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 290         orr     r3, r7, r3, lsl #SECTION_SHIFT
 291 #ifdef CONFIG_ARM_LPAE
 292         mov     r7, #1 << (54 - 32)             @ XN
 293 #ifdef CONFIG_CPU_ENDIAN_BE8
 294         str     r7, [r0], #4
 295         str     r3, [r0], #4
 296 #else
 297         str     r3, [r0], #4
 298         str     r7, [r0], #4
 299 #endif
 300 #else
 301         orr     r3, r3, #PMD_SECT_XN
 302         str     r3, [r0], #4
 303 #endif
 304
 305 #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
 306         /* we don't need any serial debugging mappings */
 307         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 308 #endif
 309
 310 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
 311         /*
 312          * If we're using the NetWinder or CATS, we also need to map
 313          * in the 16550-type serial port for the debug messages
 314          */
 315         add     r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
 316         orr     r3, r7, #0x7c000000
 317         str     r3, [r0]
 318 #endif
 319 #ifdef CONFIG_ARCH_RPC
 320         /*
 321          * Map in screen at 0x02000000 & SCREEN2_BASE
 322          * Similar reasons here - for debug.  This is
 323          * only for Acorn RiscPC architectures.
 324          */
 325         add     r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
 326         orr     r3, r7, #0x02000000
 327         str     r3, [r0]
 328         add     r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
 329         str     r3, [r0]
 330 #endif
 331 #endif
 332 #ifdef CONFIG_ARM_LPAE
 333         sub     r4, r4, #0x1000         @ point to the PGD table
 334 #endif
 335         mov     pc, lr
 336 ENDPROC(__create_page_tables)
 337         .ltorg
 338         .align
 339 __turn_mmu_on_loc:
 340         .long   .
 341         .long   __turn_mmu_on
 342         .long   __turn_mmu_on_end
 343
 344 #if defined(CONFIG_SMP)
 345         __CPUINIT
 346 ENTRY(secondary_startup)
 347         /*
 348          * Common entry point for secondary CPUs.
 349          *
 350          * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
 351          * the processor type - there is no need to check the machine type
 352          * as it has already been validated by the primary processor.
 353          */
 354 #ifdef CONFIG_ARM_VIRT_EXT
 355         bl      __hyp_stub_install_secondary
 356 #endif
 357         safe_svcmode_maskall r9
 358
 359         mrc     p15, 0, r9, c0, c0              @ get processor id
 360         bl      __lookup_processor_type
 361         movs    r10, r5                         @ invalid processor?
 362         moveq   r0, #'p'                        @ yes, error 'p'
 363  THUMB( it      eq )            @ force fixup-able long branch encoding
 364         beq     __error_p
 365
 366         /*
 367          * Use the page tables supplied from  __cpu_up.
 368          */
 369         adr     r4, __secondary_data
 370         ldmia   r4, {r5, r7, r12}               @ address to jump to after
 371         sub     lr, r4, r5                      @ mmu has been enabled
 372         ldr     r4, [r7, lr]                    @ get secondary_data.pgdir
 373         add     r7, r7, #4
 374         ldr     r8, [r7, lr]                    @ get secondary_data.swapper_pg_dir
 375         adr     lr, BSYM(__enable_mmu)          @ return address
 376         mov     r13, r12                        @ __secondary_switched address
 377  ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
 378                                                   @ (return control reg)
 379  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 380  THUMB( mov     pc, r12                         )
 381 ENDPROC(secondary_startup)
 382
 383         /*
 384          * r6  = &secondary_data
 385          */
 386 ENTRY(__secondary_switched)
 387         ldr     sp, [r7, #4]                    @ get secondary_data.stack
 388         mov     fp, #0
 389         b       secondary_start_kernel
 390 ENDPROC(__secondary_switched)
 391
 392         .align
 393
 394         .type   __secondary_data, %object
 395 __secondary_data:
 396         .long   .
 397         .long   secondary_data
 398         .long   __secondary_switched
 399 #endif /* defined(CONFIG_SMP) */
 400
 401
 402
 403 /*
 404  * Setup common bits before finally enabling the MMU.  Essentially
 405  * this is just loading the page table pointer and domain access
 406  * registers.
 407  *
 408  *  r0  = cp#15 control register
 409  *  r1  = machine ID
 410  *  r2  = atags or dtb pointer
 411  *  r4  = page table pointer
 412  *  r9  = processor ID
 413  *  r13 = *virtual* address to jump to upon completion
 414  */
 415 __enable_mmu:
 416 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
 417         orr     r0, r0, #CR_A
 418 #else
 419         bic     r0, r0, #CR_A
 420 #endif
 421 #ifdef CONFIG_CPU_DCACHE_DISABLE
 422         bic     r0, r0, #CR_C
 423 #endif
 424 #ifdef CONFIG_CPU_BPREDICT_DISABLE
 425         bic     r0, r0, #CR_Z
 426 #endif
 427 #ifdef CONFIG_CPU_ICACHE_DISABLE
 428         bic     r0, r0, #CR_I
 429 #endif
 430 #ifdef CONFIG_ARM_LPAE
 431         mov     r5, #0
 432         mcrr    p15, 0, r4, r5, c2              @ load TTBR0
 433 #else
 434         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
 435                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
 436                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
 437                       domain_val(DOMAIN_IO, DOMAIN_CLIENT))
 438         mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
 439         mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
 440 #endif
 441         b       __turn_mmu_on
 442 ENDPROC(__enable_mmu)
 443
 444 /*
 445  * Enable the MMU.  This completely changes the structure of the visible
 446  * memory space.  You will not be able to trace execution through this.
 447  * If you have an enquiry about this, *please* check the linux-arm-kernel
 448  * mailing list archives BEFORE sending another post to the list.
 449  *
 450  *  r0  = cp#15 control register
 451  *  r1  = machine ID
 452  *  r2  = atags or dtb pointer
 453  *  r9  = processor ID
 454  *  r13 = *virtual* address to jump to upon completion
 455  *
 456  * other registers depend on the function called upon completion
 457  */
 458         .align  5
 459         .pushsection    .idmap.text, "ax"
 460 ENTRY(__turn_mmu_on)
 461         mov     r0, r0
 462         instr_sync
 463         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 464         mrc     p15, 0, r3, c0, c0, 0           @ read id reg
 465         instr_sync
 466         mov     r3, r3
 467         mov     r3, r13
 468         mov     pc, r3
 469 __turn_mmu_on_end:
 470 ENDPROC(__turn_mmu_on)
 471         .popsection
 472
 473
 474 #ifdef CONFIG_SMP_ON_UP
 475         __INIT
 476 __fixup_smp:
 477         and     r3, r9, #0x000f0000     @ architecture version
 478         teq     r3, #0x000f0000         @ CPU ID supported?
 479         bne     __fixup_smp_on_up       @ no, assume UP
 480
 481         bic     r3, r9, #0x00ff0000
 482         bic     r3, r3, #0x0000000f     @ mask 0xff00fff0
 483         mov     r4, #0x41000000
 484         orr     r4, r4, #0x0000b000
 485         orr     r4, r4, #0x00000020     @ val 0x4100b020
 486         teq     r3, r4                  @ ARM 11MPCore?
 487         moveq   pc, lr                  @ yes, assume SMP
 488
 489         mrc     p15, 0, r0, c0, c0, 5   @ read MPIDR
 490         and     r0, r0, #0xc0000000     @ multiprocessing extensions and
 491         teq     r0, #0x80000000         @ not part of a uniprocessor system?
 492         moveq   pc, lr                  @ yes, assume SMP
 493
 494 __fixup_smp_on_up:
 495         adr     r0, 1f
 496         ldmia   r0, {r3 - r5}
 497         sub     r3, r0, r3
 498         add     r4, r4, r3
 499         add     r5, r5, r3
 500         b       __do_fixup_smp_on_up
 501 ENDPROC(__fixup_smp)
 502
 503         .align
 504 1:      .word   .
 505         .word   __smpalt_begin
 506         .word   __smpalt_end
 507
 508         .pushsection .data
 509         .globl  smp_on_up
 510 smp_on_up:
 511         ALT_SMP(.long   1)
 512         ALT_UP(.long    0)
 513         .popsection
 514 #endif
 515
 516         .text
 517 __do_fixup_smp_on_up:
 518         cmp     r4, r5
 519         movhs   pc, lr
 520         ldmia   r4!, {r0, r6}
 521  ARM(   str     r6, [r0, r3]    )
 522  THUMB( add     r0, r0, r3      )
 523 #ifdef __ARMEB__
 524  THUMB( mov     r6, r6, ror #16 )       @ Convert word order for big-endian.
 525 #endif
 526  THUMB( strh    r6, [r0], #2    )       @ For Thumb-2, store as two halfwords
 527  THUMB( mov     r6, r6, lsr #16 )       @ to be robust against misaligned r3.
 528  THUMB( strh    r6, [r0]        )
 529         b       __do_fixup_smp_on_up
 530 ENDPROC(__do_fixup_smp_on_up)
 531
 532 ENTRY(fixup_smp)
 533         stmfd   sp!, {r4 - r6, lr}
 534         mov     r4, r0
 535         add     r5, r0, r1
 536         mov     r3, #0
 537         bl      __do_fixup_smp_on_up
 538         ldmfd   sp!, {r4 - r6, pc}
 539 ENDPROC(fixup_smp)
 540
 541 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 542
 543 /* __fixup_pv_table - patch the stub instructions with the delta between
 544  * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
 545  * can be expressed by an immediate shifter operand. The stub instruction
 546  * has a form of '(add|sub) rd, rn, #imm'.
 547  */
 548         __HEAD
 549 __fixup_pv_table:
 550         adr     r0, 1f
 551         ldmia   r0, {r3-r5, r7}
 552         sub     r3, r0, r3      @ PHYS_OFFSET - PAGE_OFFSET
 553         add     r4, r4, r3      @ adjust table start address
 554         add     r5, r5, r3      @ adjust table end address
 555         add     r7, r7, r3      @ adjust __pv_phys_offset address
 556         str     r8, [r7]        @ save computed PHYS_OFFSET to __pv_phys_offset
 557         mov     r6, r3, lsr #24 @ constant for add/sub instructions
 558         teq     r3, r6, lsl #24 @ must be 16MiB aligned
 559 THUMB(  it      ne              @ cross section branch )
 560         bne     __error
 561         str     r6, [r7, #4]    @ save to __pv_offset
 562         b       __fixup_a_pv_table
 563 ENDPROC(__fixup_pv_table)
 564
 565         .align
 566 1:      .long   .
 567         .long   __pv_table_begin
 568         .long   __pv_table_end
 569 2:      .long   __pv_phys_offset
 570
 571         .text
 572 __fixup_a_pv_table:
 573 #ifdef CONFIG_THUMB2_KERNEL
 574         lsls    r6, #24
 575         beq     2f
 576         clz     r7, r6
 577         lsr     r6, #24
 578         lsl     r6, r7
 579         bic     r6, #0x0080
 580         lsrs    r7, #1
 581         orrcs   r6, #0x0080
 582         orr     r6, r6, r7, lsl #12
 583         orr     r6, #0x4000
 584         b       2f
 585 1:      add     r7, r3
 586         ldrh    ip, [r7, #2]
 587         and     ip, 0x8f00
 588         orr     ip, r6  @ mask in offset bits 31-24
 589         strh    ip, [r7, #2]
 590 2:      cmp     r4, r5
 591         ldrcc   r7, [r4], #4    @ use branch for delay slot
 592         bcc     1b
 593         bx      lr
 594 #else
 595         b       2f
 596 1:      ldr     ip, [r7, r3]
 597         bic     ip, ip, #0x000000ff
 598         orr     ip, ip, r6      @ mask in offset bits 31-24
 599         str     ip, [r7, r3]
 600 2:      cmp     r4, r5
 601         ldrcc   r7, [r4], #4    @ use branch for delay slot
 602         bcc     1b
 603         mov     pc, lr
 604 #endif
 605 ENDPROC(__fixup_a_pv_table)
 606
 607 ENTRY(fixup_pv_table)
 608         stmfd   sp!, {r4 - r7, lr}
 609         ldr     r2, 2f                  @ get address of __pv_phys_offset
 610         mov     r3, #0                  @ no offset
 611         mov     r4, r0                  @ r0 = table start
 612         add     r5, r0, r1              @ r1 = table size
 613         ldr     r6, [r2, #4]            @ get __pv_offset
 614         bl      __fixup_a_pv_table
 615         ldmfd   sp!, {r4 - r7, pc}
 616 ENDPROC(fixup_pv_table)
 617
 618         .align
 619 2:      .long   __pv_phys_offset
 620
 621         .data
 622         .globl  __pv_phys_offset
 623         .type   __pv_phys_offset, %object
 624 __pv_phys_offset:
 625         .long   0
 626         .size   __pv_phys_offset, . - __pv_phys_offset
 627 __pv_offset:
 628         .long   0
 629 #endif
 630
 631 #include "head-common.S"