2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Low-level vector interface routines
13 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
14 * it to save wrong values... Be aware!
16 #include <linux/config.h>
19 #include <asm/vfpmacros.h>
20 #include <asm/hardware.h> /* should be moved into entry-macro.S */
21 #include <asm/arch/irqs.h> /* should be moved into entry-macro.S */
22 #include <asm/arch/entry-macro.S>
24 #include "entry-header.S"
27 * Interrupt handling. Preserves r7, r8, r9
30 1: get_irqnr_and_base r0, r6, r5, lr
33 @ routine called with r0 = irq number, r1 = struct pt_regs *
42 * this macro assumes that irqstat (r6) and base (r5) are
43 * preserved from get_irqnr_and_base above
45 test_for_ipi r0, r6, r5, lr
54 * Invalid mode handlers
56 .macro inv_entry, sym, reason
57 sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
58 stmia sp, {r0 - lr} @ Save XXX r0 - lr
64 inv_entry abt, BAD_PREFETCH
68 inv_entry abt, BAD_DATA
72 inv_entry irq, BAD_IRQ
76 inv_entry und, BAD_UNDEFINSTR
79 ldmia r4, {r5 - r7} @ Get XXX pc, cpsr, old_r0
81 stmia r4, {r5 - r7} @ Save XXX pc, cpsr, old_r0
83 and r2, r6, #31 @ int mode
90 sub sp, sp, #S_FRAME_SIZE
91 stmia sp, {r0 - r12} @ save r0 - r12
93 add r0, sp, #S_FRAME_SIZE
94 ldmia r2, {r2 - r4} @ get pc, cpsr
99 @ We are now ready to fill in the remaining blanks on the stack:
103 @ r2 - lr_<exception>, already fixed up for correct return/restart
104 @ r3 - spsr_<exception>
105 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
115 @ get ready to re-enable interrupts if appropriate
119 biceq r9, r9, #PSR_I_BIT
122 @ Call the processor-specific abort handler:
124 @ r2 - aborted context pc
125 @ r3 - aborted context cpsr
127 @ The abort handler must return the aborted address in r0, and
128 @ the fault status register in r1. r9 must be preserved.
139 @ set desired IRQ state, then call main handler
146 @ IRQs off again before pulling preserved data off the stack
151 @ restore SPSR and restart the instruction
155 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
160 #ifdef CONFIG_PREEMPT
162 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
163 add r7, r8, #1 @ increment it
164 str r7, [tsk, #TI_PREEMPT]
167 #ifdef CONFIG_PREEMPT
168 ldr r0, [tsk, #TI_FLAGS] @ get flags
169 tst r0, #_TIF_NEED_RESCHED
172 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
173 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
175 strne r0, [r0, -r0] @ bug()
177 ldr r0, [sp, #S_PSR] @ irqs are already disabled
179 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
183 #ifdef CONFIG_PREEMPT
185 teq r8, #0 @ was preempt count = 0
186 ldreq r6, .LCirq_stat
188 ldr r0, [r6, #4] @ local_irq_count
189 ldr r1, [r6, #8] @ local_bh_count
192 mov r7, #0 @ preempt_schedule_irq
193 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
194 1: bl preempt_schedule_irq @ irq en/disable is done inside
195 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
196 tst r0, #_TIF_NEED_RESCHED
197 beq preempt_return @ go again
206 @ call emulation code, which returns using r9 if it has emulated
207 @ the instruction, or the more conventional lr if we are to treat
208 @ this as a real undefined instruction
216 mov r0, sp @ struct pt_regs *regs
220 @ IRQs off again before pulling preserved data off the stack
225 @ restore SPSR and restart the instruction
227 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
229 ldmia sp, {r0 - pc}^ @ Restore SVC registers
236 @ re-enable interrupts if appropriate
240 biceq r9, r9, #PSR_I_BIT
244 @ set args, then call main handler
246 @ r0 - address of faulting instruction
247 @ r1 - pointer to registers on stack
249 mov r0, r2 @ address (pc)
251 bl do_PrefetchAbort @ call abort handler
254 @ IRQs off again before pulling preserved data off the stack
259 @ restore SPSR and restart the instruction
263 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
280 #ifdef CONFIG_PREEMPT
288 .macro usr_entry, sym
289 sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
290 stmia sp, {r0 - r12} @ save r0 - r12
293 ldmia r7, {r2 - r4} @ Get USR pc, cpsr
295 #if __LINUX_ARM_ARCH__ < 6
296 @ make sure our user space atomic helper is aborted
298 bichs r3, r3, #PSR_Z_BIT
302 @ We are now ready to fill in the remaining blanks on the stack:
304 @ r2 - lr_<exception>, already fixed up for correct return/restart
305 @ r3 - spsr_<exception>
306 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
308 @ Also, separately save sp_usr and lr_usr
314 @ Enable the alignment trap while in kernel mode
319 @ Clear FP to mark the first stack frame
329 @ Call the processor-specific abort handler:
331 @ r2 - aborted context pc
332 @ r3 - aborted context cpsr
334 @ The abort handler must return the aborted address in r0, and
335 @ the fault status register in r1.
346 @ IRQs on, then call the main handler
350 adr lr, ret_from_exception
358 #ifdef CONFIG_PREEMPT
359 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
360 add r7, r8, #1 @ increment it
361 str r7, [tsk, #TI_PREEMPT]
364 #ifdef CONFIG_PREEMPT
365 ldr r0, [tsk, #TI_PREEMPT]
366 str r8, [tsk, #TI_PREEMPT]
379 tst r3, #PSR_T_BIT @ Thumb mode?
380 bne fpundefinstr @ ignore FP
384 @ fall through to the emulation code, which returns using r9 if
385 @ it has emulated the instruction, or the more conventional lr
386 @ if we are to treat this as a real undefined instruction
391 adr r9, ret_from_exception
394 @ fallthrough to call_fpe
398 * The out of line fixup for the ldrt above.
400 .section .fixup, "ax"
403 .section __ex_table,"a"
408 * Check whether the instruction is a co-processor instruction.
409 * If yes, we need to call the relevant co-processor handler.
411 * Note that we don't do a full check here for the co-processor
412 * instructions; all instructions with bit 27 set are well
413 * defined. The only instructions that should fault are the
414 * co-processor instructions. However, we have to watch out
415 * for the ARM6/ARM7 SWI bug.
417 * Emulators may wish to make use of the following registers:
418 * r0 = instruction opcode.
420 * r10 = this threads thread_info structure.
423 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
424 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
425 and r8, r0, #0x0f000000 @ mask out op-code bits
426 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
429 get_thread_info r10 @ get current thread
430 and r8, r0, #0x00000f00 @ mask out CP number
432 add r6, r10, #TI_USED_CP
433 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
435 @ Test if we need to give access to iWMMXt coprocessors
436 ldr r5, [r10, #TI_FLAGS]
437 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
438 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
439 bcs iwmmxt_task_enable
442 add pc, pc, r8, lsr #6
446 b do_fpe @ CP#1 (FPE)
447 b do_fpe @ CP#2 (FPE)
456 b do_vfp @ CP#10 (VFP)
457 b do_vfp @ CP#11 (VFP)
459 mov pc, lr @ CP#10 (VFP)
460 mov pc, lr @ CP#11 (VFP)
464 mov pc, lr @ CP#14 (Debug)
465 mov pc, lr @ CP#15 (Control)
469 add r10, r10, #TI_FPSTATE @ r10 = workspace
470 ldr pc, [r4] @ Call FP module USR entry point
473 * The FP module is called with these registers set:
476 * r9 = normal "successful" return address
478 * lr = unrecognised FP instruction return address
488 adr lr, ret_from_exception
495 enable_irq @ Enable interrupts
496 mov r0, r2 @ address (pc)
498 bl do_PrefetchAbort @ call abort handler
501 * This is the return code to user mode for abort handlers
503 ENTRY(ret_from_exception)
509 * Register switch for ARMv3 and ARMv4 processors
510 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
511 * previous and next are guaranteed not to be the same.
514 add ip, r1, #TI_CPU_SAVE
515 ldr r3, [r2, #TI_TP_VALUE]
516 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
517 ldr r6, [r2, #TI_CPU_DOMAIN]!
518 #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
522 #if defined(CONFIG_HAS_TLS_REG)
523 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
524 #elif !defined(CONFIG_TLS_REG_EMUL)
526 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
528 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
530 @ Always disable VFP so we can lazily save/restore the old
531 @ state. This occurs in the context of the previous thread.
533 bic r4, r4, #FPEXC_ENABLE
536 #if defined(CONFIG_IWMMXT)
537 bl iwmmxt_task_switch
538 #elif defined(CONFIG_CPU_XSCALE)
539 add r4, r2, #40 @ cpu_context_save->extra
543 ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
550 * These are segment of kernel provided user code reachable from user space
551 * at a fixed address in kernel memory. This is used to provide user space
552 * with some operations which require kernel help because of unimplemented
553 * native feature and/or instructions in many ARM CPUs. The idea is for
554 * this code to be executed directly in user mode for best efficiency but
555 * which is too intimate with the kernel counter part to be left to user
556 * libraries. In fact this code might even differ from one CPU to another
557 * depending on the available instruction set and restrictions like on
558 * SMP systems. In other words, the kernel reserves the right to change
559 * this code as needed without warning. Only the entry points and their
560 * results are guaranteed to be stable.
562 * Each segment is 32-byte aligned and will be moved to the top of the high
563 * vector page. New segments (if ever needed) must be added in front of
564 * existing ones. This mechanism should be used only for things that are
565 * really small and justified, and not be abused freely.
567 * User space is expected to implement those things inline when optimizing
568 * for a processor that has the necessary native support, but only if such
569 * resulting binaries are already to be incompatible with earlier ARM
570 * processors due to the use of unsupported instructions other than what
571 * is provided here. In other words don't make binaries unable to run on
572 * earlier processors just for the sake of not using these kernel helpers
573 * if your compiled code is not going to use the new instructions for other
578 .globl __kuser_helper_start
579 __kuser_helper_start:
582 * Reference prototype:
584 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
591 * lr = return address
595 * r0 = returned value (zero or non-zero)
596 * C flag = set if r0 == 0, clear if r0 != 0
602 * Definition and user space usage example:
604 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
605 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
607 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
608 * Return zero if *ptr was changed or non-zero if no exchange happened.
609 * The C flag is also set if *ptr was changed to allow for assembly
610 * optimization in the calling code.
612 * For example, a user space atomic_add implementation could look like this:
614 * #define atomic_add(ptr, val) \
615 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
616 * register unsigned int __result asm("r1"); \
618 * "1: @ atomic_add\n\t" \
619 * "ldr r0, [r2]\n\t" \
620 * "mov r3, #0xffff0fff\n\t" \
621 * "add lr, pc, #4\n\t" \
622 * "add r1, r0, %2\n\t" \
623 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
625 * : "=&r" (__result) \
626 * : "r" (__ptr), "rIL" (val) \
627 * : "r0","r3","ip","lr","cc","memory" ); \
631 __kuser_cmpxchg: @ 0xffff0fc0
633 #if __LINUX_ARM_ARCH__ < 6
635 #ifdef CONFIG_SMP /* sanity check */
636 #error "CONFIG_SMP on a machine supporting pre-ARMv6 processors?"
640 * Theory of operation:
642 * We set the Z flag before loading oldval. If ever an exception
643 * occurs we can not be sure the loaded value will still be the same
644 * when the exception returns, therefore the user exception handler
645 * will clear the Z flag whenever the interrupted user code was
646 * actually from the kernel address space (see the usr_entry macro).
648 * The post-increment on the str is used to prevent a race with an
649 * exception happening just after the str instruction which would
650 * clear the Z flag although the exchange was done.
652 teq ip, ip @ set Z flag
653 ldr ip, [r2] @ load current val
654 add r3, r2, #1 @ prepare store ptr
655 teqeq ip, r0 @ compare with oldval if still allowed
656 streq r1, [r3, #-1]! @ store newval if still allowed
657 subs r0, r2, r3 @ if r2 == r3 the str occured
673 * Reference prototype:
675 * int __kernel_get_tls(void)
679 * lr = return address
687 * the Z flag might be lost
689 * Definition and user space usage example:
691 * typedef int (__kernel_get_tls_t)(void);
692 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
694 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
696 * This could be used as follows:
698 * #define __kernel_get_tls() \
699 * ({ register unsigned int __val asm("r0"); \
700 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
701 * : "=r" (__val) : : "lr","cc" ); \
705 __kuser_get_tls: @ 0xffff0fe0
707 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
709 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
714 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
720 .word 0 @ pad up to __kuser_helper_version
724 * Reference declaration:
726 * extern unsigned int __kernel_helper_version;
728 * Definition and user space usage example:
730 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
732 * User space may read this to determine the curent number of helpers
736 __kuser_helper_version: @ 0xffff0ffc
737 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
739 .globl __kuser_helper_end
746 * This code is copied to 0xffff0200 so we can use branches in the
747 * vectors, rather than ldr's. Note that this code must not
748 * exceed 0x300 bytes.
750 * Common stub entry macro:
751 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
753 .macro vector_stub, name, sym, correction=0
759 sub lr, lr, #\correction
761 str lr, [r13] @ save lr_IRQ
763 str lr, [r13, #4] @ save spsr_IRQ
765 @ now branch to the relevant MODE handling routine
768 bic r13, r13, #MODE_MASK
769 orr r13, r13, #SVC_MODE
770 msr spsr_cxsf, r13 @ switch to SVC_32 mode
773 ldr lr, [pc, lr, lsl #2]
774 movs pc, lr @ Changes mode and branches
780 * Interrupt dispatcher
782 vector_stub irq, irq, 4
784 .long __irq_usr @ 0 (USR_26 / USR_32)
785 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
786 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
787 .long __irq_svc @ 3 (SVC_26 / SVC_32)
788 .long __irq_invalid @ 4
789 .long __irq_invalid @ 5
790 .long __irq_invalid @ 6
791 .long __irq_invalid @ 7
792 .long __irq_invalid @ 8
793 .long __irq_invalid @ 9
794 .long __irq_invalid @ a
795 .long __irq_invalid @ b
796 .long __irq_invalid @ c
797 .long __irq_invalid @ d
798 .long __irq_invalid @ e
799 .long __irq_invalid @ f
802 * Data abort dispatcher
803 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
805 vector_stub dabt, abt, 8
807 .long __dabt_usr @ 0 (USR_26 / USR_32)
808 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
809 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
810 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
811 .long __dabt_invalid @ 4
812 .long __dabt_invalid @ 5
813 .long __dabt_invalid @ 6
814 .long __dabt_invalid @ 7
815 .long __dabt_invalid @ 8
816 .long __dabt_invalid @ 9
817 .long __dabt_invalid @ a
818 .long __dabt_invalid @ b
819 .long __dabt_invalid @ c
820 .long __dabt_invalid @ d
821 .long __dabt_invalid @ e
822 .long __dabt_invalid @ f
825 * Prefetch abort dispatcher
826 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
828 vector_stub pabt, abt, 4
830 .long __pabt_usr @ 0 (USR_26 / USR_32)
831 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
832 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
833 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
834 .long __pabt_invalid @ 4
835 .long __pabt_invalid @ 5
836 .long __pabt_invalid @ 6
837 .long __pabt_invalid @ 7
838 .long __pabt_invalid @ 8
839 .long __pabt_invalid @ 9
840 .long __pabt_invalid @ a
841 .long __pabt_invalid @ b
842 .long __pabt_invalid @ c
843 .long __pabt_invalid @ d
844 .long __pabt_invalid @ e
845 .long __pabt_invalid @ f
848 * Undef instr entry dispatcher
849 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
853 .long __und_usr @ 0 (USR_26 / USR_32)
854 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
855 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
856 .long __und_svc @ 3 (SVC_26 / SVC_32)
857 .long __und_invalid @ 4
858 .long __und_invalid @ 5
859 .long __und_invalid @ 6
860 .long __und_invalid @ 7
861 .long __und_invalid @ 8
862 .long __und_invalid @ 9
863 .long __und_invalid @ a
864 .long __und_invalid @ b
865 .long __und_invalid @ c
866 .long __und_invalid @ d
867 .long __und_invalid @ e
868 .long __und_invalid @ f
872 /*=============================================================================
874 *-----------------------------------------------------------------------------
875 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
876 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
877 * Basically to switch modes, we *HAVE* to clobber one register... brain
878 * damage alert! I don't think that we can execute any code in here in any
879 * other mode than FIQ... Ok you can switch to another mode, but you can't
880 * get out of that mode without clobbering one register.
886 /*=============================================================================
887 * Address exception handler
888 *-----------------------------------------------------------------------------
889 * These aren't too critical.
890 * (they're not supposed to happen, and won't happen in 32-bit data mode).
897 * We group all the following data together to optimise
898 * for CPUs with separate I & D caches.
915 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
917 .globl __vectors_start
920 b vector_und + stubs_offset
921 ldr pc, .LCvswi + stubs_offset
922 b vector_pabt + stubs_offset
923 b vector_dabt + stubs_offset
924 b vector_addrexcptn + stubs_offset
925 b vector_irq + stubs_offset
926 b vector_fiq + stubs_offset
934 * Do not reorder these, and do not insert extra data between...
938 .word 0 @ saved lr_irq
939 .word 0 @ saved spsr_irq
942 .word 0 @ Saved lr_und
943 .word 0 @ Saved spsr_und
946 .word 0 @ Saved lr_abt
947 .word 0 @ Saved spsr_abt
951 .globl cr_no_alignment