2 * linux/arch/arm/kernel/arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/smp.h>
16 #include <linux/cpu.h>
17 #include <linux/jiffies.h>
18 #include <linux/clockchips.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_irq.h>
23 #include <asm/cputype.h>
24 #include <asm/localtimer.h>
25 #include <asm/arch_timer.h>
26 #include <asm/system_info.h>
27 #include <asm/sched_clock.h>
29 static unsigned long arch_timer_rate
;
30 static int arch_timer_ppi
;
31 static int arch_timer_ppi2
;
33 static struct clock_event_device __percpu
**arch_timer_evt
;
36 * Architected system timer support.
39 #define ARCH_TIMER_CTRL_ENABLE (1 << 0)
40 #define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
41 #define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
43 #define ARCH_TIMER_REG_CTRL 0
44 #define ARCH_TIMER_REG_FREQ 1
45 #define ARCH_TIMER_REG_TVAL 2
47 static void arch_timer_reg_write(int reg
, u32 val
)
50 case ARCH_TIMER_REG_CTRL
:
51 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val
));
53 case ARCH_TIMER_REG_TVAL
:
54 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val
));
61 static u32
arch_timer_reg_read(int reg
)
66 case ARCH_TIMER_REG_CTRL
:
67 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val
));
69 case ARCH_TIMER_REG_FREQ
:
70 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val
));
72 case ARCH_TIMER_REG_TVAL
:
73 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val
));
82 static irqreturn_t
arch_timer_handler(int irq
, void *dev_id
)
84 struct clock_event_device
*evt
= *(struct clock_event_device
**)dev_id
;
87 ctrl
= arch_timer_reg_read(ARCH_TIMER_REG_CTRL
);
88 if (ctrl
& ARCH_TIMER_CTRL_IT_STAT
) {
89 ctrl
|= ARCH_TIMER_CTRL_IT_MASK
;
90 arch_timer_reg_write(ARCH_TIMER_REG_CTRL
, ctrl
);
91 evt
->event_handler(evt
);
98 static void arch_timer_disable(void)
102 ctrl
= arch_timer_reg_read(ARCH_TIMER_REG_CTRL
);
103 ctrl
&= ~ARCH_TIMER_CTRL_ENABLE
;
104 arch_timer_reg_write(ARCH_TIMER_REG_CTRL
, ctrl
);
107 static void arch_timer_set_mode(enum clock_event_mode mode
,
108 struct clock_event_device
*clk
)
111 case CLOCK_EVT_MODE_UNUSED
:
112 case CLOCK_EVT_MODE_SHUTDOWN
:
113 arch_timer_disable();
120 static int arch_timer_set_next_event(unsigned long evt
,
121 struct clock_event_device
*unused
)
125 ctrl
= arch_timer_reg_read(ARCH_TIMER_REG_CTRL
);
126 ctrl
|= ARCH_TIMER_CTRL_ENABLE
;
127 ctrl
&= ~ARCH_TIMER_CTRL_IT_MASK
;
129 arch_timer_reg_write(ARCH_TIMER_REG_TVAL
, evt
);
130 arch_timer_reg_write(ARCH_TIMER_REG_CTRL
, ctrl
);
135 static int __cpuinit
arch_timer_setup(struct clock_event_device
*clk
)
138 arch_timer_disable();
140 clk
->features
= CLOCK_EVT_FEAT_ONESHOT
;
141 clk
->name
= "arch_sys_timer";
143 clk
->set_mode
= arch_timer_set_mode
;
144 clk
->set_next_event
= arch_timer_set_next_event
;
145 clk
->irq
= arch_timer_ppi
;
147 clockevents_config_and_register(clk
, arch_timer_rate
,
150 *__this_cpu_ptr(arch_timer_evt
) = clk
;
152 enable_percpu_irq(clk
->irq
, 0);
154 enable_percpu_irq(arch_timer_ppi2
, 0);
159 /* Is the optional system timer available? */
160 static int local_timer_is_architected(void)
162 return (cpu_architecture() >= CPU_ARCH_ARMv7
) &&
163 ((read_cpuid_ext(CPUID_EXT_PFR1
) >> 16) & 0xf) == 1;
166 static int arch_timer_available(void)
170 if (!local_timer_is_architected())
173 if (arch_timer_rate
== 0) {
174 arch_timer_reg_write(ARCH_TIMER_REG_CTRL
, 0);
175 freq
= arch_timer_reg_read(ARCH_TIMER_REG_FREQ
);
177 /* Check the timer frequency. */
179 pr_warn("Architected timer frequency not available\n");
183 arch_timer_rate
= freq
;
186 pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
187 arch_timer_rate
/ 1000000, (arch_timer_rate
/ 10000) % 100);
191 static inline cycle_t
arch_counter_get_cntpct(void)
195 asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall
), "=r" (cvalh
));
197 return ((cycle_t
) cvalh
<< 32) | cvall
;
200 static inline cycle_t
arch_counter_get_cntvct(void)
204 asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall
), "=r" (cvalh
));
206 return ((cycle_t
) cvalh
<< 32) | cvall
;
209 static u32 notrace
arch_counter_get_cntvct32(void)
211 cycle_t cntvct
= arch_counter_get_cntvct();
214 * The sched_clock infrastructure only knows about counters
215 * with at most 32bits. Forget about the upper 24 bits for the
218 return (u32
)(cntvct
& (u32
)~0);
221 static cycle_t
arch_counter_read(struct clocksource
*cs
)
223 return arch_counter_get_cntpct();
226 static struct clocksource clocksource_counter
= {
227 .name
= "arch_sys_counter",
229 .read
= arch_counter_read
,
230 .mask
= CLOCKSOURCE_MASK(56),
231 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
234 static void __cpuinit
arch_timer_stop(struct clock_event_device
*clk
)
236 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
237 clk
->irq
, smp_processor_id());
238 disable_percpu_irq(clk
->irq
);
240 disable_percpu_irq(arch_timer_ppi2
);
241 arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED
, clk
);
244 static struct local_timer_ops arch_timer_ops __cpuinitdata
= {
245 .setup
= arch_timer_setup
,
246 .stop
= arch_timer_stop
,
249 static struct clock_event_device arch_timer_global_evt
;
251 static int __init
arch_timer_register(void)
255 err
= arch_timer_available();
259 arch_timer_evt
= alloc_percpu(struct clock_event_device
*);
263 clocksource_register_hz(&clocksource_counter
, arch_timer_rate
);
265 err
= request_percpu_irq(arch_timer_ppi
, arch_timer_handler
,
266 "arch_timer", arch_timer_evt
);
268 pr_err("arch_timer: can't register interrupt %d (%d)\n",
269 arch_timer_ppi
, err
);
273 if (arch_timer_ppi2
) {
274 err
= request_percpu_irq(arch_timer_ppi2
, arch_timer_handler
,
275 "arch_timer", arch_timer_evt
);
277 pr_err("arch_timer: can't register interrupt %d (%d)\n",
278 arch_timer_ppi2
, err
);
284 err
= local_timer_register(&arch_timer_ops
);
287 * We couldn't register as a local timer (could be
288 * because we're on a UP platform, or because some
289 * other local timer is already present...). Try as a
290 * global timer instead.
292 arch_timer_global_evt
.cpumask
= cpumask_of(0);
293 err
= arch_timer_setup(&arch_timer_global_evt
);
302 free_percpu_irq(arch_timer_ppi
, arch_timer_evt
);
304 free_percpu_irq(arch_timer_ppi2
, arch_timer_evt
);
307 free_percpu(arch_timer_evt
);
312 static const struct of_device_id arch_timer_of_match
[] __initconst
= {
313 { .compatible
= "arm,armv7-timer", },
317 int __init
arch_timer_of_register(void)
319 struct device_node
*np
;
322 np
= of_find_matching_node(NULL
, arch_timer_of_match
);
324 pr_err("arch_timer: can't find DT node\n");
328 /* Try to determine the frequency from the device tree or CNTFRQ */
329 if (!of_property_read_u32(np
, "clock-frequency", &freq
))
330 arch_timer_rate
= freq
;
332 arch_timer_ppi
= irq_of_parse_and_map(np
, 0);
333 arch_timer_ppi2
= irq_of_parse_and_map(np
, 1);
334 pr_info("arch_timer: found %s irqs %d %d\n",
335 np
->name
, arch_timer_ppi
, arch_timer_ppi2
);
337 return arch_timer_register();
340 int __init
arch_timer_sched_clock_init(void)
344 err
= arch_timer_available();
348 setup_sched_clock(arch_counter_get_cntvct32
, 32, arch_timer_rate
);