arch/arm/include/asm/system.h

   1 #ifndef __ASM_ARM_SYSTEM_H
   2 #define __ASM_ARM_SYSTEM_H
   3
   4 #ifdef __KERNEL__
   5
   6 #define CPU_ARCH_UNKNOWN        0
   7 #define CPU_ARCH_ARMv3          1
   8 #define CPU_ARCH_ARMv4          2
   9 #define CPU_ARCH_ARMv4T         3
  10 #define CPU_ARCH_ARMv5          4
  11 #define CPU_ARCH_ARMv5T         5
  12 #define CPU_ARCH_ARMv5TE        6
  13 #define CPU_ARCH_ARMv5TEJ       7
  14 #define CPU_ARCH_ARMv6          8
  15 #define CPU_ARCH_ARMv7          9
  16
  17 /*
  18  * CR1 bits (CP#15 CR1)
  19  */
  20 #define CR_M    (1 << 0)        /* MMU enable                           */
  21 #define CR_A    (1 << 1)        /* Alignment abort enable               */
  22 #define CR_C    (1 << 2)        /* Dcache enable                        */
  23 #define CR_W    (1 << 3)        /* Write buffer enable                  */
  24 #define CR_P    (1 << 4)        /* 32-bit exception handler             */
  25 #define CR_D    (1 << 5)        /* 32-bit data address range            */
  26 #define CR_L    (1 << 6)        /* Implementation defined               */
  27 #define CR_B    (1 << 7)        /* Big endian                           */
  28 #define CR_S    (1 << 8)        /* System MMU protection                */
  29 #define CR_R    (1 << 9)        /* ROM MMU protection                   */
  30 #define CR_F    (1 << 10)       /* Implementation defined               */
  31 #define CR_Z    (1 << 11)       /* Implementation defined               */
  32 #define CR_I    (1 << 12)       /* Icache enable                        */
  33 #define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
  34 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
  35 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
  36 #define CR_DT   (1 << 16)
  37 #define CR_IT   (1 << 18)
  38 #define CR_ST   (1 << 19)
  39 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
  40 #define CR_U    (1 << 22)       /* Unaligned access operation           */
  41 #define CR_XP   (1 << 23)       /* Extended page tables                 */
  42 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
  43 #define CR_EE   (1 << 25)       /* Exception (Big) Endian               */
  44 #define CR_TRE  (1 << 28)       /* TEX remap enable                     */
  45 #define CR_AFE  (1 << 29)       /* Access flag enable                   */
  46 #define CR_TE   (1 << 30)       /* Thumb exception enable               */
  47
  48 /*
  49  * This is used to ensure the compiler did actually allocate the register we
  50  * asked it for some inline assembly sequences.  Apparently we can't trust
  51  * the compiler from one version to another so a bit of paranoia won't hurt.
  52  * This string is meant to be concatenated with the inline asm string and
  53  * will cause compilation to stop on mismatch.
  54  * (for details, see gcc PR 15089)
  55  */
  56 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
  57
  58 #ifndef __ASSEMBLY__
  59
  60 #include <linux/linkage.h>
  61 #include <linux/irqflags.h>
  62
  63 #define __exception     __attribute__((section(".exception.text")))
  64
  65 struct thread_info;
  66 struct task_struct;
  67
  68 /* information about the system we're running on */
  69 extern unsigned int system_rev;
  70 extern unsigned int system_serial_low;
  71 extern unsigned int system_serial_high;
  72 extern unsigned int mem_fclk_21285;
  73
  74 struct pt_regs;
  75
  76 void die(const char *msg, struct pt_regs *regs, int err);
  77
  78 struct siginfo;
  79 void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
  80                 unsigned long err, unsigned long trap);
  81
  82 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  83                                        struct pt_regs *),
  84                      int sig, const char *name);
  85
  86 #define xchg(ptr,x) \
  87         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  88
  89 extern asmlinkage void __backtrace(void);
  90 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
  91
  92 struct mm_struct;
  93 extern void show_pte(struct mm_struct *mm, unsigned long addr);
  94 extern void __show_regs(struct pt_regs *);
  95
  96 extern int cpu_architecture(void);
  97 extern void cpu_init(void);
  98
  99 void arm_machine_restart(char mode, const char *cmd);
 100 extern void (*arm_pm_restart)(char str, const char *cmd);
 101
 102 #define UDBG_UNDEFINED  (1 << 0)
 103 #define UDBG_SYSCALL    (1 << 1)
 104 #define UDBG_BADABORT   (1 << 2)
 105 #define UDBG_SEGV       (1 << 3)
 106 #define UDBG_BUS        (1 << 4)
 107
 108 extern unsigned int user_debug;
 109
 110 #if __LINUX_ARM_ARCH__ >= 4
 111 #define vectors_high()  (cr_alignment & CR_V)
 112 #else
 113 #define vectors_high()  (0)
 114 #endif
 115
 116 #if __LINUX_ARM_ARCH__ >= 7
 117 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
 118 #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
 119 #define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
 120 #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
 121 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
 122                                     : : "r" (0) : "memory")
 123 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
 124                                     : : "r" (0) : "memory")
 125 #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
 126                                     : : "r" (0) : "memory")
 127 #elif defined(CONFIG_CPU_FA526)
 128 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
 129                                     : : "r" (0) : "memory")
 130 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
 131                                     : : "r" (0) : "memory")
 132 #define dmb() __asm__ __volatile__ ("" : : : "memory")
 133 #else
 134 #define isb() __asm__ __volatile__ ("" : : : "memory")
 135 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
 136                                     : : "r" (0) : "memory")
 137 #define dmb() __asm__ __volatile__ ("" : : : "memory")
 138 #endif
 139
 140 #if __LINUX_ARM_ARCH__ >= 7 || defined(CONFIG_SMP)
 141 #define mb()            dmb()
 142 #define rmb()           dmb()
 143 #define wmb()           dmb()
 144 #else
 145 #define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 146 #define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 147 #define wmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 148 #endif
 149
 150 #ifndef CONFIG_SMP
 151 #define smp_mb()        barrier()
 152 #define smp_rmb()       barrier()
 153 #define smp_wmb()       barrier()
 154 #else
 155 #define smp_mb()        mb()
 156 #define smp_rmb()       rmb()
 157 #define smp_wmb()       wmb()
 158 #endif
 159
 160 #define read_barrier_depends()          do { } while(0)
 161 #define smp_read_barrier_depends()      do { } while(0)
 162
 163 #define set_mb(var, value)      do { var = value; smp_mb(); } while (0)
 164 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 165
 166 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 167 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 168
 169 static inline unsigned int get_cr(void)
 170 {
 171         unsigned int val;
 172         asm("mrc p15, 0, %0, c1, c0, 0  @ get CR" : "=r" (val) : : "cc");
 173         return val;
 174 }
 175
 176 static inline void set_cr(unsigned int val)
 177 {
 178         asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
 179           : : "r" (val) : "cc");
 180         isb();
 181 }
 182
 183 #ifndef CONFIG_SMP
 184 extern void adjust_cr(unsigned long mask, unsigned long set);
 185 #endif
 186
 187 #define CPACC_FULL(n)           (3 << (n * 2))
 188 #define CPACC_SVC(n)            (1 << (n * 2))
 189 #define CPACC_DISABLE(n)        (0 << (n * 2))
 190
 191 static inline unsigned int get_copro_access(void)
 192 {
 193         unsigned int val;
 194         asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
 195           : "=r" (val) : : "cc");
 196         return val;
 197 }
 198
 199 static inline void set_copro_access(unsigned int val)
 200 {
 201         asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
 202           : : "r" (val) : "cc");
 203         isb();
 204 }
 205
 206 /*
 207  * switch_mm() may do a full cache flush over the context switch,
 208  * so enable interrupts over the context switch to avoid high
 209  * latency.
 210  */
 211 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
 212
 213 /*
 214  * switch_to(prev, next) should switch from task `prev' to `next'
 215  * `prev' will never be the same as `next'.  schedule() itself
 216  * contains the memory barrier to tell GCC not to cache `current'.
 217  */
 218 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
 219
 220 #define switch_to(prev,next,last)                                       \
 221 do {                                                                    \
 222         last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));        \
 223 } while (0)
 224
 225 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 226 /*
 227  * On the StrongARM, "swp" is terminally broken since it bypasses the
 228  * cache totally.  This means that the cache becomes inconsistent, and,
 229  * since we use normal loads/stores as well, this is really bad.
 230  * Typically, this causes oopsen in filp_close, but could have other,
 231  * more disasterous effects.  There are two work-arounds:
 232  *  1. Disable interrupts and emulate the atomic swap
 233  *  2. Clean the cache, perform atomic swap, flush the cache
 234  *
 235  * We choose (1) since its the "easiest" to achieve here and is not
 236  * dependent on the processor type.
 237  *
 238  * NOTE that this solution won't work on an SMP system, so explcitly
 239  * forbid it here.
 240  */
 241 #define swp_is_buggy
 242 #endif
 243
 244 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 245 {
 246         extern void __bad_xchg(volatile void *, int);
 247         unsigned long ret;
 248 #ifdef swp_is_buggy
 249         unsigned long flags;
 250 #endif
 251 #if __LINUX_ARM_ARCH__ >= 6
 252         unsigned int tmp;
 253 #endif
 254
 255         smp_mb();
 256
 257         switch (size) {
 258 #if __LINUX_ARM_ARCH__ >= 6
 259         case 1:
 260                 asm volatile("@ __xchg1\n"
 261                 "1:     ldrexb  %0, [%3]\n"
 262                 "       strexb  %1, %2, [%3]\n"
 263                 "       teq     %1, #0\n"
 264                 "       bne     1b"
 265                         : "=&r" (ret), "=&r" (tmp)
 266                         : "r" (x), "r" (ptr)
 267                         : "memory", "cc");
 268                 break;
 269         case 4:
 270                 asm volatile("@ __xchg4\n"
 271                 "1:     ldrex   %0, [%3]\n"
 272                 "       strex   %1, %2, [%3]\n"
 273                 "       teq     %1, #0\n"
 274                 "       bne     1b"
 275                         : "=&r" (ret), "=&r" (tmp)
 276                         : "r" (x), "r" (ptr)
 277                         : "memory", "cc");
 278                 break;
 279 #elif defined(swp_is_buggy)
 280 #ifdef CONFIG_SMP
 281 #error SMP is not supported on this platform
 282 #endif
 283         case 1:
 284                 raw_local_irq_save(flags);
 285                 ret = *(volatile unsigned char *)ptr;
 286                 *(volatile unsigned char *)ptr = x;
 287                 raw_local_irq_restore(flags);
 288                 break;
 289
 290         case 4:
 291                 raw_local_irq_save(flags);
 292                 ret = *(volatile unsigned long *)ptr;
 293                 *(volatile unsigned long *)ptr = x;
 294                 raw_local_irq_restore(flags);
 295                 break;
 296 #else
 297         case 1:
 298                 asm volatile("@ __xchg1\n"
 299                 "       swpb    %0, %1, [%2]"
 300                         : "=&r" (ret)
 301                         : "r" (x), "r" (ptr)
 302                         : "memory", "cc");
 303                 break;
 304         case 4:
 305                 asm volatile("@ __xchg4\n"
 306                 "       swp     %0, %1, [%2]"
 307                         : "=&r" (ret)
 308                         : "r" (x), "r" (ptr)
 309                         : "memory", "cc");
 310                 break;
 311 #endif
 312         default:
 313                 __bad_xchg(ptr, size), ret = 0;
 314                 break;
 315         }
 316         smp_mb();
 317
 318         return ret;
 319 }
 320
 321 extern void disable_hlt(void);
 322 extern void enable_hlt(void);
 323
 324 #include <asm-generic/cmpxchg-local.h>
 325
 326 #if __LINUX_ARM_ARCH__ < 6
 327
 328 #ifdef CONFIG_SMP
 329 #error "SMP is not supported on this platform"
 330 #endif
 331
 332 /*
 333  * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 334  * them available.
 335  */
 336 #define cmpxchg_local(ptr, o, n)                                               \
 337         ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
 338                         (unsigned long)(n), sizeof(*(ptr))))
 339 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 340
 341 #ifndef CONFIG_SMP
 342 #include <asm-generic/cmpxchg.h>
 343 #endif
 344
 345 #else   /* __LINUX_ARM_ARCH__ >= 6 */
 346
 347 extern void __bad_cmpxchg(volatile void *ptr, int size);
 348
 349 /*
 350  * cmpxchg only support 32-bits operands on ARMv6.
 351  */
 352
 353 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 354                                       unsigned long new, int size)
 355 {
 356         unsigned long oldval, res;
 357
 358         switch (size) {
 359 #ifdef CONFIG_CPU_32v6K
 360         case 1:
 361                 do {
 362                         asm volatile("@ __cmpxchg1\n"
 363                         "       ldrexb  %1, [%2]\n"
 364                         "       mov     %0, #0\n"
 365                         "       teq     %1, %3\n"
 366                         "       strexbeq %0, %4, [%2]\n"
 367                                 : "=&r" (res), "=&r" (oldval)
 368                                 : "r" (ptr), "Ir" (old), "r" (new)
 369                                 : "memory", "cc");
 370                 } while (res);
 371                 break;
 372         case 2:
 373                 do {
 374                         asm volatile("@ __cmpxchg1\n"
 375                         "       ldrexh  %1, [%2]\n"
 376                         "       mov     %0, #0\n"
 377                         "       teq     %1, %3\n"
 378                         "       strexheq %0, %4, [%2]\n"
 379                                 : "=&r" (res), "=&r" (oldval)
 380                                 : "r" (ptr), "Ir" (old), "r" (new)
 381                                 : "memory", "cc");
 382                 } while (res);
 383                 break;
 384 #endif /* CONFIG_CPU_32v6K */
 385         case 4:
 386                 do {
 387                         asm volatile("@ __cmpxchg4\n"
 388                         "       ldrex   %1, [%2]\n"
 389                         "       mov     %0, #0\n"
 390                         "       teq     %1, %3\n"
 391                         "       strexeq %0, %4, [%2]\n"
 392                                 : "=&r" (res), "=&r" (oldval)
 393                                 : "r" (ptr), "Ir" (old), "r" (new)
 394                                 : "memory", "cc");
 395                 } while (res);
 396                 break;
 397         default:
 398                 __bad_cmpxchg(ptr, size);
 399                 oldval = 0;
 400         }
 401
 402         return oldval;
 403 }
 404
 405 static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
 406                                          unsigned long new, int size)
 407 {
 408         unsigned long ret;
 409
 410         smp_mb();
 411         ret = __cmpxchg(ptr, old, new, size);
 412         smp_mb();
 413
 414         return ret;
 415 }
 416
 417 #define cmpxchg(ptr,o,n)                                                \
 418         ((__typeof__(*(ptr)))__cmpxchg_mb((ptr),                        \
 419                                           (unsigned long)(o),           \
 420                                           (unsigned long)(n),           \
 421                                           sizeof(*(ptr))))
 422
 423 static inline unsigned long __cmpxchg_local(volatile void *ptr,
 424                                             unsigned long old,
 425                                             unsigned long new, int size)
 426 {
 427         unsigned long ret;
 428
 429         switch (size) {
 430 #ifndef CONFIG_CPU_32v6K
 431         case 1:
 432         case 2:
 433                 ret = __cmpxchg_local_generic(ptr, old, new, size);
 434                 break;
 435 #endif  /* !CONFIG_CPU_32v6K */
 436         default:
 437                 ret = __cmpxchg(ptr, old, new, size);
 438         }
 439
 440         return ret;
 441 }
 442
 443 #define cmpxchg_local(ptr,o,n)                                          \
 444         ((__typeof__(*(ptr)))__cmpxchg_local((ptr),                     \
 445                                        (unsigned long)(o),              \
 446                                        (unsigned long)(n),              \
 447                                        sizeof(*(ptr))))
 448
 449 #ifdef CONFIG_CPU_32v6K
 450
 451 /*
 452  * Note : ARMv7-M (currently unsupported by Linux) does not support
 453  * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
 454  * not be allowed to use __cmpxchg64.
 455  */
 456 static inline unsigned long long __cmpxchg64(volatile void *ptr,
 457                                              unsigned long long old,
 458                                              unsigned long long new)
 459 {
 460         register unsigned long long oldval asm("r0");
 461         register unsigned long long __old asm("r2") = old;
 462         register unsigned long long __new asm("r4") = new;
 463         unsigned long res;
 464
 465         do {
 466                 asm volatile(
 467                 "       @ __cmpxchg8\n"
 468                 "       ldrexd  %1, %H1, [%2]\n"
 469                 "       mov     %0, #0\n"
 470                 "       teq     %1, %3\n"
 471                 "       teqeq   %H1, %H3\n"
 472                 "       strexdeq %0, %4, %H4, [%2]\n"
 473                         : "=&r" (res), "=&r" (oldval)
 474                         : "r" (ptr), "Ir" (__old), "r" (__new)
 475                         : "memory", "cc");
 476         } while (res);
 477
 478         return oldval;
 479 }
 480
 481 static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
 482                                                 unsigned long long old,
 483                                                 unsigned long long new)
 484 {
 485         unsigned long long ret;
 486
 487         smp_mb();
 488         ret = __cmpxchg64(ptr, old, new);
 489         smp_mb();
 490
 491         return ret;
 492 }
 493
 494 #define cmpxchg64(ptr,o,n)                                              \
 495         ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),                      \
 496                                             (unsigned long long)(o),    \
 497                                             (unsigned long long)(n)))
 498
 499 #define cmpxchg64_local(ptr,o,n)                                        \
 500         ((__typeof__(*(ptr)))__cmpxchg64((ptr),                         \
 501                                          (unsigned long long)(o),       \
 502                                          (unsigned long long)(n)))
 503
 504 #else   /* !CONFIG_CPU_32v6K */
 505
 506 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 507
 508 #endif  /* CONFIG_CPU_32v6K */
 509
 510 #endif  /* __LINUX_ARM_ARCH__ >= 6 */
 511
 512 #endif /* __ASSEMBLY__ */
 513
 514 #define arch_align_stack(x) (x)
 515
 516 #endif /* __KERNEL__ */
 517
 518 #endif