arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPIDR     5
  12 #define CPUID_REVIDR    6
  13
  14 #define CPUID_EXT_PFR0  "c1, 0"
  15 #define CPUID_EXT_PFR1  "c1, 1"
  16 #define CPUID_EXT_DFR0  "c1, 2"
  17 #define CPUID_EXT_AFR0  "c1, 3"
  18 #define CPUID_EXT_MMFR0 "c1, 4"
  19 #define CPUID_EXT_MMFR1 "c1, 5"
  20 #define CPUID_EXT_MMFR2 "c1, 6"
  21 #define CPUID_EXT_MMFR3 "c1, 7"
  22 #define CPUID_EXT_ISAR0 "c2, 0"
  23 #define CPUID_EXT_ISAR1 "c2, 1"
  24 #define CPUID_EXT_ISAR2 "c2, 2"
  25 #define CPUID_EXT_ISAR3 "c2, 3"
  26 #define CPUID_EXT_ISAR4 "c2, 4"
  27 #define CPUID_EXT_ISAR5 "c2, 5"
  28
  29 #define MPIDR_SMP_BITMASK (0x3 << 30)
  30 #define MPIDR_SMP_VALUE (0x2 << 30)
  31
  32 #define MPIDR_MT_BITMASK (0x1 << 24)
  33
  34 #define MPIDR_HWID_BITMASK 0xFFFFFF
  35
  36 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  37
  38 #define MPIDR_LEVEL_BITS 8
  39 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  40
  41 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  42         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  43
  44 #define ARM_CPU_IMP_ARM                 0x41
  45 #define ARM_CPU_IMP_INTEL               0x69
  46
  47 #define ARM_CPU_PART_ARM1136            0xB360
  48 #define ARM_CPU_PART_ARM1156            0xB560
  49 #define ARM_CPU_PART_ARM1176            0xB760
  50 #define ARM_CPU_PART_ARM11MPCORE        0xB020
  51 #define ARM_CPU_PART_CORTEX_A8          0xC080
  52 #define ARM_CPU_PART_CORTEX_A9          0xC090
  53 #define ARM_CPU_PART_CORTEX_A5          0xC050
  54 #define ARM_CPU_PART_CORTEX_A15         0xC0F0
  55 #define ARM_CPU_PART_CORTEX_A7          0xC070
  56 #define ARM_CPU_PART_CORTEX_A12         0xC0D0
  57 #define ARM_CPU_PART_CORTEX_A17         0xC0E0
  58 #define ARM_CPU_PART_CORTEX_A53         0xD030
  59
  60 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  61 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  62 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  63 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  64
  65 /* Qualcomm implemented cores */
  66 #define ARM_CPU_PART_SCORPION           0x510002d0
  67
  68 extern unsigned int processor_id;
  69
  70 #ifdef CONFIG_CPU_CP15
  71 #define read_cpuid(reg)                                                 \
  72         ({                                                              \
  73                 unsigned int __val;                                     \
  74                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  75                     : "=r" (__val)                                      \
  76                     :                                                   \
  77                     : "cc");                                            \
  78                 __val;                                                  \
  79         })
  80
  81 #define read_cpuid_ext(ext_reg)                                         \
  82         ({                                                              \
  83                 unsigned int __val;                                     \
  84                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
  85                     : "=r" (__val)                                      \
  86                     :                                                   \
  87                     : "cc");                                            \
  88                 __val;                                                  \
  89         })
  90
  91 #else /* ifdef CONFIG_CPU_CP15 */
  92
  93 /*
  94  * read_cpuid and read_cpuid_ext should only ever be called on machines that
  95  * have cp15 so warn on other usages.
  96  */
  97 #define read_cpuid(reg)                                                 \
  98         ({                                                              \
  99                 WARN_ON_ONCE(1);                                        \
 100                 0;                                                      \
 101         })
 102
 103 #define read_cpuid_ext(reg) read_cpuid(reg)
 104
 105 #endif /* ifdef CONFIG_CPU_CP15 / else */
 106
 107 #ifdef CONFIG_CPU_CP15
 108 /*
 109  * The CPU ID never changes at run time, so we might as well tell the
 110  * compiler that it's constant.  Use this function to read the CPU ID
 111  * rather than directly reading processor_id or read_cpuid() directly.
 112  */
 113 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 114 {
 115         return read_cpuid(CPUID_ID);
 116 }
 117
 118 #else /* ifdef CONFIG_CPU_CP15 */
 119
 120 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 121 {
 122         return processor_id;
 123 }
 124
 125 #endif /* ifdef CONFIG_CPU_CP15 / else */
 126
 127 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 128 {
 129         return (read_cpuid_id() & 0xFF000000) >> 24;
 130 }
 131
 132 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 133 {
 134         return read_cpuid_id() & 0xFFF0;
 135 }
 136
 137 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 138 {
 139         return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
 140 }
 141
 142 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 143 {
 144         return read_cpuid(CPUID_CACHETYPE);
 145 }
 146
 147 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 148 {
 149         return read_cpuid(CPUID_TCM);
 150 }
 151
 152 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 153 {
 154         return read_cpuid(CPUID_MPIDR);
 155 }
 156
 157 /*
 158  * Intel's XScale3 core supports some v6 features (supersections, L2)
 159  * but advertises itself as v5 as it does not support the v6 ISA.  For
 160  * this reason, we need a way to explicitly test for this type of CPU.
 161  */
 162 #ifndef CONFIG_CPU_XSC3
 163 #define cpu_is_xsc3()   0
 164 #else
 165 static inline int cpu_is_xsc3(void)
 166 {
 167         unsigned int id;
 168         id = read_cpuid_id() & 0xffffe000;
 169         /* It covers both Intel ID and Marvell ID */
 170         if ((id == 0x69056000) || (id == 0x56056000))
 171                 return 1;
 172
 173         return 0;
 174 }
 175 #endif
 176
 177 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
 178 #define cpu_is_xscale() 0
 179 #else
 180 #define cpu_is_xscale() 1
 181 #endif
 182
 183 #endif