arch/arm/include/asm/barrier.h

   1 #ifndef __ASM_BARRIER_H
   2 #define __ASM_BARRIER_H
   3
   4 #ifndef __ASSEMBLY__
   5 #include <asm/outercache.h>
   6
   7 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
   8
   9 #if __LINUX_ARM_ARCH__ >= 7 ||          \
  10         (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
  11 #define sev()   __asm__ __volatile__ ("sev" : : : "memory")
  12 #define wfe()   __asm__ __volatile__ ("wfe" : : : "memory")
  13 #define wfi()   __asm__ __volatile__ ("wfi" : : : "memory")
  14 #endif
  15
  16 #if __LINUX_ARM_ARCH__ >= 7
  17 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
  18 #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
  19 #define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
  20 #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
  21 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
  22                                     : : "r" (0) : "memory")
  23 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
  24                                     : : "r" (0) : "memory")
  25 #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
  26                                     : : "r" (0) : "memory")
  27 #elif defined(CONFIG_CPU_FA526)
  28 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
  29                                     : : "r" (0) : "memory")
  30 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
  31                                     : : "r" (0) : "memory")
  32 #define dmb() __asm__ __volatile__ ("" : : : "memory")
  33 #else
  34 #define isb() __asm__ __volatile__ ("" : : : "memory")
  35 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
  36                                     : : "r" (0) : "memory")
  37 #define dmb() __asm__ __volatile__ ("" : : : "memory")
  38 #endif
  39
  40 #ifdef CONFIG_ARCH_HAS_BARRIERS
  41 #include <mach/barriers.h>
  42 #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
  43 #define mb()            do { dsb(); outer_sync(); } while (0)
  44 #define rmb()           dsb()
  45 #define wmb()           mb()
  46 #else
  47 #define mb()            barrier()
  48 #define rmb()           barrier()
  49 #define wmb()           barrier()
  50 #endif
  51
  52 #ifndef CONFIG_SMP
  53 #define smp_mb()        barrier()
  54 #define smp_rmb()       barrier()
  55 #define smp_wmb()       barrier()
  56 #else
  57 #define smp_mb()        dmb()
  58 #define smp_rmb()       dmb()
  59 #define smp_wmb()       dmb()
  60 #endif
  61
  62 #define smp_store_release(p, v)                                         \
  63 do {                                                                    \
  64         compiletime_assert_atomic_type(*p);                             \
  65         smp_mb();                                                       \
  66         ACCESS_ONCE(*p) = (v);                                          \
  67 } while (0)
  68
  69 #define smp_load_acquire(p)                                             \
  70 ({                                                                      \
  71         typeof(*p) ___p1 = ACCESS_ONCE(*p);                             \
  72         compiletime_assert_atomic_type(*p);                             \
  73         smp_mb();                                                       \
  74         ___p1;                                                          \
  75 })
  76
  77 #define read_barrier_depends()          do { } while(0)
  78 #define smp_read_barrier_depends()      do { } while(0)
  79
  80 #define set_mb(var, value)      do { var = value; smp_mb(); } while (0)
  81
  82 #endif /* !__ASSEMBLY__ */
  83 #endif /* __ASM_BARRIER_H */