arch/arm/boot/dts/wm8505.dtsi

   1 /*
   2  * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
   3  *
   4  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "wm,wm8505";
  13
  14         cpus {
  15                 cpu@0 {
  16                         compatible = "arm,arm926ejs";
  17                 };
  18         };
  19
  20         soc {
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 compatible = "simple-bus";
  24                 ranges;
  25                 interrupt-parent = <&intc0>;
  26
  27                 intc0: interrupt-controller@d8140000 {
  28                         compatible = "via,vt8500-intc";
  29                         interrupt-controller;
  30                         reg = <0xd8140000 0x10000>;
  31                         #interrupt-cells = <1>;
  32                 };
  33
  34                 /* Secondary IC cascaded to intc0 */
  35                 intc1: interrupt-controller@d8150000 {
  36                         compatible = "via,vt8500-intc";
  37                         interrupt-controller;
  38                         #interrupt-cells = <1>;
  39                         reg = <0xD8150000 0x10000>;
  40                         interrupts = <56 57 58 59 60 61 62 63>;
  41                 };
  42
  43                 pinctrl: pinctrl@d8110000 {
  44                         compatible = "wm,wm8505-pinctrl";
  45                         reg = <0xd8110000 0x10000>;
  46                         interrupt-controller;
  47                         #interrupt-cells = <2>;
  48                         gpio-controller;
  49                         #gpio-cells = <2>;
  50                 };
  51
  52                 pmc@d8130000 {
  53                         compatible = "via,vt8500-pmc";
  54                         reg = <0xd8130000 0x1000>;
  55                         clocks {
  56                                 #address-cells = <1>;
  57                                 #size-cells = <0>;
  58
  59                                 ref24: ref24M {
  60                                         #clock-cells = <0>;
  61                                         compatible = "fixed-clock";
  62                                         clock-frequency = <24000000>;
  63                                 };
  64
  65                                 clkuart0: uart0 {
  66                                         #clock-cells = <0>;
  67                                         compatible = "via,vt8500-device-clock";
  68                                         clocks = <&ref24>;
  69                                         enable-reg = <0x250>;
  70                                         enable-bit = <1>;
  71                                 };
  72
  73                                 clkuart1: uart1 {
  74                                         #clock-cells = <0>;
  75                                         compatible = "via,vt8500-device-clock";
  76                                         clocks = <&ref24>;
  77                                         enable-reg = <0x250>;
  78                                         enable-bit = <2>;
  79                                 };
  80
  81                                 clkuart2: uart2 {
  82                                         #clock-cells = <0>;
  83                                         compatible = "via,vt8500-device-clock";
  84                                         clocks = <&ref24>;
  85                                         enable-reg = <0x250>;
  86                                         enable-bit = <3>;
  87                                 };
  88
  89                                 clkuart3: uart3 {
  90                                         #clock-cells = <0>;
  91                                         compatible = "via,vt8500-device-clock";
  92                                         clocks = <&ref24>;
  93                                         enable-reg = <0x250>;
  94                                         enable-bit = <4>;
  95                                 };
  96
  97                                 clkuart4: uart4 {
  98                                         #clock-cells = <0>;
  99                                         compatible = "via,vt8500-device-clock";
 100                                         clocks = <&ref24>;
 101                                         enable-reg = <0x250>;
 102                                         enable-bit = <22>;
 103                                 };
 104
 105                                 clkuart5: uart5 {
 106                                         #clock-cells = <0>;
 107                                         compatible = "via,vt8500-device-clock";
 108                                         clocks = <&ref24>;
 109                                         enable-reg = <0x250>;
 110                                         enable-bit = <23>;
 111                                 };
 112                         };
 113                 };
 114
 115                 timer@d8130100 {
 116                         compatible = "via,vt8500-timer";
 117                         reg = <0xd8130100 0x28>;
 118                         interrupts = <36>;
 119                 };
 120
 121                 ehci@d8007100 {
 122                         compatible = "via,vt8500-ehci";
 123                         reg = <0xd8007100 0x200>;
 124                         interrupts = <1>;
 125                 };
 126
 127                 uhci@d8007300 {
 128                         compatible = "platform-uhci";
 129                         reg = <0xd8007300 0x200>;
 130                         interrupts = <0>;
 131                 };
 132
 133                 fb@d8050800 {
 134                         compatible = "wm,wm8505-fb";
 135                         reg = <0xd8050800 0x200>;
 136                         display = <&display>;
 137                         default-mode = <&mode0>;
 138                 };
 139
 140                 ge_rops@d8050400 {
 141                         compatible = "wm,prizm-ge-rops";
 142                         reg = <0xd8050400 0x100>;
 143                 };
 144
 145                 uart@d8200000 {
 146                         compatible = "via,vt8500-uart";
 147                         reg = <0xd8200000 0x1040>;
 148                         interrupts = <32>;
 149                         clocks = <&clkuart0>;
 150                 };
 151
 152                 uart@d82b0000 {
 153                         compatible = "via,vt8500-uart";
 154                         reg = <0xd82b0000 0x1040>;
 155                         interrupts = <33>;
 156                         clocks = <&clkuart1>;
 157                 };
 158
 159                 uart@d8210000 {
 160                         compatible = "via,vt8500-uart";
 161                         reg = <0xd8210000 0x1040>;
 162                         interrupts = <47>;
 163                         clocks = <&clkuart2>;
 164                 };
 165
 166                 uart@d82c0000 {
 167                         compatible = "via,vt8500-uart";
 168                         reg = <0xd82c0000 0x1040>;
 169                         interrupts = <50>;
 170                         clocks = <&clkuart3>;
 171                 };
 172
 173                 uart@d8370000 {
 174                         compatible = "via,vt8500-uart";
 175                         reg = <0xd8370000 0x1040>;
 176                         interrupts = <31>;
 177                         clocks = <&clkuart4>;
 178                 };
 179
 180                 uart@d8380000 {
 181                         compatible = "via,vt8500-uart";
 182                         reg = <0xd8380000 0x1040>;
 183                         interrupts = <30>;
 184                         clocks = <&clkuart5>;
 185                 };
 186
 187                 rtc@d8100000 {
 188                         compatible = "via,vt8500-rtc";
 189                         reg = <0xd8100000 0x10000>;
 190                         interrupts = <48>;
 191                 };
 192         };
 193 };