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Merge tag 'omap-for-v3.10/fixes-for-merge-window' of git://git.kernel.org/pub/scm...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / dts / at91sam9x5.dtsi
1 /*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12 /include/ "skeleton.dtsi"
13
14 / {
15 model = "Atmel AT91SAM9x5 family SoC";
16 compatible = "atmel,at91sam9x5";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 tcb0 = &tcb0;
29 tcb1 = &tcb1;
30 i2c0 = &i2c0;
31 i2c1 = &i2c1;
32 i2c2 = &i2c2;
33 ssc0 = &ssc0;
34 };
35 cpus {
36 cpu@0 {
37 compatible = "arm,arm926ejs";
38 };
39 };
40
41 memory {
42 reg = <0x20000000 0x10000000>;
43 };
44
45 ahb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
51 apb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 aic: interrupt-controller@fffff000 {
58 #interrupt-cells = <3>;
59 compatible = "atmel,at91rm9200-aic";
60 interrupt-controller;
61 reg = <0xfffff000 0x200>;
62 atmel,external-irqs = <31>;
63 };
64
65 ramc0: ramc@ffffe800 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe800 0x200>;
68 };
69
70 pmc: pmc@fffffc00 {
71 compatible = "atmel,at91rm9200-pmc";
72 reg = <0xfffffc00 0x100>;
73 };
74
75 rstc@fffffe00 {
76 compatible = "atmel,at91sam9g45-rstc";
77 reg = <0xfffffe00 0x10>;
78 };
79
80 shdwc@fffffe10 {
81 compatible = "atmel,at91sam9x5-shdwc";
82 reg = <0xfffffe10 0x10>;
83 };
84
85 pit: timer@fffffe30 {
86 compatible = "atmel,at91sam9260-pit";
87 reg = <0xfffffe30 0xf>;
88 interrupts = <1 4 7>;
89 };
90
91 tcb0: timer@f8008000 {
92 compatible = "atmel,at91sam9x5-tcb";
93 reg = <0xf8008000 0x100>;
94 interrupts = <17 4 0>;
95 };
96
97 tcb1: timer@f800c000 {
98 compatible = "atmel,at91sam9x5-tcb";
99 reg = <0xf800c000 0x100>;
100 interrupts = <17 4 0>;
101 };
102
103 dma0: dma-controller@ffffec00 {
104 compatible = "atmel,at91sam9g45-dma";
105 reg = <0xffffec00 0x200>;
106 interrupts = <20 4 0>;
107 #dma-cells = <2>;
108 };
109
110 dma1: dma-controller@ffffee00 {
111 compatible = "atmel,at91sam9g45-dma";
112 reg = <0xffffee00 0x200>;
113 interrupts = <21 4 0>;
114 #dma-cells = <2>;
115 };
116
117 pinctrl@fffff400 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
121 ranges = <0xfffff400 0xfffff400 0x800>;
122
123 /* shared pinctrl settings */
124 dbgu {
125 pinctrl_dbgu: dbgu-0 {
126 atmel,pins =
127 <0 9 0x1 0x0 /* PA9 periph A */
128 0 10 0x1 0x1>; /* PA10 periph A with pullup */
129 };
130 };
131
132 usart0 {
133 pinctrl_usart0: usart0-0 {
134 atmel,pins =
135 <0 0 0x1 0x1 /* PA0 periph A with pullup */
136 0 1 0x1 0x0>; /* PA1 periph A */
137 };
138
139 pinctrl_usart0_rts: usart0_rts-0 {
140 atmel,pins =
141 <0 2 0x1 0x0>; /* PA2 periph A */
142 };
143
144 pinctrl_usart0_cts: usart0_cts-0 {
145 atmel,pins =
146 <0 3 0x1 0x0>; /* PA3 periph A */
147 };
148
149 pinctrl_usart0_sck: usart0_sck-0 {
150 atmel,pins =
151 <0 4 0x1 0x0>; /* PA4 periph A */
152 };
153 };
154
155 usart1 {
156 pinctrl_usart1: usart1-0 {
157 atmel,pins =
158 <0 5 0x1 0x1 /* PA5 periph A with pullup */
159 0 6 0x1 0x0>; /* PA6 periph A */
160 };
161
162 pinctrl_usart1_rts: usart1_rts-0 {
163 atmel,pins =
164 <2 27 0x3 0x0>; /* PC27 periph C */
165 };
166
167 pinctrl_usart1_cts: usart1_cts-0 {
168 atmel,pins =
169 <2 28 0x3 0x0>; /* PC28 periph C */
170 };
171
172 pinctrl_usart1_sck: usart1_sck-0 {
173 atmel,pins =
174 <2 28 0x3 0x0>; /* PC29 periph C */
175 };
176 };
177
178 usart2 {
179 pinctrl_usart2: usart2-0 {
180 atmel,pins =
181 <0 7 0x1 0x1 /* PA7 periph A with pullup */
182 0 8 0x1 0x0>; /* PA8 periph A */
183 };
184
185 pinctrl_uart2_rts: uart2_rts-0 {
186 atmel,pins =
187 <1 0 0x2 0x0>; /* PB0 periph B */
188 };
189
190 pinctrl_uart2_cts: uart2_cts-0 {
191 atmel,pins =
192 <1 1 0x2 0x0>; /* PB1 periph B */
193 };
194
195 pinctrl_usart2_sck: usart2_sck-0 {
196 atmel,pins =
197 <1 2 0x2 0x0>; /* PB2 periph B */
198 };
199 };
200
201 usart3 {
202 pinctrl_usart3: usart3-0 {
203 atmel,pins =
204 <2 22 0x2 0x1 /* PC22 periph B with pullup */
205 2 23 0x2 0x0>; /* PC23 periph B */
206 };
207
208 pinctrl_usart3_rts: usart3_rts-0 {
209 atmel,pins =
210 <2 24 0x2 0x0>; /* PC24 periph B */
211 };
212
213 pinctrl_usart3_cts: usart3_cts-0 {
214 atmel,pins =
215 <2 25 0x2 0x0>; /* PC25 periph B */
216 };
217
218 pinctrl_usart3_sck: usart3_sck-0 {
219 atmel,pins =
220 <2 26 0x2 0x0>; /* PC26 periph B */
221 };
222 };
223
224 uart0 {
225 pinctrl_uart0: uart0-0 {
226 atmel,pins =
227 <2 8 0x3 0x0 /* PC8 periph C */
228 2 9 0x3 0x1>; /* PC9 periph C with pullup */
229 };
230 };
231
232 uart1 {
233 pinctrl_uart1: uart1-0 {
234 atmel,pins =
235 <2 16 0x3 0x0 /* PC16 periph C */
236 2 17 0x3 0x1>; /* PC17 periph C with pullup */
237 };
238 };
239
240 nand {
241 pinctrl_nand: nand-0 {
242 atmel,pins =
243 <3 0 0x1 0x0 /* PD0 periph A Read Enable */
244 3 1 0x1 0x0 /* PD1 periph A Write Enable */
245 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */
246 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */
247 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */
248 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */
249 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */
250 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */
251 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */
252 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */
253 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */
254 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */
255 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */
256 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
257 };
258
259 pinctrl_nand_16bits: nand_16bits-0 {
260 atmel,pins =
261 <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */
262 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */
263 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */
264 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */
265 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */
266 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */
267 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */
268 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
269 };
270 };
271
272 macb0 {
273 pinctrl_macb0_rmii: macb0_rmii-0 {
274 atmel,pins =
275 <1 0 0x1 0x0 /* PB0 periph A */
276 1 1 0x1 0x0 /* PB1 periph A */
277 1 2 0x1 0x0 /* PB2 periph A */
278 1 3 0x1 0x0 /* PB3 periph A */
279 1 4 0x1 0x0 /* PB4 periph A */
280 1 5 0x1 0x0 /* PB5 periph A */
281 1 6 0x1 0x0 /* PB6 periph A */
282 1 7 0x1 0x0 /* PB7 periph A */
283 1 9 0x1 0x0 /* PB9 periph A */
284 1 10 0x1 0x0>; /* PB10 periph A */
285 };
286
287 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
288 atmel,pins =
289 <1 8 0x1 0x0 /* PB8 periph A */
290 1 11 0x1 0x0 /* PB11 periph A */
291 1 12 0x1 0x0 /* PB12 periph A */
292 1 13 0x1 0x0 /* PB13 periph A */
293 1 14 0x1 0x0 /* PB14 periph A */
294 1 15 0x1 0x0 /* PB15 periph A */
295 1 16 0x1 0x0 /* PB16 periph A */
296 1 17 0x1 0x0>; /* PB17 periph A */
297 };
298 };
299
300 mmc0 {
301 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
302 atmel,pins =
303 <0 17 0x1 0x0 /* PA17 periph A */
304 0 16 0x1 0x1 /* PA16 periph A with pullup */
305 0 15 0x1 0x1>; /* PA15 periph A with pullup */
306 };
307
308 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
309 atmel,pins =
310 <0 18 0x1 0x1 /* PA18 periph A with pullup */
311 0 19 0x1 0x1 /* PA19 periph A with pullup */
312 0 20 0x1 0x1>; /* PA20 periph A with pullup */
313 };
314 };
315
316 mmc1 {
317 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
318 atmel,pins =
319 <0 13 0x2 0x0 /* PA13 periph B */
320 0 12 0x2 0x1 /* PA12 periph B with pullup */
321 0 11 0x2 0x1>; /* PA11 periph B with pullup */
322 };
323
324 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
325 atmel,pins =
326 <0 2 0x2 0x1 /* PA2 periph B with pullup */
327 0 3 0x2 0x1 /* PA3 periph B with pullup */
328 0 4 0x2 0x1>; /* PA4 periph B with pullup */
329 };
330 };
331
332 ssc0 {
333 pinctrl_ssc0_tx: ssc0_tx-0 {
334 atmel,pins =
335 <0 24 0x2 0x0 /* PA24 periph B */
336 0 25 0x2 0x0 /* PA25 periph B */
337 0 26 0x2 0x0>; /* PA26 periph B */
338 };
339
340 pinctrl_ssc0_rx: ssc0_rx-0 {
341 atmel,pins =
342 <0 27 0x2 0x0 /* PA27 periph B */
343 0 28 0x2 0x0 /* PA28 periph B */
344 0 29 0x2 0x0>; /* PA29 periph B */
345 };
346 };
347
348 pioA: gpio@fffff400 {
349 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
350 reg = <0xfffff400 0x200>;
351 interrupts = <2 4 1>;
352 #gpio-cells = <2>;
353 gpio-controller;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 };
357
358 pioB: gpio@fffff600 {
359 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
360 reg = <0xfffff600 0x200>;
361 interrupts = <2 4 1>;
362 #gpio-cells = <2>;
363 gpio-controller;
364 #gpio-lines = <19>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
367 };
368
369 pioC: gpio@fffff800 {
370 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
371 reg = <0xfffff800 0x200>;
372 interrupts = <3 4 1>;
373 #gpio-cells = <2>;
374 gpio-controller;
375 interrupt-controller;
376 #interrupt-cells = <2>;
377 };
378
379 pioD: gpio@fffffa00 {
380 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
381 reg = <0xfffffa00 0x200>;
382 interrupts = <3 4 1>;
383 #gpio-cells = <2>;
384 gpio-controller;
385 #gpio-lines = <22>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 };
389 };
390
391 ssc0: ssc@f0010000 {
392 compatible = "atmel,at91sam9g45-ssc";
393 reg = <0xf0010000 0x4000>;
394 interrupts = <28 4 5>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
397 status = "disabled";
398 };
399
400 mmc0: mmc@f0008000 {
401 compatible = "atmel,hsmci";
402 reg = <0xf0008000 0x600>;
403 interrupts = <12 4 0>;
404 dmas = <&dma0 1 0>;
405 dma-names = "rxtx";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 status = "disabled";
409 };
410
411 mmc1: mmc@f000c000 {
412 compatible = "atmel,hsmci";
413 reg = <0xf000c000 0x600>;
414 interrupts = <26 4 0>;
415 dmas = <&dma1 1 0>;
416 dma-names = "rxtx";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 status = "disabled";
420 };
421
422 dbgu: serial@fffff200 {
423 compatible = "atmel,at91sam9260-usart";
424 reg = <0xfffff200 0x200>;
425 interrupts = <1 4 7>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_dbgu>;
428 status = "disabled";
429 };
430
431 usart0: serial@f801c000 {
432 compatible = "atmel,at91sam9260-usart";
433 reg = <0xf801c000 0x200>;
434 interrupts = <5 4 5>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_usart0>;
437 status = "disabled";
438 };
439
440 usart1: serial@f8020000 {
441 compatible = "atmel,at91sam9260-usart";
442 reg = <0xf8020000 0x200>;
443 interrupts = <6 4 5>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_usart1>;
446 status = "disabled";
447 };
448
449 usart2: serial@f8024000 {
450 compatible = "atmel,at91sam9260-usart";
451 reg = <0xf8024000 0x200>;
452 interrupts = <7 4 5>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_usart2>;
455 status = "disabled";
456 };
457
458 macb0: ethernet@f802c000 {
459 compatible = "cdns,at32ap7000-macb", "cdns,macb";
460 reg = <0xf802c000 0x100>;
461 interrupts = <24 4 3>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_macb0_rmii>;
464 status = "disabled";
465 };
466
467 macb1: ethernet@f8030000 {
468 compatible = "cdns,at32ap7000-macb", "cdns,macb";
469 reg = <0xf8030000 0x100>;
470 interrupts = <27 4 3>;
471 status = "disabled";
472 };
473
474 i2c0: i2c@f8010000 {
475 compatible = "atmel,at91sam9x5-i2c";
476 reg = <0xf8010000 0x100>;
477 interrupts = <9 4 6>;
478 dmas = <&dma0 1 7>,
479 <&dma0 1 8>;
480 dma-names = "tx", "rx";
481 #address-cells = <1>;
482 #size-cells = <0>;
483 status = "disabled";
484 };
485
486 i2c1: i2c@f8014000 {
487 compatible = "atmel,at91sam9x5-i2c";
488 reg = <0xf8014000 0x100>;
489 interrupts = <10 4 6>;
490 dmas = <&dma1 1 5>,
491 <&dma1 1 6>;
492 dma-names = "tx", "rx";
493 #address-cells = <1>;
494 #size-cells = <0>;
495 status = "disabled";
496 };
497
498 i2c2: i2c@f8018000 {
499 compatible = "atmel,at91sam9x5-i2c";
500 reg = <0xf8018000 0x100>;
501 interrupts = <11 4 6>;
502 dmas = <&dma0 1 9>,
503 <&dma0 1 10>;
504 dma-names = "tx", "rx";
505 #address-cells = <1>;
506 #size-cells = <0>;
507 status = "disabled";
508 };
509
510 adc0: adc@f804c000 {
511 compatible = "atmel,at91sam9260-adc";
512 reg = <0xf804c000 0x100>;
513 interrupts = <19 4 0>;
514 atmel,adc-use-external;
515 atmel,adc-channels-used = <0xffff>;
516 atmel,adc-vref = <3300>;
517 atmel,adc-num-channels = <12>;
518 atmel,adc-startup-time = <40>;
519 atmel,adc-channel-base = <0x50>;
520 atmel,adc-drdy-mask = <0x1000000>;
521 atmel,adc-status-register = <0x30>;
522 atmel,adc-trigger-register = <0xc0>;
523
524 trigger@0 {
525 trigger-name = "external-rising";
526 trigger-value = <0x1>;
527 trigger-external;
528 };
529
530 trigger@1 {
531 trigger-name = "external-falling";
532 trigger-value = <0x2>;
533 trigger-external;
534 };
535
536 trigger@2 {
537 trigger-name = "external-any";
538 trigger-value = <0x3>;
539 trigger-external;
540 };
541
542 trigger@3 {
543 trigger-name = "continuous";
544 trigger-value = <0x6>;
545 };
546 };
547 };
548
549 nand0: nand@40000000 {
550 compatible = "atmel,at91rm9200-nand";
551 #address-cells = <1>;
552 #size-cells = <1>;
553 reg = <0x40000000 0x10000000
554 0xffffe000 0x600 /* PMECC Registers */
555 0xffffe600 0x200 /* PMECC Error Location Registers */
556 0x00108000 0x18000 /* PMECC looup table in ROM code */
557 >;
558 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
559 atmel,nand-addr-offset = <21>;
560 atmel,nand-cmd-offset = <22>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_nand>;
563 gpios = <&pioD 5 0
564 &pioD 4 0
565 0
566 >;
567 status = "disabled";
568 };
569
570 usb0: ohci@00600000 {
571 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
572 reg = <0x00600000 0x100000>;
573 interrupts = <22 4 2>;
574 status = "disabled";
575 };
576
577 usb1: ehci@00700000 {
578 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
579 reg = <0x00700000 0x100000>;
580 interrupts = <22 4 2>;
581 status = "disabled";
582 };
583 };
584
585 i2c@0 {
586 compatible = "i2c-gpio";
587 gpios = <&pioA 30 0 /* sda */
588 &pioA 31 0 /* scl */
589 >;
590 i2c-gpio,sda-open-drain;
591 i2c-gpio,scl-open-drain;
592 i2c-gpio,delay-us = <2>; /* ~100 kHz */
593 #address-cells = <1>;
594 #size-cells = <0>;
595 status = "disabled";
596 };
597
598 i2c@1 {
599 compatible = "i2c-gpio";
600 gpios = <&pioC 0 0 /* sda */
601 &pioC 1 0 /* scl */
602 >;
603 i2c-gpio,sda-open-drain;
604 i2c-gpio,scl-open-drain;
605 i2c-gpio,delay-us = <2>; /* ~100 kHz */
606 #address-cells = <1>;
607 #size-cells = <0>;
608 status = "disabled";
609 };
610
611 i2c@2 {
612 compatible = "i2c-gpio";
613 gpios = <&pioB 4 0 /* sda */
614 &pioB 5 0 /* scl */
615 >;
616 i2c-gpio,sda-open-drain;
617 i2c-gpio,scl-open-drain;
618 i2c-gpio,delay-us = <2>; /* ~100 kHz */
619 #address-cells = <1>;
620 #size-cells = <0>;
621 status = "disabled";
622 };
623 };
kernel source for telekom puls (alcatel/mediatek)