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Merge tag 'sunxi-dt-for-3.10-4' of git://github.com/mripard/linux into next/dt
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / boot / dts / at91sam9x5.dtsi
1 /*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12 /include/ "skeleton.dtsi"
13
14 / {
15 model = "Atmel AT91SAM9x5 family SoC";
16 compatible = "atmel,at91sam9x5";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 tcb0 = &tcb0;
29 tcb1 = &tcb1;
30 i2c0 = &i2c0;
31 i2c1 = &i2c1;
32 i2c2 = &i2c2;
33 ssc0 = &ssc0;
34 };
35 cpus {
36 cpu@0 {
37 compatible = "arm,arm926ejs";
38 };
39 };
40
41 memory {
42 reg = <0x20000000 0x10000000>;
43 };
44
45 ahb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
51 apb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 aic: interrupt-controller@fffff000 {
58 #interrupt-cells = <3>;
59 compatible = "atmel,at91rm9200-aic";
60 interrupt-controller;
61 reg = <0xfffff000 0x200>;
62 atmel,external-irqs = <31>;
63 };
64
65 ramc0: ramc@ffffe800 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe800 0x200>;
68 };
69
70 pmc: pmc@fffffc00 {
71 compatible = "atmel,at91rm9200-pmc";
72 reg = <0xfffffc00 0x100>;
73 };
74
75 rstc@fffffe00 {
76 compatible = "atmel,at91sam9g45-rstc";
77 reg = <0xfffffe00 0x10>;
78 };
79
80 shdwc@fffffe10 {
81 compatible = "atmel,at91sam9x5-shdwc";
82 reg = <0xfffffe10 0x10>;
83 };
84
85 pit: timer@fffffe30 {
86 compatible = "atmel,at91sam9260-pit";
87 reg = <0xfffffe30 0xf>;
88 interrupts = <1 4 7>;
89 };
90
91 tcb0: timer@f8008000 {
92 compatible = "atmel,at91sam9x5-tcb";
93 reg = <0xf8008000 0x100>;
94 interrupts = <17 4 0>;
95 };
96
97 tcb1: timer@f800c000 {
98 compatible = "atmel,at91sam9x5-tcb";
99 reg = <0xf800c000 0x100>;
100 interrupts = <17 4 0>;
101 };
102
103 dma0: dma-controller@ffffec00 {
104 compatible = "atmel,at91sam9g45-dma";
105 reg = <0xffffec00 0x200>;
106 interrupts = <20 4 0>;
107 };
108
109 dma1: dma-controller@ffffee00 {
110 compatible = "atmel,at91sam9g45-dma";
111 reg = <0xffffee00 0x200>;
112 interrupts = <21 4 0>;
113 };
114
115 pinctrl@fffff400 {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
119 ranges = <0xfffff400 0xfffff400 0x800>;
120
121 /* shared pinctrl settings */
122 dbgu {
123 pinctrl_dbgu: dbgu-0 {
124 atmel,pins =
125 <0 9 0x1 0x0 /* PA9 periph A */
126 0 10 0x1 0x1>; /* PA10 periph A with pullup */
127 };
128 };
129
130 usart0 {
131 pinctrl_usart0: usart0-0 {
132 atmel,pins =
133 <0 0 0x1 0x1 /* PA0 periph A with pullup */
134 0 1 0x1 0x0>; /* PA1 periph A */
135 };
136
137 pinctrl_usart0_rts: usart0_rts-0 {
138 atmel,pins =
139 <0 2 0x1 0x0>; /* PA2 periph A */
140 };
141
142 pinctrl_usart0_cts: usart0_cts-0 {
143 atmel,pins =
144 <0 3 0x1 0x0>; /* PA3 periph A */
145 };
146
147 pinctrl_usart0_sck: usart0_sck-0 {
148 atmel,pins =
149 <0 4 0x1 0x0>; /* PA4 periph A */
150 };
151 };
152
153 usart1 {
154 pinctrl_usart1: usart1-0 {
155 atmel,pins =
156 <0 5 0x1 0x1 /* PA5 periph A with pullup */
157 0 6 0x1 0x0>; /* PA6 periph A */
158 };
159
160 pinctrl_usart1_rts: usart1_rts-0 {
161 atmel,pins =
162 <2 27 0x3 0x0>; /* PC27 periph C */
163 };
164
165 pinctrl_usart1_cts: usart1_cts-0 {
166 atmel,pins =
167 <2 28 0x3 0x0>; /* PC28 periph C */
168 };
169
170 pinctrl_usart1_sck: usart1_sck-0 {
171 atmel,pins =
172 <2 28 0x3 0x0>; /* PC29 periph C */
173 };
174 };
175
176 usart2 {
177 pinctrl_usart2: usart2-0 {
178 atmel,pins =
179 <0 7 0x1 0x1 /* PA7 periph A with pullup */
180 0 8 0x1 0x0>; /* PA8 periph A */
181 };
182
183 pinctrl_uart2_rts: uart2_rts-0 {
184 atmel,pins =
185 <1 0 0x2 0x0>; /* PB0 periph B */
186 };
187
188 pinctrl_uart2_cts: uart2_cts-0 {
189 atmel,pins =
190 <1 1 0x2 0x0>; /* PB1 periph B */
191 };
192
193 pinctrl_usart2_sck: usart2_sck-0 {
194 atmel,pins =
195 <1 2 0x2 0x0>; /* PB2 periph B */
196 };
197 };
198
199 usart3 {
200 pinctrl_usart3: usart3-0 {
201 atmel,pins =
202 <2 22 0x2 0x1 /* PC22 periph B with pullup */
203 2 23 0x2 0x0>; /* PC23 periph B */
204 };
205
206 pinctrl_usart3_rts: usart3_rts-0 {
207 atmel,pins =
208 <2 24 0x2 0x0>; /* PC24 periph B */
209 };
210
211 pinctrl_usart3_cts: usart3_cts-0 {
212 atmel,pins =
213 <2 25 0x2 0x0>; /* PC25 periph B */
214 };
215
216 pinctrl_usart3_sck: usart3_sck-0 {
217 atmel,pins =
218 <2 26 0x2 0x0>; /* PC26 periph B */
219 };
220 };
221
222 uart0 {
223 pinctrl_uart0: uart0-0 {
224 atmel,pins =
225 <2 8 0x3 0x0 /* PC8 periph C */
226 2 9 0x3 0x1>; /* PC9 periph C with pullup */
227 };
228 };
229
230 uart1 {
231 pinctrl_uart1: uart1-0 {
232 atmel,pins =
233 <2 16 0x3 0x0 /* PC16 periph C */
234 2 17 0x3 0x1>; /* PC17 periph C with pullup */
235 };
236 };
237
238 nand {
239 pinctrl_nand: nand-0 {
240 atmel,pins =
241 <3 0 0x1 0x0 /* PD0 periph A Read Enable */
242 3 1 0x1 0x0 /* PD1 periph A Write Enable */
243 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */
244 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */
245 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */
246 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */
247 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */
248 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */
249 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */
250 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */
251 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */
252 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */
253 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */
254 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
255 };
256
257 pinctrl_nand_16bits: nand_16bits-0 {
258 atmel,pins =
259 <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */
260 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */
261 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */
262 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */
263 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */
264 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */
265 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */
266 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
267 };
268 };
269
270 macb0 {
271 pinctrl_macb0_rmii: macb0_rmii-0 {
272 atmel,pins =
273 <1 0 0x1 0x0 /* PB0 periph A */
274 1 1 0x1 0x0 /* PB1 periph A */
275 1 2 0x1 0x0 /* PB2 periph A */
276 1 3 0x1 0x0 /* PB3 periph A */
277 1 4 0x1 0x0 /* PB4 periph A */
278 1 5 0x1 0x0 /* PB5 periph A */
279 1 6 0x1 0x0 /* PB6 periph A */
280 1 7 0x1 0x0 /* PB7 periph A */
281 1 9 0x1 0x0 /* PB9 periph A */
282 1 10 0x1 0x0>; /* PB10 periph A */
283 };
284
285 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
286 atmel,pins =
287 <1 8 0x1 0x0 /* PB8 periph A */
288 1 11 0x1 0x0 /* PB11 periph A */
289 1 12 0x1 0x0 /* PB12 periph A */
290 1 13 0x1 0x0 /* PB13 periph A */
291 1 14 0x1 0x0 /* PB14 periph A */
292 1 15 0x1 0x0 /* PB15 periph A */
293 1 16 0x1 0x0 /* PB16 periph A */
294 1 17 0x1 0x0>; /* PB17 periph A */
295 };
296 };
297
298 mmc0 {
299 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
300 atmel,pins =
301 <0 17 0x1 0x0 /* PA17 periph A */
302 0 16 0x1 0x1 /* PA16 periph A with pullup */
303 0 15 0x1 0x1>; /* PA15 periph A with pullup */
304 };
305
306 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
307 atmel,pins =
308 <0 18 0x1 0x1 /* PA18 periph A with pullup */
309 0 19 0x1 0x1 /* PA19 periph A with pullup */
310 0 20 0x1 0x1>; /* PA20 periph A with pullup */
311 };
312 };
313
314 mmc1 {
315 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
316 atmel,pins =
317 <0 13 0x2 0x0 /* PA13 periph B */
318 0 12 0x2 0x1 /* PA12 periph B with pullup */
319 0 11 0x2 0x1>; /* PA11 periph B with pullup */
320 };
321
322 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
323 atmel,pins =
324 <0 2 0x2 0x1 /* PA2 periph B with pullup */
325 0 3 0x2 0x1 /* PA3 periph B with pullup */
326 0 4 0x2 0x1>; /* PA4 periph B with pullup */
327 };
328 };
329
330 ssc0 {
331 pinctrl_ssc0_tx: ssc0_tx-0 {
332 atmel,pins =
333 <0 24 0x2 0x0 /* PA24 periph B */
334 0 25 0x2 0x0 /* PA25 periph B */
335 0 26 0x2 0x0>; /* PA26 periph B */
336 };
337
338 pinctrl_ssc0_rx: ssc0_rx-0 {
339 atmel,pins =
340 <0 27 0x2 0x0 /* PA27 periph B */
341 0 28 0x2 0x0 /* PA28 periph B */
342 0 29 0x2 0x0>; /* PA29 periph B */
343 };
344 };
345
346 i2c0 {
347 pinctrl_i2c0: i2c0-0 {
348 atmel,pins =
349 <0 30 0x1 0x0 /* PA30 periph A I2C0 data */
350 0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */
351 };
352 };
353
354 i2c1 {
355 pinctrl_i2c1: i2c1-0 {
356 atmel,pins =
357 <2 0 0x3 0x0 /* PC0 periph C I2C1 data */
358 2 1 0x3 0x0>; /* PC1 periph C I2C1 clock */
359 };
360 };
361
362 i2c2 {
363 pinctrl_i2c2: i2c2-0 {
364 atmel,pins =
365 <1 4 0x2 0x0 /* PB4 periph B I2C2 data */
366 1 5 0x2 0x0>; /* PB5 periph B I2C2 clock */
367 };
368 };
369
370 i2c_gpio0 {
371 pinctrl_i2c_gpio0: i2c_gpio0-0 {
372 atmel,pins =
373 <0 30 0x0 0x2 /* PA30 gpio multidrive I2C0 data */
374 0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */
375 };
376 };
377
378 i2c_gpio1 {
379 pinctrl_i2c_gpio1: i2c_gpio1-0 {
380 atmel,pins =
381 <2 0 0x0 0x2 /* PC0 gpio multidrive I2C1 data */
382 2 1 0x0 0x2>; /* PC1 gpio multidrive I2C1 clock */
383 };
384 };
385
386 i2c_gpio2 {
387 pinctrl_i2c_gpio2: i2c_gpio2-0 {
388 atmel,pins =
389 <1 4 0x0 0x2 /* PB4 gpio multidrive I2C2 data */
390 1 5 0x0 0x2>; /* PB5 gpio multidrive I2C2 clock */
391 };
392 };
393
394 pioA: gpio@fffff400 {
395 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
396 reg = <0xfffff400 0x200>;
397 interrupts = <2 4 1>;
398 #gpio-cells = <2>;
399 gpio-controller;
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 };
403
404 pioB: gpio@fffff600 {
405 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
406 reg = <0xfffff600 0x200>;
407 interrupts = <2 4 1>;
408 #gpio-cells = <2>;
409 gpio-controller;
410 #gpio-lines = <19>;
411 interrupt-controller;
412 #interrupt-cells = <2>;
413 };
414
415 pioC: gpio@fffff800 {
416 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
417 reg = <0xfffff800 0x200>;
418 interrupts = <3 4 1>;
419 #gpio-cells = <2>;
420 gpio-controller;
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 };
424
425 pioD: gpio@fffffa00 {
426 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
427 reg = <0xfffffa00 0x200>;
428 interrupts = <3 4 1>;
429 #gpio-cells = <2>;
430 gpio-controller;
431 #gpio-lines = <22>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
435 };
436
437 ssc0: ssc@f0010000 {
438 compatible = "atmel,at91sam9g45-ssc";
439 reg = <0xf0010000 0x4000>;
440 interrupts = <28 4 5>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
443 status = "disabled";
444 };
445
446 mmc0: mmc@f0008000 {
447 compatible = "atmel,hsmci";
448 reg = <0xf0008000 0x600>;
449 interrupts = <12 4 0>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 status = "disabled";
453 };
454
455 mmc1: mmc@f000c000 {
456 compatible = "atmel,hsmci";
457 reg = <0xf000c000 0x600>;
458 interrupts = <26 4 0>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 status = "disabled";
462 };
463
464 dbgu: serial@fffff200 {
465 compatible = "atmel,at91sam9260-usart";
466 reg = <0xfffff200 0x200>;
467 interrupts = <1 4 7>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pinctrl_dbgu>;
470 status = "disabled";
471 };
472
473 usart0: serial@f801c000 {
474 compatible = "atmel,at91sam9260-usart";
475 reg = <0xf801c000 0x200>;
476 interrupts = <5 4 5>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_usart0>;
479 status = "disabled";
480 };
481
482 usart1: serial@f8020000 {
483 compatible = "atmel,at91sam9260-usart";
484 reg = <0xf8020000 0x200>;
485 interrupts = <6 4 5>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_usart1>;
488 status = "disabled";
489 };
490
491 usart2: serial@f8024000 {
492 compatible = "atmel,at91sam9260-usart";
493 reg = <0xf8024000 0x200>;
494 interrupts = <7 4 5>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_usart2>;
497 status = "disabled";
498 };
499
500 macb0: ethernet@f802c000 {
501 compatible = "cdns,at32ap7000-macb", "cdns,macb";
502 reg = <0xf802c000 0x100>;
503 interrupts = <24 4 3>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_macb0_rmii>;
506 status = "disabled";
507 };
508
509 macb1: ethernet@f8030000 {
510 compatible = "cdns,at32ap7000-macb", "cdns,macb";
511 reg = <0xf8030000 0x100>;
512 interrupts = <27 4 3>;
513 status = "disabled";
514 };
515
516 i2c0: i2c@f8010000 {
517 compatible = "atmel,at91sam9x5-i2c";
518 reg = <0xf8010000 0x100>;
519 interrupts = <9 4 6>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_i2c0>;
524 status = "disabled";
525 };
526
527 i2c1: i2c@f8014000 {
528 compatible = "atmel,at91sam9x5-i2c";
529 reg = <0xf8014000 0x100>;
530 interrupts = <10 4 6>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_i2c1>;
535 status = "disabled";
536 };
537
538 i2c2: i2c@f8018000 {
539 compatible = "atmel,at91sam9x5-i2c";
540 reg = <0xf8018000 0x100>;
541 interrupts = <11 4 6>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&pinctrl_i2c2>;
546 status = "disabled";
547 };
548
549 adc0: adc@f804c000 {
550 compatible = "atmel,at91sam9260-adc";
551 reg = <0xf804c000 0x100>;
552 interrupts = <19 4 0>;
553 atmel,adc-use-external;
554 atmel,adc-channels-used = <0xffff>;
555 atmel,adc-vref = <3300>;
556 atmel,adc-num-channels = <12>;
557 atmel,adc-startup-time = <40>;
558 atmel,adc-channel-base = <0x50>;
559 atmel,adc-drdy-mask = <0x1000000>;
560 atmel,adc-status-register = <0x30>;
561 atmel,adc-trigger-register = <0xc0>;
562 atmel,adc-res = <8 10>;
563 atmel,adc-res-names = "lowres", "highres";
564 atmel,adc-use-res = "highres";
565
566 trigger@0 {
567 trigger-name = "external-rising";
568 trigger-value = <0x1>;
569 trigger-external;
570 };
571
572 trigger@1 {
573 trigger-name = "external-falling";
574 trigger-value = <0x2>;
575 trigger-external;
576 };
577
578 trigger@2 {
579 trigger-name = "external-any";
580 trigger-value = <0x3>;
581 trigger-external;
582 };
583
584 trigger@3 {
585 trigger-name = "continuous";
586 trigger-value = <0x6>;
587 };
588 };
589
590 rtc@fffffeb0 {
591 compatible = "atmel,at91rm9200-rtc";
592 reg = <0xfffffeb0 0x40>;
593 interrupts = <1 4 7>;
594 status = "disabled";
595 };
596 };
597
598 nand0: nand@40000000 {
599 compatible = "atmel,at91rm9200-nand";
600 #address-cells = <1>;
601 #size-cells = <1>;
602 reg = <0x40000000 0x10000000
603 0xffffe000 0x600 /* PMECC Registers */
604 0xffffe600 0x200 /* PMECC Error Location Registers */
605 0x00108000 0x18000 /* PMECC looup table in ROM code */
606 >;
607 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
608 atmel,nand-addr-offset = <21>;
609 atmel,nand-cmd-offset = <22>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&pinctrl_nand>;
612 gpios = <&pioD 5 0
613 &pioD 4 0
614 0
615 >;
616 status = "disabled";
617 };
618
619 usb0: ohci@00600000 {
620 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
621 reg = <0x00600000 0x100000>;
622 interrupts = <22 4 2>;
623 status = "disabled";
624 };
625
626 usb1: ehci@00700000 {
627 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
628 reg = <0x00700000 0x100000>;
629 interrupts = <22 4 2>;
630 status = "disabled";
631 };
632 };
633
634 i2c@0 {
635 compatible = "i2c-gpio";
636 gpios = <&pioA 30 0 /* sda */
637 &pioA 31 0 /* scl */
638 >;
639 i2c-gpio,sda-open-drain;
640 i2c-gpio,scl-open-drain;
641 i2c-gpio,delay-us = <2>; /* ~100 kHz */
642 #address-cells = <1>;
643 #size-cells = <0>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_i2c_gpio0>;
646 status = "disabled";
647 };
648
649 i2c@1 {
650 compatible = "i2c-gpio";
651 gpios = <&pioC 0 0 /* sda */
652 &pioC 1 0 /* scl */
653 >;
654 i2c-gpio,sda-open-drain;
655 i2c-gpio,scl-open-drain;
656 i2c-gpio,delay-us = <2>; /* ~100 kHz */
657 #address-cells = <1>;
658 #size-cells = <0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&pinctrl_i2c_gpio1>;
661 status = "disabled";
662 };
663
664 i2c@2 {
665 compatible = "i2c-gpio";
666 gpios = <&pioB 4 0 /* sda */
667 &pioB 5 0 /* scl */
668 >;
669 i2c-gpio,sda-open-drain;
670 i2c-gpio,scl-open-drain;
671 i2c-gpio,delay-us = <2>; /* ~100 kHz */
672 #address-cells = <1>;
673 #size-cells = <0>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_i2c_gpio2>;
676 status = "disabled";
677 };
678 };
kernel source for telekom puls (alcatel/mediatek)