arch/arm/boot/dts/armada-370.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 370 family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * Contains definitions specific to the Armada 370 SoC that are not
  15  * common to all Armada SoCs.
  16  */
  17
  18 /include/ "armada-370-xp.dtsi"
  19
  20 / {
  21         model = "Marvell Armada 370 family SoC";
  22         compatible = "marvell,armada370", "marvell,armada-370-xp";
  23         L2: l2-cache {
  24                 compatible = "marvell,aurora-outer-cache";
  25                 reg = <0xd0008000 0x1000>;
  26                 cache-id-part = <0x100>;
  27                 wt-override;
  28         };
  29
  30         aliases {
  31                 gpio0 = &gpio0;
  32                 gpio1 = &gpio1;
  33                 gpio2 = &gpio2;
  34         };
  35
  36         mpic: interrupt-controller@d0020000 {
  37               reg = <0xd0020a00 0x1d0>,
  38                     <0xd0021870 0x58>;
  39         };
  40
  41         soc {
  42                 system-controller@d0018200 {
  43                                 compatible = "marvell,armada-370-xp-system-controller";
  44                                 reg = <0xd0018200 0x100>;
  45                 };
  46
  47                 pinctrl {
  48                         compatible = "marvell,mv88f6710-pinctrl";
  49                         reg = <0xd0018000 0x38>;
  50
  51                         sdio_pins1: sdio-pins1 {
  52                               marvell,pins = "mpp9",  "mpp11", "mpp12",
  53                                              "mpp13", "mpp14", "mpp15";
  54                               marvell,function = "sd0";
  55                         };
  56
  57                         sdio_pins2: sdio-pins2 {
  58                               marvell,pins = "mpp47", "mpp48", "mpp49",
  59                                              "mpp50", "mpp51", "mpp52";
  60                               marvell,function = "sd0";
  61                         };
  62
  63                         sdio_pins3: sdio-pins3 {
  64                               marvell,pins = "mpp48", "mpp49", "mpp50",
  65                                              "mpp51", "mpp52", "mpp53";
  66                               marvell,function = "sd0";
  67                         };
  68                 };
  69
  70                 gpio0: gpio@d0018100 {
  71                         compatible = "marvell,orion-gpio";
  72                         reg = <0xd0018100 0x40>;
  73                         ngpios = <32>;
  74                         gpio-controller;
  75                         #gpio-cells = <2>;
  76                         interrupt-controller;
  77                         #interrupts-cells = <2>;
  78                         interrupts = <82>, <83>, <84>, <85>;
  79                 };
  80
  81                 gpio1: gpio@d0018140 {
  82                         compatible = "marvell,orion-gpio";
  83                         reg = <0xd0018140 0x40>;
  84                         ngpios = <32>;
  85                         gpio-controller;
  86                         #gpio-cells = <2>;
  87                         interrupt-controller;
  88                         #interrupts-cells = <2>;
  89                         interrupts = <87>, <88>, <89>, <90>;
  90                 };
  91
  92                 gpio2: gpio@d0018180 {
  93                         compatible = "marvell,orion-gpio";
  94                         reg = <0xd0018180 0x40>;
  95                         ngpios = <2>;
  96                         gpio-controller;
  97                         #gpio-cells = <2>;
  98                         interrupt-controller;
  99                         #interrupts-cells = <2>;
 100                         interrupts = <91>;
 101                 };
 102
 103                 coreclk: mvebu-sar@d0018230 {
 104                         compatible = "marvell,armada-370-core-clock";
 105                         reg = <0xd0018230 0x08>;
 106                         #clock-cells = <1>;
 107                 };
 108
 109                 gateclk: clock-gating-control@d0018220 {
 110                         compatible = "marvell,armada-370-gating-clock";
 111                         reg = <0xd0018220 0x4>;
 112                         clocks = <&coreclk 0>;
 113                         #clock-cells = <1>;
 114                 };
 115
 116                 xor@d0060800 {
 117                         compatible = "marvell,orion-xor";
 118                         reg = <0xd0060800 0x100
 119                                0xd0060A00 0x100>;
 120                         status = "okay";
 121
 122                         xor00 {
 123                                 interrupts = <51>;
 124                                 dmacap,memcpy;
 125                                 dmacap,xor;
 126                         };
 127                         xor01 {
 128                                 interrupts = <52>;
 129                                 dmacap,memcpy;
 130                                 dmacap,xor;
 131                                 dmacap,memset;
 132                         };
 133                 };
 134
 135                 xor@d0060900 {
 136                         compatible = "marvell,orion-xor";
 137                         reg = <0xd0060900 0x100
 138                                0xd0060b00 0x100>;
 139                         status = "okay";
 140
 141                         xor10 {
 142                                 interrupts = <94>;
 143                                 dmacap,memcpy;
 144                                 dmacap,xor;
 145                         };
 146                         xor11 {
 147                                 interrupts = <95>;
 148                                 dmacap,memcpy;
 149                                 dmacap,xor;
 150                                 dmacap,memset;
 151                         };
 152                 };
 153
 154                 usb@d0050000 {
 155                         clocks = <&coreclk 0>;
 156                 };
 157
 158                 usb@d0051000 {
 159                         clocks = <&coreclk 0>;
 160                 };
 161
 162                 thermal@d0018300 {
 163                         compatible = "marvell,armada370-thermal";
 164                         reg = <0xd0018300 0x4
 165                                0xd0018304 0x4>;
 166                         status = "okay";
 167                 };
 168
 169                 pcie-controller {
 170                         compatible = "marvell,armada-370-pcie";
 171                         status = "disabled";
 172                         device_type = "pci";
 173
 174                         #address-cells = <3>;
 175                         #size-cells = <2>;
 176
 177                         bus-range = <0x00 0xff>;
 178
 179                         reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
 180
 181                         reg-names = "pcie0.0", "pcie1.0";
 182
 183                         ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
 184                                   0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
 185                                   0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 186                                   0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
 187
 188                         pcie@1,0 {
 189                                 device_type = "pci";
 190                                 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
 191                                 reg = <0x0800 0 0 0 0>;
 192                                 #address-cells = <3>;
 193                                 #size-cells = <2>;
 194                                 #interrupt-cells = <1>;
 195                                 ranges;
 196                                 interrupt-map-mask = <0 0 0 0>;
 197                                 interrupt-map = <0 0 0 0 &mpic 58>;
 198                                 marvell,pcie-port = <0>;
 199                                 marvell,pcie-lane = <0>;
 200                                 clocks = <&gateclk 5>;
 201                                 status = "disabled";
 202                         };
 203
 204                         pcie@2,0 {
 205                                 device_type = "pci";
 206                                 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
 207                                 reg = <0x1000 0 0 0 0>;
 208                                 #address-cells = <3>;
 209                                 #size-cells = <2>;
 210                                 #interrupt-cells = <1>;
 211                                 ranges;
 212                                 interrupt-map-mask = <0 0 0 0>;
 213                                 interrupt-map = <0 0 0 0 &mpic 62>;
 214                                 marvell,pcie-port = <1>;
 215                                 marvell,pcie-lane = <0>;
 216                                 clocks = <&gateclk 9>;
 217                                 status = "disabled";
 218                         };
 219                 };
 220         };
 221 };