arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAVE_CUSTOM_GPIO_H
   5         select HAVE_AOUT
   6         select HAVE_DMA_API_DEBUG
   7         select HAVE_IDE if PCI || ISA || PCMCIA
   8         select HAVE_DMA_ATTRS
   9         select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
  10         select HAVE_MEMBLOCK
  11         select RTC_LIB
  12         select SYS_SUPPORTS_APM_EMULATION
  13         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  15         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  16         select HAVE_ARCH_KGDB
  17         select HAVE_ARCH_TRACEHOOK
  18         select HAVE_KPROBES if !XIP_KERNEL
  19         select HAVE_KRETPROBES if (HAVE_KPROBES)
  20         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  21         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  22         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  23         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  24         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  25         select HAVE_GENERIC_DMA_COHERENT
  26         select HAVE_KERNEL_GZIP
  27         select HAVE_KERNEL_LZO
  28         select HAVE_KERNEL_LZMA
  29         select HAVE_KERNEL_XZ
  30         select HAVE_IRQ_WORK
  31         select HAVE_PERF_EVENTS
  32         select PERF_USE_VMALLOC
  33         select HAVE_REGS_AND_STACK_ACCESS_API
  34         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  35         select HAVE_C_RECORDMCOUNT
  36         select HAVE_GENERIC_HARDIRQS
  37         select HARDIRQS_SW_RESEND
  38         select GENERIC_IRQ_PROBE
  39         select GENERIC_IRQ_SHOW
  40         select GENERIC_IRQ_PROBE
  41         select HARDIRQS_SW_RESEND
  42         select CPU_PM if (SUSPEND || CPU_IDLE)
  43         select GENERIC_PCI_IOMAP
  44         select HAVE_BPF_JIT
  45         select GENERIC_SMP_IDLE_THREAD
  46         select KTIME_SCALAR
  47         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  48         help
  49           The ARM series is a line of low-power-consumption RISC chip designs
  50           licensed by ARM Ltd and targeted at embedded applications and
  51           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  52           manufactured, but legacy ARM-based PC hardware remains popular in
  53           Europe.  There is an ARM Linux project with a web page at
  54           <http://www.arm.linux.org.uk/>.
  55
  56 config ARM_HAS_SG_CHAIN
  57         bool
  58
  59 config NEED_SG_DMA_LENGTH
  60         bool
  61
  62 config ARM_DMA_USE_IOMMU
  63         select NEED_SG_DMA_LENGTH
  64         select ARM_HAS_SG_CHAIN
  65         bool
  66
  67 config HAVE_PWM
  68         bool
  69
  70 config MIGHT_HAVE_PCI
  71         bool
  72
  73 config SYS_SUPPORTS_APM_EMULATION
  74         bool
  75
  76 config GENERIC_GPIO
  77         bool
  78
  79 config HAVE_TCM
  80         bool
  81         select GENERIC_ALLOCATOR
  82
  83 config HAVE_PROC_CPU
  84         bool
  85
  86 config NO_IOPORT
  87         bool
  88
  89 config EISA
  90         bool
  91         ---help---
  92           The Extended Industry Standard Architecture (EISA) bus was
  93           developed as an open alternative to the IBM MicroChannel bus.
  94
  95           The EISA bus provided some of the features of the IBM MicroChannel
  96           bus while maintaining backward compatibility with cards made for
  97           the older ISA bus.  The EISA bus saw limited use between 1988 and
  98           1995 when it was made obsolete by the PCI bus.
  99
 100           Say Y here if you are building a kernel for an EISA-based machine.
 101
 102           Otherwise, say N.
 103
 104 config SBUS
 105         bool
 106
 107 config STACKTRACE_SUPPORT
 108         bool
 109         default y
 110
 111 config HAVE_LATENCYTOP_SUPPORT
 112         bool
 113         depends on !SMP
 114         default y
 115
 116 config LOCKDEP_SUPPORT
 117         bool
 118         default y
 119
 120 config TRACE_IRQFLAGS_SUPPORT
 121         bool
 122         default y
 123
 124 config GENERIC_LOCKBREAK
 125         bool
 126         default y
 127         depends on SMP && PREEMPT
 128
 129 config RWSEM_GENERIC_SPINLOCK
 130         bool
 131         default y
 132
 133 config RWSEM_XCHGADD_ALGORITHM
 134         bool
 135
 136 config ARCH_HAS_ILOG2_U32
 137         bool
 138
 139 config ARCH_HAS_ILOG2_U64
 140         bool
 141
 142 config ARCH_HAS_CPUFREQ
 143         bool
 144         help
 145           Internal node to signify that the ARCH has CPUFREQ support
 146           and that the relevant menu configurations are displayed for
 147           it.
 148
 149 config GENERIC_HWEIGHT
 150         bool
 151         default y
 152
 153 config GENERIC_CALIBRATE_DELAY
 154         bool
 155         default y
 156
 157 config ARCH_MAY_HAVE_PC_FDC
 158         bool
 159
 160 config ZONE_DMA
 161         bool
 162
 163 config NEED_DMA_MAP_STATE
 164        def_bool y
 165
 166 config ARCH_HAS_DMA_SET_COHERENT_MASK
 167         bool
 168
 169 config GENERIC_ISA_DMA
 170         bool
 171
 172 config FIQ
 173         bool
 174
 175 config NEED_RET_TO_USER
 176         bool
 177
 178 config ARCH_MTD_XIP
 179         bool
 180
 181 config VECTORS_BASE
 182         hex
 183         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 184         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 185         default 0x00000000
 186         help
 187           The base address of exception vectors.
 188
 189 config ARM_PATCH_PHYS_VIRT
 190         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 191         default y
 192         depends on !XIP_KERNEL && MMU
 193         depends on !ARCH_REALVIEW || !SPARSEMEM
 194         help
 195           Patch phys-to-virt and virt-to-phys translation functions at
 196           boot and module load time according to the position of the
 197           kernel in system memory.
 198
 199           This can only be used with non-XIP MMU kernels where the base
 200           of physical memory is at a 16MB boundary.
 201
 202           Only disable this option if you know that you do not require
 203           this feature (eg, building a kernel for a single machine) and
 204           you need to shrink the kernel to the minimal size.
 205
 206 config NEED_MACH_IO_H
 207         bool
 208         help
 209           Select this when mach/io.h is required to provide special
 210           definitions for this platform.  The need for mach/io.h should
 211           be avoided when possible.
 212
 213 config NEED_MACH_MEMORY_H
 214         bool
 215         help
 216           Select this when mach/memory.h is required to provide special
 217           definitions for this platform.  The need for mach/memory.h should
 218           be avoided when possible.
 219
 220 config PHYS_OFFSET
 221         hex "Physical address of main memory" if MMU
 222         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 223         default DRAM_BASE if !MMU
 224         help
 225           Please provide the physical address corresponding to the
 226           location of main memory in your system.
 227
 228 config GENERIC_BUG
 229         def_bool y
 230         depends on BUG
 231
 232 source "init/Kconfig"
 233
 234 source "kernel/Kconfig.freezer"
 235
 236 menu "System Type"
 237
 238 config MMU
 239         bool "MMU-based Paged Memory Management Support"
 240         default y
 241         help
 242           Select if you want MMU-based virtualised addressing space
 243           support by paged memory management. If unsure, say 'Y'.
 244
 245 #
 246 # The "ARM system type" choice list is ordered alphabetically by option
 247 # text.  Please add new entries in the option alphabetic order.
 248 #
 249 choice
 250         prompt "ARM system type"
 251         default ARCH_VERSATILE
 252
 253 config ARCH_INTEGRATOR
 254         bool "ARM Ltd. Integrator family"
 255         select ARM_AMBA
 256         select ARCH_HAS_CPUFREQ
 257         select CLKDEV_LOOKUP
 258         select HAVE_MACH_CLKDEV
 259         select HAVE_TCM
 260         select ICST
 261         select GENERIC_CLOCKEVENTS
 262         select PLAT_VERSATILE
 263         select PLAT_VERSATILE_FPGA_IRQ
 264         select NEED_MACH_IO_H
 265         select NEED_MACH_MEMORY_H
 266         select SPARSE_IRQ
 267         select MULTI_IRQ_HANDLER
 268         help
 269           Support for ARM's Integrator platform.
 270
 271 config ARCH_REALVIEW
 272         bool "ARM Ltd. RealView family"
 273         select ARM_AMBA
 274         select CLKDEV_LOOKUP
 275         select HAVE_MACH_CLKDEV
 276         select ICST
 277         select GENERIC_CLOCKEVENTS
 278         select ARCH_WANT_OPTIONAL_GPIOLIB
 279         select PLAT_VERSATILE
 280         select PLAT_VERSATILE_CLCD
 281         select ARM_TIMER_SP804
 282         select GPIO_PL061 if GPIOLIB
 283         select NEED_MACH_MEMORY_H
 284         help
 285           This enables support for ARM Ltd RealView boards.
 286
 287 config ARCH_VERSATILE
 288         bool "ARM Ltd. Versatile family"
 289         select ARM_AMBA
 290         select ARM_VIC
 291         select CLKDEV_LOOKUP
 292         select HAVE_MACH_CLKDEV
 293         select ICST
 294         select GENERIC_CLOCKEVENTS
 295         select ARCH_WANT_OPTIONAL_GPIOLIB
 296         select PLAT_VERSATILE
 297         select PLAT_VERSATILE_CLCD
 298         select PLAT_VERSATILE_FPGA_IRQ
 299         select ARM_TIMER_SP804
 300         help
 301           This enables support for ARM Ltd Versatile board.
 302
 303 config ARCH_VEXPRESS
 304         bool "ARM Ltd. Versatile Express family"
 305         select ARCH_WANT_OPTIONAL_GPIOLIB
 306         select ARM_AMBA
 307         select ARM_TIMER_SP804
 308         select CLKDEV_LOOKUP
 309         select HAVE_MACH_CLKDEV
 310         select GENERIC_CLOCKEVENTS
 311         select HAVE_CLK
 312         select HAVE_PATA_PLATFORM
 313         select ICST
 314         select NO_IOPORT
 315         select PLAT_VERSATILE
 316         select PLAT_VERSATILE_CLCD
 317         help
 318           This enables support for the ARM Ltd Versatile Express boards.
 319
 320 config ARCH_AT91
 321         bool "Atmel AT91"
 322         select ARCH_REQUIRE_GPIOLIB
 323         select HAVE_CLK
 324         select CLKDEV_LOOKUP
 325         select IRQ_DOMAIN
 326         select NEED_MACH_IO_H if PCCARD
 327         help
 328           This enables support for systems based on Atmel
 329           AT91RM9200 and AT91SAM9* processors.
 330
 331 config ARCH_BCMRING
 332         bool "Broadcom BCMRING"
 333         depends on MMU
 334         select CPU_V6
 335         select ARM_AMBA
 336         select ARM_TIMER_SP804
 337         select CLKDEV_LOOKUP
 338         select GENERIC_CLOCKEVENTS
 339         select ARCH_WANT_OPTIONAL_GPIOLIB
 340         help
 341           Support for Broadcom's BCMRing platform.
 342
 343 config ARCH_HIGHBANK
 344         bool "Calxeda Highbank-based"
 345         select ARCH_WANT_OPTIONAL_GPIOLIB
 346         select ARM_AMBA
 347         select ARM_GIC
 348         select ARM_TIMER_SP804
 349         select CACHE_L2X0
 350         select CLKDEV_LOOKUP
 351         select CPU_V7
 352         select GENERIC_CLOCKEVENTS
 353         select HAVE_ARM_SCU
 354         select HAVE_SMP
 355         select SPARSE_IRQ
 356         select USE_OF
 357         help
 358           Support for the Calxeda Highbank SoC based boards.
 359
 360 config ARCH_CLPS711X
 361         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 362         select CPU_ARM720T
 363         select ARCH_USES_GETTIMEOFFSET
 364         select NEED_MACH_MEMORY_H
 365         help
 366           Support for Cirrus Logic 711x/721x/731x based boards.
 367
 368 config ARCH_CNS3XXX
 369         bool "Cavium Networks CNS3XXX family"
 370         select CPU_V6K
 371         select GENERIC_CLOCKEVENTS
 372         select ARM_GIC
 373         select MIGHT_HAVE_CACHE_L2X0
 374         select MIGHT_HAVE_PCI
 375         select PCI_DOMAINS if PCI
 376         help
 377           Support for Cavium Networks CNS3XXX platform.
 378
 379 config ARCH_GEMINI
 380         bool "Cortina Systems Gemini"
 381         select CPU_FA526
 382         select ARCH_REQUIRE_GPIOLIB
 383         select ARCH_USES_GETTIMEOFFSET
 384         help
 385           Support for the Cortina Systems Gemini family SoCs
 386
 387 config ARCH_PRIMA2
 388         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 389         select CPU_V7
 390         select NO_IOPORT
 391         select GENERIC_CLOCKEVENTS
 392         select CLKDEV_LOOKUP
 393         select GENERIC_IRQ_CHIP
 394         select MIGHT_HAVE_CACHE_L2X0
 395         select PINCTRL
 396         select PINCTRL_SIRF
 397         select USE_OF
 398         select ZONE_DMA
 399         help
 400           Support for CSR SiRFSoC ARM Cortex A9 Platform
 401
 402 config ARCH_EBSA110
 403         bool "EBSA-110"
 404         select CPU_SA110
 405         select ISA
 406         select NO_IOPORT
 407         select ARCH_USES_GETTIMEOFFSET
 408         select NEED_MACH_IO_H
 409         select NEED_MACH_MEMORY_H
 410         help
 411           This is an evaluation board for the StrongARM processor available
 412           from Digital. It has limited hardware on-board, including an
 413           Ethernet interface, two PCMCIA sockets, two serial ports and a
 414           parallel port.
 415
 416 config ARCH_EP93XX
 417         bool "EP93xx-based"
 418         select CPU_ARM920T
 419         select ARM_AMBA
 420         select ARM_VIC
 421         select CLKDEV_LOOKUP
 422         select ARCH_REQUIRE_GPIOLIB
 423         select ARCH_HAS_HOLES_MEMORYMODEL
 424         select ARCH_USES_GETTIMEOFFSET
 425         select NEED_MACH_MEMORY_H
 426         help
 427           This enables support for the Cirrus EP93xx series of CPUs.
 428
 429 config ARCH_FOOTBRIDGE
 430         bool "FootBridge"
 431         select CPU_SA110
 432         select FOOTBRIDGE
 433         select GENERIC_CLOCKEVENTS
 434         select HAVE_IDE
 435         select NEED_MACH_IO_H
 436         select NEED_MACH_MEMORY_H
 437         help
 438           Support for systems based on the DC21285 companion chip
 439           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 440
 441 config ARCH_MXC
 442         bool "Freescale MXC/iMX-based"
 443         select GENERIC_CLOCKEVENTS
 444         select ARCH_REQUIRE_GPIOLIB
 445         select CLKDEV_LOOKUP
 446         select CLKSRC_MMIO
 447         select GENERIC_IRQ_CHIP
 448         select MULTI_IRQ_HANDLER
 449         help
 450           Support for Freescale MXC/iMX-based family of processors
 451
 452 config ARCH_MXS
 453         bool "Freescale MXS-based"
 454         select GENERIC_CLOCKEVENTS
 455         select ARCH_REQUIRE_GPIOLIB
 456         select CLKDEV_LOOKUP
 457         select CLKSRC_MMIO
 458         select COMMON_CLK
 459         select HAVE_CLK_PREPARE
 460         select PINCTRL
 461         select USE_OF
 462         help
 463           Support for Freescale MXS-based family of processors
 464
 465 config ARCH_NETX
 466         bool "Hilscher NetX based"
 467         select CLKSRC_MMIO
 468         select CPU_ARM926T
 469         select ARM_VIC
 470         select GENERIC_CLOCKEVENTS
 471         help
 472           This enables support for systems based on the Hilscher NetX Soc
 473
 474 config ARCH_H720X
 475         bool "Hynix HMS720x-based"
 476         select CPU_ARM720T
 477         select ISA_DMA_API
 478         select ARCH_USES_GETTIMEOFFSET
 479         help
 480           This enables support for systems based on the Hynix HMS720x
 481
 482 config ARCH_IOP13XX
 483         bool "IOP13xx-based"
 484         depends on MMU
 485         select CPU_XSC3
 486         select PLAT_IOP
 487         select PCI
 488         select ARCH_SUPPORTS_MSI
 489         select VMSPLIT_1G
 490         select NEED_MACH_IO_H
 491         select NEED_MACH_MEMORY_H
 492         select NEED_RET_TO_USER
 493         help
 494           Support for Intel's IOP13XX (XScale) family of processors.
 495
 496 config ARCH_IOP32X
 497         bool "IOP32x-based"
 498         depends on MMU
 499         select CPU_XSCALE
 500         select NEED_MACH_IO_H
 501         select NEED_RET_TO_USER
 502         select PLAT_IOP
 503         select PCI
 504         select ARCH_REQUIRE_GPIOLIB
 505         help
 506           Support for Intel's 80219 and IOP32X (XScale) family of
 507           processors.
 508
 509 config ARCH_IOP33X
 510         bool "IOP33x-based"
 511         depends on MMU
 512         select CPU_XSCALE
 513         select NEED_MACH_IO_H
 514         select NEED_RET_TO_USER
 515         select PLAT_IOP
 516         select PCI
 517         select ARCH_REQUIRE_GPIOLIB
 518         help
 519           Support for Intel's IOP33X (XScale) family of processors.
 520
 521 config ARCH_IXP4XX
 522         bool "IXP4xx-based"
 523         depends on MMU
 524         select ARCH_HAS_DMA_SET_COHERENT_MASK
 525         select CLKSRC_MMIO
 526         select CPU_XSCALE
 527         select ARCH_REQUIRE_GPIOLIB
 528         select GENERIC_CLOCKEVENTS
 529         select MIGHT_HAVE_PCI
 530         select NEED_MACH_IO_H
 531         select DMABOUNCE if PCI
 532         help
 533           Support for Intel's IXP4XX (XScale) family of processors.
 534
 535 config ARCH_DOVE
 536         bool "Marvell Dove"
 537         select CPU_V7
 538         select PCI
 539         select ARCH_REQUIRE_GPIOLIB
 540         select GENERIC_CLOCKEVENTS
 541         select NEED_MACH_IO_H
 542         select PLAT_ORION
 543         help
 544           Support for the Marvell Dove SoC 88AP510
 545
 546 config ARCH_KIRKWOOD
 547         bool "Marvell Kirkwood"
 548         select CPU_FEROCEON
 549         select PCI
 550         select ARCH_REQUIRE_GPIOLIB
 551         select GENERIC_CLOCKEVENTS
 552         select NEED_MACH_IO_H
 553         select PLAT_ORION
 554         help
 555           Support for the following Marvell Kirkwood series SoCs:
 556           88F6180, 88F6192 and 88F6281.
 557
 558 config ARCH_LPC32XX
 559         bool "NXP LPC32XX"
 560         select CLKSRC_MMIO
 561         select CPU_ARM926T
 562         select ARCH_REQUIRE_GPIOLIB
 563         select HAVE_IDE
 564         select ARM_AMBA
 565         select USB_ARCH_HAS_OHCI
 566         select CLKDEV_LOOKUP
 567         select GENERIC_CLOCKEVENTS
 568         select USE_OF
 569         help
 570           Support for the NXP LPC32XX family of processors
 571
 572 config ARCH_MV78XX0
 573         bool "Marvell MV78xx0"
 574         select CPU_FEROCEON
 575         select PCI
 576         select ARCH_REQUIRE_GPIOLIB
 577         select GENERIC_CLOCKEVENTS
 578         select NEED_MACH_IO_H
 579         select PLAT_ORION
 580         help
 581           Support for the following Marvell MV78xx0 series SoCs:
 582           MV781x0, MV782x0.
 583
 584 config ARCH_ORION5X
 585         bool "Marvell Orion"
 586         depends on MMU
 587         select CPU_FEROCEON
 588         select PCI
 589         select ARCH_REQUIRE_GPIOLIB
 590         select GENERIC_CLOCKEVENTS
 591         select PLAT_ORION
 592         help
 593           Support for the following Marvell Orion 5x series SoCs:
 594           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 595           Orion-2 (5281), Orion-1-90 (6183).
 596
 597 config ARCH_MMP
 598         bool "Marvell PXA168/910/MMP2"
 599         depends on MMU
 600         select ARCH_REQUIRE_GPIOLIB
 601         select CLKDEV_LOOKUP
 602         select GENERIC_CLOCKEVENTS
 603         select GPIO_PXA
 604         select IRQ_DOMAIN
 605         select PLAT_PXA
 606         select SPARSE_IRQ
 607         select GENERIC_ALLOCATOR
 608         help
 609           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 610
 611 config ARCH_KS8695
 612         bool "Micrel/Kendin KS8695"
 613         select CPU_ARM922T
 614         select ARCH_REQUIRE_GPIOLIB
 615         select ARCH_USES_GETTIMEOFFSET
 616         select NEED_MACH_MEMORY_H
 617         help
 618           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 619           System-on-Chip devices.
 620
 621 config ARCH_W90X900
 622         bool "Nuvoton W90X900 CPU"
 623         select CPU_ARM926T
 624         select ARCH_REQUIRE_GPIOLIB
 625         select CLKDEV_LOOKUP
 626         select CLKSRC_MMIO
 627         select GENERIC_CLOCKEVENTS
 628         help
 629           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 630           At present, the w90x900 has been renamed nuc900, regarding
 631           the ARM series product line, you can login the following
 632           link address to know more.
 633
 634           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 635                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 636
 637 config ARCH_TEGRA
 638         bool "NVIDIA Tegra"
 639         select CLKDEV_LOOKUP
 640         select CLKSRC_MMIO
 641         select GENERIC_CLOCKEVENTS
 642         select GENERIC_GPIO
 643         select HAVE_CLK
 644         select HAVE_SMP
 645         select MIGHT_HAVE_CACHE_L2X0
 646         select NEED_MACH_IO_H if PCI
 647         select ARCH_HAS_CPUFREQ
 648         help
 649           This enables support for NVIDIA Tegra based systems (Tegra APX,
 650           Tegra 6xx and Tegra 2 series).
 651
 652 config ARCH_PICOXCELL
 653         bool "Picochip picoXcell"
 654         select ARCH_REQUIRE_GPIOLIB
 655         select ARM_PATCH_PHYS_VIRT
 656         select ARM_VIC
 657         select CPU_V6K
 658         select DW_APB_TIMER
 659         select GENERIC_CLOCKEVENTS
 660         select GENERIC_GPIO
 661         select HAVE_TCM
 662         select NO_IOPORT
 663         select SPARSE_IRQ
 664         select USE_OF
 665         help
 666           This enables support for systems based on the Picochip picoXcell
 667           family of Femtocell devices.  The picoxcell support requires device tree
 668           for all boards.
 669
 670 config ARCH_PNX4008
 671         bool "Philips Nexperia PNX4008 Mobile"
 672         select CPU_ARM926T
 673         select CLKDEV_LOOKUP
 674         select ARCH_USES_GETTIMEOFFSET
 675         help
 676           This enables support for Philips PNX4008 mobile platform.
 677
 678 config ARCH_PXA
 679         bool "PXA2xx/PXA3xx-based"
 680         depends on MMU
 681         select ARCH_MTD_XIP
 682         select ARCH_HAS_CPUFREQ
 683         select CLKDEV_LOOKUP
 684         select CLKSRC_MMIO
 685         select ARCH_REQUIRE_GPIOLIB
 686         select GENERIC_CLOCKEVENTS
 687         select GPIO_PXA
 688         select PLAT_PXA
 689         select SPARSE_IRQ
 690         select AUTO_ZRELADDR
 691         select MULTI_IRQ_HANDLER
 692         select ARM_CPU_SUSPEND if PM
 693         select HAVE_IDE
 694         help
 695           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 696
 697 config ARCH_MSM
 698         bool "Qualcomm MSM"
 699         select HAVE_CLK
 700         select GENERIC_CLOCKEVENTS
 701         select ARCH_REQUIRE_GPIOLIB
 702         select CLKDEV_LOOKUP
 703         help
 704           Support for Qualcomm MSM/QSD based systems.  This runs on the
 705           apps processor of the MSM/QSD and depends on a shared memory
 706           interface to the modem processor which runs the baseband
 707           stack and controls some vital subsystems
 708           (clock and power control, etc).
 709
 710 config ARCH_SHMOBILE
 711         bool "Renesas SH-Mobile / R-Mobile"
 712         select HAVE_CLK
 713         select CLKDEV_LOOKUP
 714         select HAVE_MACH_CLKDEV
 715         select HAVE_SMP
 716         select GENERIC_CLOCKEVENTS
 717         select MIGHT_HAVE_CACHE_L2X0
 718         select NO_IOPORT
 719         select SPARSE_IRQ
 720         select MULTI_IRQ_HANDLER
 721         select PM_GENERIC_DOMAINS if PM
 722         select NEED_MACH_MEMORY_H
 723         help
 724           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 725
 726 config ARCH_RPC
 727         bool "RiscPC"
 728         select ARCH_ACORN
 729         select FIQ
 730         select ARCH_MAY_HAVE_PC_FDC
 731         select HAVE_PATA_PLATFORM
 732         select ISA_DMA_API
 733         select NO_IOPORT
 734         select ARCH_SPARSEMEM_ENABLE
 735         select ARCH_USES_GETTIMEOFFSET
 736         select HAVE_IDE
 737         select NEED_MACH_IO_H
 738         select NEED_MACH_MEMORY_H
 739         help
 740           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 741           CD-ROM interface, serial and parallel port, and the floppy drive.
 742
 743 config ARCH_SA1100
 744         bool "SA1100-based"
 745         select CLKSRC_MMIO
 746         select CPU_SA1100
 747         select ISA
 748         select ARCH_SPARSEMEM_ENABLE
 749         select ARCH_MTD_XIP
 750         select ARCH_HAS_CPUFREQ
 751         select CPU_FREQ
 752         select GENERIC_CLOCKEVENTS
 753         select CLKDEV_LOOKUP
 754         select ARCH_REQUIRE_GPIOLIB
 755         select HAVE_IDE
 756         select NEED_MACH_MEMORY_H
 757         select SPARSE_IRQ
 758         help
 759           Support for StrongARM 11x0 based boards.
 760
 761 config ARCH_S3C24XX
 762         bool "Samsung S3C24XX SoCs"
 763         select GENERIC_GPIO
 764         select ARCH_HAS_CPUFREQ
 765         select HAVE_CLK
 766         select CLKDEV_LOOKUP
 767         select ARCH_USES_GETTIMEOFFSET
 768         select HAVE_S3C2410_I2C if I2C
 769         select HAVE_S3C_RTC if RTC_CLASS
 770         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 771         select NEED_MACH_IO_H
 772         help
 773           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 774           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 775           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 776           Samsung SMDK2410 development board (and derivatives).
 777
 778 config ARCH_S3C64XX
 779         bool "Samsung S3C64XX"
 780         select PLAT_SAMSUNG
 781         select CPU_V6
 782         select ARM_VIC
 783         select HAVE_CLK
 784         select HAVE_TCM
 785         select CLKDEV_LOOKUP
 786         select NO_IOPORT
 787         select ARCH_USES_GETTIMEOFFSET
 788         select ARCH_HAS_CPUFREQ
 789         select ARCH_REQUIRE_GPIOLIB
 790         select SAMSUNG_CLKSRC
 791         select SAMSUNG_IRQ_VIC_TIMER
 792         select S3C_GPIO_TRACK
 793         select S3C_DEV_NAND
 794         select USB_ARCH_HAS_OHCI
 795         select SAMSUNG_GPIOLIB_4BIT
 796         select HAVE_S3C2410_I2C if I2C
 797         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 798         help
 799           Samsung S3C64XX series based systems
 800
 801 config ARCH_S5P64X0
 802         bool "Samsung S5P6440 S5P6450"
 803         select CPU_V6
 804         select GENERIC_GPIO
 805         select HAVE_CLK
 806         select CLKDEV_LOOKUP
 807         select CLKSRC_MMIO
 808         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 809         select GENERIC_CLOCKEVENTS
 810         select HAVE_S3C2410_I2C if I2C
 811         select HAVE_S3C_RTC if RTC_CLASS
 812         help
 813           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 814           SMDK6450.
 815
 816 config ARCH_S5PC100
 817         bool "Samsung S5PC100"
 818         select GENERIC_GPIO
 819         select HAVE_CLK
 820         select CLKDEV_LOOKUP
 821         select CPU_V7
 822         select ARCH_USES_GETTIMEOFFSET
 823         select HAVE_S3C2410_I2C if I2C
 824         select HAVE_S3C_RTC if RTC_CLASS
 825         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 826         help
 827           Samsung S5PC100 series based systems
 828
 829 config ARCH_S5PV210
 830         bool "Samsung S5PV210/S5PC110"
 831         select CPU_V7
 832         select ARCH_SPARSEMEM_ENABLE
 833         select ARCH_HAS_HOLES_MEMORYMODEL
 834         select GENERIC_GPIO
 835         select HAVE_CLK
 836         select CLKDEV_LOOKUP
 837         select CLKSRC_MMIO
 838         select ARCH_HAS_CPUFREQ
 839         select GENERIC_CLOCKEVENTS
 840         select HAVE_S3C2410_I2C if I2C
 841         select HAVE_S3C_RTC if RTC_CLASS
 842         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 843         select NEED_MACH_MEMORY_H
 844         help
 845           Samsung S5PV210/S5PC110 series based systems
 846
 847 config ARCH_EXYNOS
 848         bool "SAMSUNG EXYNOS"
 849         select CPU_V7
 850         select ARCH_SPARSEMEM_ENABLE
 851         select ARCH_HAS_HOLES_MEMORYMODEL
 852         select GENERIC_GPIO
 853         select HAVE_CLK
 854         select CLKDEV_LOOKUP
 855         select ARCH_HAS_CPUFREQ
 856         select GENERIC_CLOCKEVENTS
 857         select HAVE_S3C_RTC if RTC_CLASS
 858         select HAVE_S3C2410_I2C if I2C
 859         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 860         select NEED_MACH_MEMORY_H
 861         help
 862           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 863
 864 config ARCH_SHARK
 865         bool "Shark"
 866         select CPU_SA110
 867         select ISA
 868         select ISA_DMA
 869         select ZONE_DMA
 870         select PCI
 871         select ARCH_USES_GETTIMEOFFSET
 872         select NEED_MACH_MEMORY_H
 873         select NEED_MACH_IO_H
 874         help
 875           Support for the StrongARM based Digital DNARD machine, also known
 876           as "Shark" (<http://www.shark-linux.de/shark.html>).
 877
 878 config ARCH_U300
 879         bool "ST-Ericsson U300 Series"
 880         depends on MMU
 881         select CLKSRC_MMIO
 882         select CPU_ARM926T
 883         select HAVE_TCM
 884         select ARM_AMBA
 885         select ARM_PATCH_PHYS_VIRT
 886         select ARM_VIC
 887         select GENERIC_CLOCKEVENTS
 888         select CLKDEV_LOOKUP
 889         select HAVE_MACH_CLKDEV
 890         select GENERIC_GPIO
 891         select ARCH_REQUIRE_GPIOLIB
 892         help
 893           Support for ST-Ericsson U300 series mobile platforms.
 894
 895 config ARCH_U8500
 896         bool "ST-Ericsson U8500 Series"
 897         depends on MMU
 898         select CPU_V7
 899         select ARM_AMBA
 900         select GENERIC_CLOCKEVENTS
 901         select CLKDEV_LOOKUP
 902         select ARCH_REQUIRE_GPIOLIB
 903         select ARCH_HAS_CPUFREQ
 904         select HAVE_SMP
 905         select MIGHT_HAVE_CACHE_L2X0
 906         help
 907           Support for ST-Ericsson's Ux500 architecture
 908
 909 config ARCH_NOMADIK
 910         bool "STMicroelectronics Nomadik"
 911         select ARM_AMBA
 912         select ARM_VIC
 913         select CPU_ARM926T
 914         select CLKDEV_LOOKUP
 915         select GENERIC_CLOCKEVENTS
 916         select PINCTRL
 917         select MIGHT_HAVE_CACHE_L2X0
 918         select ARCH_REQUIRE_GPIOLIB
 919         help
 920           Support for the Nomadik platform by ST-Ericsson
 921
 922 config ARCH_DAVINCI
 923         bool "TI DaVinci"
 924         select GENERIC_CLOCKEVENTS
 925         select ARCH_REQUIRE_GPIOLIB
 926         select ZONE_DMA
 927         select HAVE_IDE
 928         select CLKDEV_LOOKUP
 929         select GENERIC_ALLOCATOR
 930         select GENERIC_IRQ_CHIP
 931         select ARCH_HAS_HOLES_MEMORYMODEL
 932         help
 933           Support for TI's DaVinci platform.
 934
 935 config ARCH_OMAP
 936         bool "TI OMAP"
 937         select HAVE_CLK
 938         select ARCH_REQUIRE_GPIOLIB
 939         select ARCH_HAS_CPUFREQ
 940         select CLKSRC_MMIO
 941         select GENERIC_CLOCKEVENTS
 942         select ARCH_HAS_HOLES_MEMORYMODEL
 943         help
 944           Support for TI's OMAP platform (OMAP1/2/3/4).
 945
 946 config PLAT_SPEAR
 947         bool "ST SPEAr"
 948         select ARM_AMBA
 949         select ARCH_REQUIRE_GPIOLIB
 950         select CLKDEV_LOOKUP
 951         select COMMON_CLK
 952         select CLKSRC_MMIO
 953         select GENERIC_CLOCKEVENTS
 954         select HAVE_CLK
 955         help
 956           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 957
 958 config ARCH_VT8500
 959         bool "VIA/WonderMedia 85xx"
 960         select CPU_ARM926T
 961         select GENERIC_GPIO
 962         select ARCH_HAS_CPUFREQ
 963         select GENERIC_CLOCKEVENTS
 964         select ARCH_REQUIRE_GPIOLIB
 965         select HAVE_PWM
 966         help
 967           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 968
 969 config ARCH_ZYNQ
 970         bool "Xilinx Zynq ARM Cortex A9 Platform"
 971         select CPU_V7
 972         select GENERIC_CLOCKEVENTS
 973         select CLKDEV_LOOKUP
 974         select ARM_GIC
 975         select ARM_AMBA
 976         select ICST
 977         select MIGHT_HAVE_CACHE_L2X0
 978         select USE_OF
 979         help
 980           Support for Xilinx Zynq ARM Cortex A9 Platform
 981 endchoice
 982
 983 #
 984 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 985 # Kconfigs may be included either alphabetically (according to the
 986 # plat- suffix) or along side the corresponding mach-* source.
 987 #
 988 source "arch/arm/mach-at91/Kconfig"
 989
 990 source "arch/arm/mach-bcmring/Kconfig"
 991
 992 source "arch/arm/mach-clps711x/Kconfig"
 993
 994 source "arch/arm/mach-cns3xxx/Kconfig"
 995
 996 source "arch/arm/mach-davinci/Kconfig"
 997
 998 source "arch/arm/mach-dove/Kconfig"
 999
1000 source "arch/arm/mach-ep93xx/Kconfig"
1001
1002 source "arch/arm/mach-footbridge/Kconfig"
1003
1004 source "arch/arm/mach-gemini/Kconfig"
1005
1006 source "arch/arm/mach-h720x/Kconfig"
1007
1008 source "arch/arm/mach-integrator/Kconfig"
1009
1010 source "arch/arm/mach-iop32x/Kconfig"
1011
1012 source "arch/arm/mach-iop33x/Kconfig"
1013
1014 source "arch/arm/mach-iop13xx/Kconfig"
1015
1016 source "arch/arm/mach-ixp4xx/Kconfig"
1017
1018 source "arch/arm/mach-kirkwood/Kconfig"
1019
1020 source "arch/arm/mach-ks8695/Kconfig"
1021
1022 source "arch/arm/mach-lpc32xx/Kconfig"
1023
1024 source "arch/arm/mach-msm/Kconfig"
1025
1026 source "arch/arm/mach-mv78xx0/Kconfig"
1027
1028 source "arch/arm/plat-mxc/Kconfig"
1029
1030 source "arch/arm/mach-mxs/Kconfig"
1031
1032 source "arch/arm/mach-netx/Kconfig"
1033
1034 source "arch/arm/mach-nomadik/Kconfig"
1035 source "arch/arm/plat-nomadik/Kconfig"
1036
1037 source "arch/arm/plat-omap/Kconfig"
1038
1039 source "arch/arm/mach-omap1/Kconfig"
1040
1041 source "arch/arm/mach-omap2/Kconfig"
1042
1043 source "arch/arm/mach-orion5x/Kconfig"
1044
1045 source "arch/arm/mach-pxa/Kconfig"
1046 source "arch/arm/plat-pxa/Kconfig"
1047
1048 source "arch/arm/mach-mmp/Kconfig"
1049
1050 source "arch/arm/mach-realview/Kconfig"
1051
1052 source "arch/arm/mach-sa1100/Kconfig"
1053
1054 source "arch/arm/plat-samsung/Kconfig"
1055 source "arch/arm/plat-s3c24xx/Kconfig"
1056
1057 source "arch/arm/plat-spear/Kconfig"
1058
1059 source "arch/arm/mach-s3c24xx/Kconfig"
1060 if ARCH_S3C24XX
1061 source "arch/arm/mach-s3c2412/Kconfig"
1062 source "arch/arm/mach-s3c2440/Kconfig"
1063 endif
1064
1065 if ARCH_S3C64XX
1066 source "arch/arm/mach-s3c64xx/Kconfig"
1067 endif
1068
1069 source "arch/arm/mach-s5p64x0/Kconfig"
1070
1071 source "arch/arm/mach-s5pc100/Kconfig"
1072
1073 source "arch/arm/mach-s5pv210/Kconfig"
1074
1075 source "arch/arm/mach-exynos/Kconfig"
1076
1077 source "arch/arm/mach-shmobile/Kconfig"
1078
1079 source "arch/arm/mach-tegra/Kconfig"
1080
1081 source "arch/arm/mach-u300/Kconfig"
1082
1083 source "arch/arm/mach-ux500/Kconfig"
1084
1085 source "arch/arm/mach-versatile/Kconfig"
1086
1087 source "arch/arm/mach-vexpress/Kconfig"
1088 source "arch/arm/plat-versatile/Kconfig"
1089
1090 source "arch/arm/mach-vt8500/Kconfig"
1091
1092 source "arch/arm/mach-w90x900/Kconfig"
1093
1094 # Definitions to make life easier
1095 config ARCH_ACORN
1096         bool
1097
1098 config PLAT_IOP
1099         bool
1100         select GENERIC_CLOCKEVENTS
1101
1102 config PLAT_ORION
1103         bool
1104         select CLKSRC_MMIO
1105         select GENERIC_IRQ_CHIP
1106         select COMMON_CLK
1107
1108 config PLAT_PXA
1109         bool
1110
1111 config PLAT_VERSATILE
1112         bool
1113
1114 config ARM_TIMER_SP804
1115         bool
1116         select CLKSRC_MMIO
1117         select HAVE_SCHED_CLOCK
1118
1119 source arch/arm/mm/Kconfig
1120
1121 config ARM_NR_BANKS
1122         int
1123         default 16 if ARCH_EP93XX
1124         default 8
1125
1126 config IWMMXT
1127         bool "Enable iWMMXt support"
1128         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1129         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1130         help
1131           Enable support for iWMMXt context switching at run time if
1132           running on a CPU that supports it.
1133
1134 config XSCALE_PMU
1135         bool
1136         depends on CPU_XSCALE
1137         default y
1138
1139 config CPU_HAS_PMU
1140         depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1141                    (!ARCH_OMAP3 || OMAP3_EMU)
1142         default y
1143         bool
1144
1145 config MULTI_IRQ_HANDLER
1146         bool
1147         help
1148           Allow each machine to specify it's own IRQ handler at run time.
1149
1150 if !MMU
1151 source "arch/arm/Kconfig-nommu"
1152 endif
1153
1154 config ARM_ERRATA_326103
1155         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1156         depends on CPU_V6
1157         help
1158           Executing a SWP instruction to read-only memory does not set bit 11
1159           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1160           treat the access as a read, preventing a COW from occurring and
1161           causing the faulting task to livelock.
1162
1163 config ARM_ERRATA_411920
1164         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1165         depends on CPU_V6 || CPU_V6K
1166         help
1167           Invalidation of the Instruction Cache operation can
1168           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1169           It does not affect the MPCore. This option enables the ARM Ltd.
1170           recommended workaround.
1171
1172 config ARM_ERRATA_430973
1173         bool "ARM errata: Stale prediction on replaced interworking branch"
1174         depends on CPU_V7
1175         help
1176           This option enables the workaround for the 430973 Cortex-A8
1177           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1178           interworking branch is replaced with another code sequence at the
1179           same virtual address, whether due to self-modifying code or virtual
1180           to physical address re-mapping, Cortex-A8 does not recover from the
1181           stale interworking branch prediction. This results in Cortex-A8
1182           executing the new code sequence in the incorrect ARM or Thumb state.
1183           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1184           and also flushes the branch target cache at every context switch.
1185           Note that setting specific bits in the ACTLR register may not be
1186           available in non-secure mode.
1187
1188 config ARM_ERRATA_458693
1189         bool "ARM errata: Processor deadlock when a false hazard is created"
1190         depends on CPU_V7
1191         help
1192           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1193           erratum. For very specific sequences of memory operations, it is
1194           possible for a hazard condition intended for a cache line to instead
1195           be incorrectly associated with a different cache line. This false
1196           hazard might then cause a processor deadlock. The workaround enables
1197           the L1 caching of the NEON accesses and disables the PLD instruction
1198           in the ACTLR register. Note that setting specific bits in the ACTLR
1199           register may not be available in non-secure mode.
1200
1201 config ARM_ERRATA_460075
1202         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1203         depends on CPU_V7
1204         help
1205           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1206           erratum. Any asynchronous access to the L2 cache may encounter a
1207           situation in which recent store transactions to the L2 cache are lost
1208           and overwritten with stale memory contents from external memory. The
1209           workaround disables the write-allocate mode for the L2 cache via the
1210           ACTLR register. Note that setting specific bits in the ACTLR register
1211           may not be available in non-secure mode.
1212
1213 config ARM_ERRATA_742230
1214         bool "ARM errata: DMB operation may be faulty"
1215         depends on CPU_V7 && SMP
1216         help
1217           This option enables the workaround for the 742230 Cortex-A9
1218           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1219           between two write operations may not ensure the correct visibility
1220           ordering of the two writes. This workaround sets a specific bit in
1221           the diagnostic register of the Cortex-A9 which causes the DMB
1222           instruction to behave as a DSB, ensuring the correct behaviour of
1223           the two writes.
1224
1225 config ARM_ERRATA_742231
1226         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1227         depends on CPU_V7 && SMP
1228         help
1229           This option enables the workaround for the 742231 Cortex-A9
1230           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1231           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1232           accessing some data located in the same cache line, may get corrupted
1233           data due to bad handling of the address hazard when the line gets
1234           replaced from one of the CPUs at the same time as another CPU is
1235           accessing it. This workaround sets specific bits in the diagnostic
1236           register of the Cortex-A9 which reduces the linefill issuing
1237           capabilities of the processor.
1238
1239 config PL310_ERRATA_588369
1240         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1241         depends on CACHE_L2X0
1242         help
1243            The PL310 L2 cache controller implements three types of Clean &
1244            Invalidate maintenance operations: by Physical Address
1245            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1246            They are architecturally defined to behave as the execution of a
1247            clean operation followed immediately by an invalidate operation,
1248            both performing to the same memory location. This functionality
1249            is not correctly implemented in PL310 as clean lines are not
1250            invalidated as a result of these operations.
1251
1252 config ARM_ERRATA_720789
1253         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1254         depends on CPU_V7
1255         help
1256           This option enables the workaround for the 720789 Cortex-A9 (prior to
1257           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1258           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1259           As a consequence of this erratum, some TLB entries which should be
1260           invalidated are not, resulting in an incoherency in the system page
1261           tables. The workaround changes the TLB flushing routines to invalidate
1262           entries regardless of the ASID.
1263
1264 config PL310_ERRATA_727915
1265         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1266         depends on CACHE_L2X0
1267         help
1268           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1269           operation (offset 0x7FC). This operation runs in background so that
1270           PL310 can handle normal accesses while it is in progress. Under very
1271           rare circumstances, due to this erratum, write data can be lost when
1272           PL310 treats a cacheable write transaction during a Clean &
1273           Invalidate by Way operation.
1274
1275 config ARM_ERRATA_743622
1276         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1277         depends on CPU_V7
1278         help
1279           This option enables the workaround for the 743622 Cortex-A9
1280           (r2p*) erratum. Under very rare conditions, a faulty
1281           optimisation in the Cortex-A9 Store Buffer may lead to data
1282           corruption. This workaround sets a specific bit in the diagnostic
1283           register of the Cortex-A9 which disables the Store Buffer
1284           optimisation, preventing the defect from occurring. This has no
1285           visible impact on the overall performance or power consumption of the
1286           processor.
1287
1288 config ARM_ERRATA_751472
1289         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1290         depends on CPU_V7
1291         help
1292           This option enables the workaround for the 751472 Cortex-A9 (prior
1293           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1294           completion of a following broadcasted operation if the second
1295           operation is received by a CPU before the ICIALLUIS has completed,
1296           potentially leading to corrupted entries in the cache or TLB.
1297
1298 config PL310_ERRATA_753970
1299         bool "PL310 errata: cache sync operation may be faulty"
1300         depends on CACHE_PL310
1301         help
1302           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1303
1304           Under some condition the effect of cache sync operation on
1305           the store buffer still remains when the operation completes.
1306           This means that the store buffer is always asked to drain and
1307           this prevents it from merging any further writes. The workaround
1308           is to replace the normal offset of cache sync operation (0x730)
1309           by another offset targeting an unmapped PL310 register 0x740.
1310           This has the same effect as the cache sync operation: store buffer
1311           drain and waiting for all buffers empty.
1312
1313 config ARM_ERRATA_754322
1314         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1315         depends on CPU_V7
1316         help
1317           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1318           r3p*) erratum. A speculative memory access may cause a page table walk
1319           which starts prior to an ASID switch but completes afterwards. This
1320           can populate the micro-TLB with a stale entry which may be hit with
1321           the new ASID. This workaround places two dsb instructions in the mm
1322           switching code so that no page table walks can cross the ASID switch.
1323
1324 config ARM_ERRATA_754327
1325         bool "ARM errata: no automatic Store Buffer drain"
1326         depends on CPU_V7 && SMP
1327         help
1328           This option enables the workaround for the 754327 Cortex-A9 (prior to
1329           r2p0) erratum. The Store Buffer does not have any automatic draining
1330           mechanism and therefore a livelock may occur if an external agent
1331           continuously polls a memory location waiting to observe an update.
1332           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1333           written polling loops from denying visibility of updates to memory.
1334
1335 config ARM_ERRATA_364296
1336         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1337         depends on CPU_V6 && !SMP
1338         help
1339           This options enables the workaround for the 364296 ARM1136
1340           r0p2 erratum (possible cache data corruption with
1341           hit-under-miss enabled). It sets the undocumented bit 31 in
1342           the auxiliary control register and the FI bit in the control
1343           register, thus disabling hit-under-miss without putting the
1344           processor into full low interrupt latency mode. ARM11MPCore
1345           is not affected.
1346
1347 config ARM_ERRATA_764369
1348         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1349         depends on CPU_V7 && SMP
1350         help
1351           This option enables the workaround for erratum 764369
1352           affecting Cortex-A9 MPCore with two or more processors (all
1353           current revisions). Under certain timing circumstances, a data
1354           cache line maintenance operation by MVA targeting an Inner
1355           Shareable memory region may fail to proceed up to either the
1356           Point of Coherency or to the Point of Unification of the
1357           system. This workaround adds a DSB instruction before the
1358           relevant cache maintenance functions and sets a specific bit
1359           in the diagnostic control register of the SCU.
1360
1361 config PL310_ERRATA_769419
1362         bool "PL310 errata: no automatic Store Buffer drain"
1363         depends on CACHE_L2X0
1364         help
1365           On revisions of the PL310 prior to r3p2, the Store Buffer does
1366           not automatically drain. This can cause normal, non-cacheable
1367           writes to be retained when the memory system is idle, leading
1368           to suboptimal I/O performance for drivers using coherent DMA.
1369           This option adds a write barrier to the cpu_idle loop so that,
1370           on systems with an outer cache, the store buffer is drained
1371           explicitly.
1372
1373 endmenu
1374
1375 source "arch/arm/common/Kconfig"
1376
1377 menu "Bus support"
1378
1379 config ARM_AMBA
1380         bool
1381
1382 config ISA
1383         bool
1384         help
1385           Find out whether you have ISA slots on your motherboard.  ISA is the
1386           name of a bus system, i.e. the way the CPU talks to the other stuff
1387           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1388           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1389           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1390
1391 # Select ISA DMA controller support
1392 config ISA_DMA
1393         bool
1394         select ISA_DMA_API
1395
1396 # Select ISA DMA interface
1397 config ISA_DMA_API
1398         bool
1399
1400 config PCI
1401         bool "PCI support" if MIGHT_HAVE_PCI
1402         help
1403           Find out whether you have a PCI motherboard. PCI is the name of a
1404           bus system, i.e. the way the CPU talks to the other stuff inside
1405           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1406           VESA. If you have PCI, say Y, otherwise N.
1407
1408 config PCI_DOMAINS
1409         bool
1410         depends on PCI
1411
1412 config PCI_NANOENGINE
1413         bool "BSE nanoEngine PCI support"
1414         depends on SA1100_NANOENGINE
1415         help
1416           Enable PCI on the BSE nanoEngine board.
1417
1418 config PCI_SYSCALL
1419         def_bool PCI
1420
1421 # Select the host bridge type
1422 config PCI_HOST_VIA82C505
1423         bool
1424         depends on PCI && ARCH_SHARK
1425         default y
1426
1427 config PCI_HOST_ITE8152
1428         bool
1429         depends on PCI && MACH_ARMCORE
1430         default y
1431         select DMABOUNCE
1432
1433 source "drivers/pci/Kconfig"
1434
1435 source "drivers/pcmcia/Kconfig"
1436
1437 endmenu
1438
1439 menu "Kernel Features"
1440
1441 config HAVE_SMP
1442         bool
1443         help
1444           This option should be selected by machines which have an SMP-
1445           capable CPU.
1446
1447           The only effect of this option is to make the SMP-related
1448           options available to the user for configuration.
1449
1450 config SMP
1451         bool "Symmetric Multi-Processing"
1452         depends on CPU_V6K || CPU_V7
1453         depends on GENERIC_CLOCKEVENTS
1454         depends on HAVE_SMP
1455         depends on MMU
1456         select USE_GENERIC_SMP_HELPERS
1457         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1458         help
1459           This enables support for systems with more than one CPU. If you have
1460           a system with only one CPU, like most personal computers, say N. If
1461           you have a system with more than one CPU, say Y.
1462
1463           If you say N here, the kernel will run on single and multiprocessor
1464           machines, but will use only one CPU of a multiprocessor machine. If
1465           you say Y here, the kernel will run on many, but not all, single
1466           processor machines. On a single processor machine, the kernel will
1467           run faster if you say N here.
1468
1469           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1470           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1471           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1472
1473           If you don't know what to do here, say N.
1474
1475 config SMP_ON_UP
1476         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1477         depends on EXPERIMENTAL
1478         depends on SMP && !XIP_KERNEL
1479         default y
1480         help
1481           SMP kernels contain instructions which fail on non-SMP processors.
1482           Enabling this option allows the kernel to modify itself to make
1483           these instructions safe.  Disabling it allows about 1K of space
1484           savings.
1485
1486           If you don't know what to do here, say Y.
1487
1488 config ARM_CPU_TOPOLOGY
1489         bool "Support cpu topology definition"
1490         depends on SMP && CPU_V7
1491         default y
1492         help
1493           Support ARM cpu topology definition. The MPIDR register defines
1494           affinity between processors which is then used to describe the cpu
1495           topology of an ARM System.
1496
1497 config SCHED_MC
1498         bool "Multi-core scheduler support"
1499         depends on ARM_CPU_TOPOLOGY
1500         help
1501           Multi-core scheduler support improves the CPU scheduler's decision
1502           making when dealing with multi-core CPU chips at a cost of slightly
1503           increased overhead in some places. If unsure say N here.
1504
1505 config SCHED_SMT
1506         bool "SMT scheduler support"
1507         depends on ARM_CPU_TOPOLOGY
1508         help
1509           Improves the CPU scheduler's decision making when dealing with
1510           MultiThreading at a cost of slightly increased overhead in some
1511           places. If unsure say N here.
1512
1513 config HAVE_ARM_SCU
1514         bool
1515         help
1516           This option enables support for the ARM system coherency unit
1517
1518 config ARM_ARCH_TIMER
1519         bool "Architected timer support"
1520         depends on CPU_V7
1521         help
1522           This option enables support for the ARM architected timer
1523
1524 config HAVE_ARM_TWD
1525         bool
1526         depends on SMP
1527         help
1528           This options enables support for the ARM timer and watchdog unit
1529
1530 choice
1531         prompt "Memory split"
1532         default VMSPLIT_3G
1533         help
1534           Select the desired split between kernel and user memory.
1535
1536           If you are not absolutely sure what you are doing, leave this
1537           option alone!
1538
1539         config VMSPLIT_3G
1540                 bool "3G/1G user/kernel split"
1541         config VMSPLIT_2G
1542                 bool "2G/2G user/kernel split"
1543         config VMSPLIT_1G
1544                 bool "1G/3G user/kernel split"
1545 endchoice
1546
1547 config PAGE_OFFSET
1548         hex
1549         default 0x40000000 if VMSPLIT_1G
1550         default 0x80000000 if VMSPLIT_2G
1551         default 0xC0000000
1552
1553 config NR_CPUS
1554         int "Maximum number of CPUs (2-32)"
1555         range 2 32
1556         depends on SMP
1557         default "4"
1558
1559 config HOTPLUG_CPU
1560         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1561         depends on SMP && HOTPLUG && EXPERIMENTAL
1562         help
1563           Say Y here to experiment with turning CPUs off and on.  CPUs
1564           can be controlled through /sys/devices/system/cpu.
1565
1566 config LOCAL_TIMERS
1567         bool "Use local timer interrupts"
1568         depends on SMP
1569         default y
1570         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1571         help
1572           Enable support for local timers on SMP platforms, rather then the
1573           legacy IPI broadcast method.  Local timers allows the system
1574           accounting to be spread across the timer interval, preventing a
1575           "thundering herd" at every timer tick.
1576
1577 config ARCH_NR_GPIO
1578         int
1579         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1580         default 355 if ARCH_U8500
1581         default 264 if MACH_H4700
1582         default 0
1583         help
1584           Maximum number of GPIOs in the system.
1585
1586           If unsure, leave the default value.
1587
1588 source kernel/Kconfig.preempt
1589
1590 config HZ
1591         int
1592         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1593                 ARCH_S5PV210 || ARCH_EXYNOS4
1594         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1595         default AT91_TIMER_HZ if ARCH_AT91
1596         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1597         default 100
1598
1599 config THUMB2_KERNEL
1600         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1601         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1602         select AEABI
1603         select ARM_ASM_UNIFIED
1604         select ARM_UNWIND
1605         help
1606           By enabling this option, the kernel will be compiled in
1607           Thumb-2 mode. A compiler/assembler that understand the unified
1608           ARM-Thumb syntax is needed.
1609
1610           If unsure, say N.
1611
1612 config THUMB2_AVOID_R_ARM_THM_JUMP11
1613         bool "Work around buggy Thumb-2 short branch relocations in gas"
1614         depends on THUMB2_KERNEL && MODULES
1615         default y
1616         help
1617           Various binutils versions can resolve Thumb-2 branches to
1618           locally-defined, preemptible global symbols as short-range "b.n"
1619           branch instructions.
1620
1621           This is a problem, because there's no guarantee the final
1622           destination of the symbol, or any candidate locations for a
1623           trampoline, are within range of the branch.  For this reason, the
1624           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1625           relocation in modules at all, and it makes little sense to add
1626           support.
1627
1628           The symptom is that the kernel fails with an "unsupported
1629           relocation" error when loading some modules.
1630
1631           Until fixed tools are available, passing
1632           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1633           code which hits this problem, at the cost of a bit of extra runtime
1634           stack usage in some cases.
1635
1636           The problem is described in more detail at:
1637               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1638
1639           Only Thumb-2 kernels are affected.
1640
1641           Unless you are sure your tools don't have this problem, say Y.
1642
1643 config ARM_ASM_UNIFIED
1644         bool
1645
1646 config AEABI
1647         bool "Use the ARM EABI to compile the kernel"
1648         help
1649           This option allows for the kernel to be compiled using the latest
1650           ARM ABI (aka EABI).  This is only useful if you are using a user
1651           space environment that is also compiled with EABI.
1652
1653           Since there are major incompatibilities between the legacy ABI and
1654           EABI, especially with regard to structure member alignment, this
1655           option also changes the kernel syscall calling convention to
1656           disambiguate both ABIs and allow for backward compatibility support
1657           (selected with CONFIG_OABI_COMPAT).
1658
1659           To use this you need GCC version 4.0.0 or later.
1660
1661 config OABI_COMPAT
1662         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1663         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1664         default y
1665         help
1666           This option preserves the old syscall interface along with the
1667           new (ARM EABI) one. It also provides a compatibility layer to
1668           intercept syscalls that have structure arguments which layout
1669           in memory differs between the legacy ABI and the new ARM EABI
1670           (only for non "thumb" binaries). This option adds a tiny
1671           overhead to all syscalls and produces a slightly larger kernel.
1672           If you know you'll be using only pure EABI user space then you
1673           can say N here. If this option is not selected and you attempt
1674           to execute a legacy ABI binary then the result will be
1675           UNPREDICTABLE (in fact it can be predicted that it won't work
1676           at all). If in doubt say Y.
1677
1678 config ARCH_HAS_HOLES_MEMORYMODEL
1679         bool
1680
1681 config ARCH_SPARSEMEM_ENABLE
1682         bool
1683
1684 config ARCH_SPARSEMEM_DEFAULT
1685         def_bool ARCH_SPARSEMEM_ENABLE
1686
1687 config ARCH_SELECT_MEMORY_MODEL
1688         def_bool ARCH_SPARSEMEM_ENABLE
1689
1690 config HAVE_ARCH_PFN_VALID
1691         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1692
1693 config HIGHMEM
1694         bool "High Memory Support"
1695         depends on MMU
1696         help
1697           The address space of ARM processors is only 4 Gigabytes large
1698           and it has to accommodate user address space, kernel address
1699           space as well as some memory mapped IO. That means that, if you
1700           have a large amount of physical memory and/or IO, not all of the
1701           memory can be "permanently mapped" by the kernel. The physical
1702           memory that is not permanently mapped is called "high memory".
1703
1704           Depending on the selected kernel/user memory split, minimum
1705           vmalloc space and actual amount of RAM, you may not need this
1706           option which should result in a slightly faster kernel.
1707
1708           If unsure, say n.
1709
1710 config HIGHPTE
1711         bool "Allocate 2nd-level pagetables from highmem"
1712         depends on HIGHMEM
1713
1714 config HW_PERF_EVENTS
1715         bool "Enable hardware performance counter support for perf events"
1716         depends on PERF_EVENTS && CPU_HAS_PMU
1717         default y
1718         help
1719           Enable hardware performance counter support for perf events. If
1720           disabled, perf events will use software events only.
1721
1722 source "mm/Kconfig"
1723
1724 config FORCE_MAX_ZONEORDER
1725         int "Maximum zone order" if ARCH_SHMOBILE
1726         range 11 64 if ARCH_SHMOBILE
1727         default "9" if SA1111
1728         default "11"
1729         help
1730           The kernel memory allocator divides physically contiguous memory
1731           blocks into "zones", where each zone is a power of two number of
1732           pages.  This option selects the largest power of two that the kernel
1733           keeps in the memory allocator.  If you need to allocate very large
1734           blocks of physically contiguous memory, then you may need to
1735           increase this value.
1736
1737           This config option is actually maximum order plus one. For example,
1738           a value of 11 means that the largest free memory block is 2^10 pages.
1739
1740 config LEDS
1741         bool "Timer and CPU usage LEDs"
1742         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1743                    ARCH_EBSA285 || ARCH_INTEGRATOR || \
1744                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1745                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1746                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1747                    ARCH_AT91 || ARCH_DAVINCI || \
1748                    ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1749         help
1750           If you say Y here, the LEDs on your machine will be used
1751           to provide useful information about your current system status.
1752
1753           If you are compiling a kernel for a NetWinder or EBSA-285, you will
1754           be able to select which LEDs are active using the options below. If
1755           you are compiling a kernel for the EBSA-110 or the LART however, the
1756           red LED will simply flash regularly to indicate that the system is
1757           still functional. It is safe to say Y here if you have a CATS
1758           system, but the driver will do nothing.
1759
1760 config LEDS_TIMER
1761         bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1762                             OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1763                             || MACH_OMAP_PERSEUS2
1764         depends on LEDS
1765         depends on !GENERIC_CLOCKEVENTS
1766         default y if ARCH_EBSA110
1767         help
1768           If you say Y here, one of the system LEDs (the green one on the
1769           NetWinder, the amber one on the EBSA285, or the red one on the LART)
1770           will flash regularly to indicate that the system is still
1771           operational. This is mainly useful to kernel hackers who are
1772           debugging unstable kernels.
1773
1774           The LART uses the same LED for both Timer LED and CPU usage LED
1775           functions. You may choose to use both, but the Timer LED function
1776           will overrule the CPU usage LED.
1777
1778 config LEDS_CPU
1779         bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1780                         !ARCH_OMAP) \
1781                         || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1782                         || MACH_OMAP_PERSEUS2
1783         depends on LEDS
1784         help
1785           If you say Y here, the red LED will be used to give a good real
1786           time indication of CPU usage, by lighting whenever the idle task
1787           is not currently executing.
1788
1789           The LART uses the same LED for both Timer LED and CPU usage LED
1790           functions. You may choose to use both, but the Timer LED function
1791           will overrule the CPU usage LED.
1792
1793 config ALIGNMENT_TRAP
1794         bool
1795         depends on CPU_CP15_MMU
1796         default y if !ARCH_EBSA110
1797         select HAVE_PROC_CPU if PROC_FS
1798         help
1799           ARM processors cannot fetch/store information which is not
1800           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1801           address divisible by 4. On 32-bit ARM processors, these non-aligned
1802           fetch/store instructions will be emulated in software if you say
1803           here, which has a severe performance impact. This is necessary for
1804           correct operation of some network protocols. With an IP-only
1805           configuration it is safe to say N, otherwise say Y.
1806
1807 config UACCESS_WITH_MEMCPY
1808         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1809         depends on MMU && EXPERIMENTAL
1810         default y if CPU_FEROCEON
1811         help
1812           Implement faster copy_to_user and clear_user methods for CPU
1813           cores where a 8-word STM instruction give significantly higher
1814           memory write throughput than a sequence of individual 32bit stores.
1815
1816           A possible side effect is a slight increase in scheduling latency
1817           between threads sharing the same address space if they invoke
1818           such copy operations with large buffers.
1819
1820           However, if the CPU data cache is using a write-allocate mode,
1821           this option is unlikely to provide any performance gain.
1822
1823 config SECCOMP
1824         bool
1825         prompt "Enable seccomp to safely compute untrusted bytecode"
1826         ---help---
1827           This kernel feature is useful for number crunching applications
1828           that may need to compute untrusted bytecode during their
1829           execution. By using pipes or other transports made available to
1830           the process as file descriptors supporting the read/write
1831           syscalls, it's possible to isolate those applications in
1832           their own address space using seccomp. Once seccomp is
1833           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1834           and the task is only allowed to execute a few safe syscalls
1835           defined by each seccomp mode.
1836
1837 config CC_STACKPROTECTOR
1838         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1839         depends on EXPERIMENTAL
1840         help
1841           This option turns on the -fstack-protector GCC feature. This
1842           feature puts, at the beginning of functions, a canary value on
1843           the stack just before the return address, and validates
1844           the value just before actually returning.  Stack based buffer
1845           overflows (that need to overwrite this return address) now also
1846           overwrite the canary, which gets detected and the attack is then
1847           neutralized via a kernel panic.
1848           This feature requires gcc version 4.2 or above.
1849
1850 config DEPRECATED_PARAM_STRUCT
1851         bool "Provide old way to pass kernel parameters"
1852         help
1853           This was deprecated in 2001 and announced to live on for 5 years.
1854           Some old boot loaders still use this way.
1855
1856 endmenu
1857
1858 menu "Boot options"
1859
1860 config USE_OF
1861         bool "Flattened Device Tree support"
1862         select OF
1863         select OF_EARLY_FLATTREE
1864         select IRQ_DOMAIN
1865         help
1866           Include support for flattened device tree machine descriptions.
1867
1868 # Compressed boot loader in ROM.  Yes, we really want to ask about
1869 # TEXT and BSS so we preserve their values in the config files.
1870 config ZBOOT_ROM_TEXT
1871         hex "Compressed ROM boot loader base address"
1872         default "0"
1873         help
1874           The physical address at which the ROM-able zImage is to be
1875           placed in the target.  Platforms which normally make use of
1876           ROM-able zImage formats normally set this to a suitable
1877           value in their defconfig file.
1878
1879           If ZBOOT_ROM is not enabled, this has no effect.
1880
1881 config ZBOOT_ROM_BSS
1882         hex "Compressed ROM boot loader BSS address"
1883         default "0"
1884         help
1885           The base address of an area of read/write memory in the target
1886           for the ROM-able zImage which must be available while the
1887           decompressor is running. It must be large enough to hold the
1888           entire decompressed kernel plus an additional 128 KiB.
1889           Platforms which normally make use of ROM-able zImage formats
1890           normally set this to a suitable value in their defconfig file.
1891
1892           If ZBOOT_ROM is not enabled, this has no effect.
1893
1894 config ZBOOT_ROM
1895         bool "Compressed boot loader in ROM/flash"
1896         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1897         help
1898           Say Y here if you intend to execute your compressed kernel image
1899           (zImage) directly from ROM or flash.  If unsure, say N.
1900
1901 choice
1902         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1903         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1904         default ZBOOT_ROM_NONE
1905         help
1906           Include experimental SD/MMC loading code in the ROM-able zImage.
1907           With this enabled it is possible to write the ROM-able zImage
1908           kernel image to an MMC or SD card and boot the kernel straight
1909           from the reset vector. At reset the processor Mask ROM will load
1910           the first part of the ROM-able zImage which in turn loads the
1911           rest the kernel image to RAM.
1912
1913 config ZBOOT_ROM_NONE
1914         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1915         help
1916           Do not load image from SD or MMC
1917
1918 config ZBOOT_ROM_MMCIF
1919         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1920         help
1921           Load image from MMCIF hardware block.
1922
1923 config ZBOOT_ROM_SH_MOBILE_SDHI
1924         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1925         help
1926           Load image from SDHI hardware block
1927
1928 endchoice
1929
1930 config ARM_APPENDED_DTB
1931         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1932         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1933         help
1934           With this option, the boot code will look for a device tree binary
1935           (DTB) appended to zImage
1936           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1937
1938           This is meant as a backward compatibility convenience for those
1939           systems with a bootloader that can't be upgraded to accommodate
1940           the documented boot protocol using a device tree.
1941
1942           Beware that there is very little in terms of protection against
1943           this option being confused by leftover garbage in memory that might
1944           look like a DTB header after a reboot if no actual DTB is appended
1945           to zImage.  Do not leave this option active in a production kernel
1946           if you don't intend to always append a DTB.  Proper passing of the
1947           location into r2 of a bootloader provided DTB is always preferable
1948           to this option.
1949
1950 config ARM_ATAG_DTB_COMPAT
1951         bool "Supplement the appended DTB with traditional ATAG information"
1952         depends on ARM_APPENDED_DTB
1953         help
1954           Some old bootloaders can't be updated to a DTB capable one, yet
1955           they provide ATAGs with memory configuration, the ramdisk address,
1956           the kernel cmdline string, etc.  Such information is dynamically
1957           provided by the bootloader and can't always be stored in a static
1958           DTB.  To allow a device tree enabled kernel to be used with such
1959           bootloaders, this option allows zImage to extract the information
1960           from the ATAG list and store it at run time into the appended DTB.
1961
1962 config CMDLINE
1963         string "Default kernel command string"
1964         default ""
1965         help
1966           On some architectures (EBSA110 and CATS), there is currently no way
1967           for the boot loader to pass arguments to the kernel. For these
1968           architectures, you should supply some command-line options at build
1969           time by entering them here. As a minimum, you should specify the
1970           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1971
1972 choice
1973         prompt "Kernel command line type" if CMDLINE != ""
1974         default CMDLINE_FROM_BOOTLOADER
1975
1976 config CMDLINE_FROM_BOOTLOADER
1977         bool "Use bootloader kernel arguments if available"
1978         help
1979           Uses the command-line options passed by the boot loader. If
1980           the boot loader doesn't provide any, the default kernel command
1981           string provided in CMDLINE will be used.
1982
1983 config CMDLINE_EXTEND
1984         bool "Extend bootloader kernel arguments"
1985         help
1986           The command-line arguments provided by the boot loader will be
1987           appended to the default kernel command string.
1988
1989 config CMDLINE_FORCE
1990         bool "Always use the default kernel command string"
1991         help
1992           Always use the default kernel command string, even if the boot
1993           loader passes other arguments to the kernel.
1994           This is useful if you cannot or don't want to change the
1995           command-line options your boot loader passes to the kernel.
1996 endchoice
1997
1998 config XIP_KERNEL
1999         bool "Kernel Execute-In-Place from ROM"
2000         depends on !ZBOOT_ROM && !ARM_LPAE
2001         help
2002           Execute-In-Place allows the kernel to run from non-volatile storage
2003           directly addressable by the CPU, such as NOR flash. This saves RAM
2004           space since the text section of the kernel is not loaded from flash
2005           to RAM.  Read-write sections, such as the data section and stack,
2006           are still copied to RAM.  The XIP kernel is not compressed since
2007           it has to run directly from flash, so it will take more space to
2008           store it.  The flash address used to link the kernel object files,
2009           and for storing it, is configuration dependent. Therefore, if you
2010           say Y here, you must know the proper physical address where to
2011           store the kernel image depending on your own flash memory usage.
2012
2013           Also note that the make target becomes "make xipImage" rather than
2014           "make zImage" or "make Image".  The final kernel binary to put in
2015           ROM memory will be arch/arm/boot/xipImage.
2016
2017           If unsure, say N.
2018
2019 config XIP_PHYS_ADDR
2020         hex "XIP Kernel Physical Location"
2021         depends on XIP_KERNEL
2022         default "0x00080000"
2023         help
2024           This is the physical address in your flash memory the kernel will
2025           be linked for and stored to.  This address is dependent on your
2026           own flash usage.
2027
2028 config KEXEC
2029         bool "Kexec system call (EXPERIMENTAL)"
2030         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2031         help
2032           kexec is a system call that implements the ability to shutdown your
2033           current kernel, and to start another kernel.  It is like a reboot
2034           but it is independent of the system firmware.   And like a reboot
2035           you can start any kernel with it, not just Linux.
2036
2037           It is an ongoing process to be certain the hardware in a machine
2038           is properly shutdown, so do not be surprised if this code does not
2039           initially work for you.  It may help to enable device hotplugging
2040           support.
2041
2042 config ATAGS_PROC
2043         bool "Export atags in procfs"
2044         depends on KEXEC
2045         default y
2046         help
2047           Should the atags used to boot the kernel be exported in an "atags"
2048           file in procfs. Useful with kexec.
2049
2050 config CRASH_DUMP
2051         bool "Build kdump crash kernel (EXPERIMENTAL)"
2052         depends on EXPERIMENTAL
2053         help
2054           Generate crash dump after being started by kexec. This should
2055           be normally only set in special crash dump kernels which are
2056           loaded in the main kernel with kexec-tools into a specially
2057           reserved region and then later executed after a crash by
2058           kdump/kexec. The crash dump kernel must be compiled to a
2059           memory address not used by the main kernel
2060
2061           For more details see Documentation/kdump/kdump.txt
2062
2063 config AUTO_ZRELADDR
2064         bool "Auto calculation of the decompressed kernel image address"
2065         depends on !ZBOOT_ROM && !ARCH_U300
2066         help
2067           ZRELADDR is the physical address where the decompressed kernel
2068           image will be placed. If AUTO_ZRELADDR is selected, the address
2069           will be determined at run-time by masking the current IP with
2070           0xf8000000. This assumes the zImage being placed in the first 128MB
2071           from start of memory.
2072
2073 endmenu
2074
2075 menu "CPU Power Management"
2076
2077 if ARCH_HAS_CPUFREQ
2078
2079 source "drivers/cpufreq/Kconfig"
2080
2081 config CPU_FREQ_IMX
2082         tristate "CPUfreq driver for i.MX CPUs"
2083         depends on ARCH_MXC && CPU_FREQ
2084         help
2085           This enables the CPUfreq driver for i.MX CPUs.
2086
2087 config CPU_FREQ_SA1100
2088         bool
2089
2090 config CPU_FREQ_SA1110
2091         bool
2092
2093 config CPU_FREQ_INTEGRATOR
2094         tristate "CPUfreq driver for ARM Integrator CPUs"
2095         depends on ARCH_INTEGRATOR && CPU_FREQ
2096         default y
2097         help
2098           This enables the CPUfreq driver for ARM Integrator CPUs.
2099
2100           For details, take a look at <file:Documentation/cpu-freq>.
2101
2102           If in doubt, say Y.
2103
2104 config CPU_FREQ_PXA
2105         bool
2106         depends on CPU_FREQ && ARCH_PXA && PXA25x
2107         default y
2108         select CPU_FREQ_TABLE
2109         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2110
2111 config CPU_FREQ_S3C
2112         bool
2113         help
2114           Internal configuration node for common cpufreq on Samsung SoC
2115
2116 config CPU_FREQ_S3C24XX
2117         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2118         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2119         select CPU_FREQ_S3C
2120         help
2121           This enables the CPUfreq driver for the Samsung S3C24XX family
2122           of CPUs.
2123
2124           For details, take a look at <file:Documentation/cpu-freq>.
2125
2126           If in doubt, say N.
2127
2128 config CPU_FREQ_S3C24XX_PLL
2129         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2130         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2131         help
2132           Compile in support for changing the PLL frequency from the
2133           S3C24XX series CPUfreq driver. The PLL takes time to settle
2134           after a frequency change, so by default it is not enabled.
2135
2136           This also means that the PLL tables for the selected CPU(s) will
2137           be built which may increase the size of the kernel image.
2138
2139 config CPU_FREQ_S3C24XX_DEBUG
2140         bool "Debug CPUfreq Samsung driver core"
2141         depends on CPU_FREQ_S3C24XX
2142         help
2143           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2144
2145 config CPU_FREQ_S3C24XX_IODEBUG
2146         bool "Debug CPUfreq Samsung driver IO timing"
2147         depends on CPU_FREQ_S3C24XX
2148         help
2149           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2150
2151 config CPU_FREQ_S3C24XX_DEBUGFS
2152         bool "Export debugfs for CPUFreq"
2153         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2154         help
2155           Export status information via debugfs.
2156
2157 endif
2158
2159 source "drivers/cpuidle/Kconfig"
2160
2161 endmenu
2162
2163 menu "Floating point emulation"
2164
2165 comment "At least one emulation must be selected"
2166
2167 config FPE_NWFPE
2168         bool "NWFPE math emulation"
2169         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2170         ---help---
2171           Say Y to include the NWFPE floating point emulator in the kernel.
2172           This is necessary to run most binaries. Linux does not currently
2173           support floating point hardware so you need to say Y here even if
2174           your machine has an FPA or floating point co-processor podule.
2175
2176           You may say N here if you are going to load the Acorn FPEmulator
2177           early in the bootup.
2178
2179 config FPE_NWFPE_XP
2180         bool "Support extended precision"
2181         depends on FPE_NWFPE
2182         help
2183           Say Y to include 80-bit support in the kernel floating-point
2184           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2185           Note that gcc does not generate 80-bit operations by default,
2186           so in most cases this option only enlarges the size of the
2187           floating point emulator without any good reason.
2188
2189           You almost surely want to say N here.
2190
2191 config FPE_FASTFPE
2192         bool "FastFPE math emulation (EXPERIMENTAL)"
2193         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2194         ---help---
2195           Say Y here to include the FAST floating point emulator in the kernel.
2196           This is an experimental much faster emulator which now also has full
2197           precision for the mantissa.  It does not support any exceptions.
2198           It is very simple, and approximately 3-6 times faster than NWFPE.
2199
2200           It should be sufficient for most programs.  It may be not suitable
2201           for scientific calculations, but you have to check this for yourself.
2202           If you do not feel you need a faster FP emulation you should better
2203           choose NWFPE.
2204
2205 config VFP
2206         bool "VFP-format floating point maths"
2207         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2208         help
2209           Say Y to include VFP support code in the kernel. This is needed
2210           if your hardware includes a VFP unit.
2211
2212           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2213           release notes and additional status information.
2214
2215           Say N if your target does not have VFP hardware.
2216
2217 config VFPv3
2218         bool
2219         depends on VFP
2220         default y if CPU_V7
2221
2222 config NEON
2223         bool "Advanced SIMD (NEON) Extension support"
2224         depends on VFPv3 && CPU_V7
2225         help
2226           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2227           Extension.
2228
2229 endmenu
2230
2231 menu "Userspace binary formats"
2232
2233 source "fs/Kconfig.binfmt"
2234
2235 config ARTHUR
2236         tristate "RISC OS personality"
2237         depends on !AEABI
2238         help
2239           Say Y here to include the kernel code necessary if you want to run
2240           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2241           experimental; if this sounds frightening, say N and sleep in peace.
2242           You can also say M here to compile this support as a module (which
2243           will be called arthur).
2244
2245 endmenu
2246
2247 menu "Power management options"
2248
2249 source "kernel/power/Kconfig"
2250
2251 config ARCH_SUSPEND_POSSIBLE
2252         depends on !ARCH_S5PC100 && !ARCH_TEGRA
2253         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2254                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2255         def_bool y
2256
2257 config ARM_CPU_SUSPEND
2258         def_bool PM_SLEEP
2259
2260 endmenu
2261
2262 source "net/Kconfig"
2263
2264 source "drivers/Kconfig"
2265
2266 source "fs/Kconfig"
2267
2268 source "arch/arm/Kconfig.debug"
2269
2270 source "security/Kconfig"
2271
2272 source "crypto/Kconfig"
2273
2274 source "lib/Kconfig"