arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAVE_CUSTOM_GPIO_H
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_WANT_IPC_PARSE_VERSION
   9         select BUILDTIME_EXTABLE_SORT if MMU
  10         select CPU_PM if (SUSPEND || CPU_IDLE)
  11         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
  12         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  13         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  14         select GENERIC_IRQ_PROBE
  15         select GENERIC_IRQ_SHOW
  16         select GENERIC_PCI_IOMAP
  17         select GENERIC_SMP_IDLE_THREAD
  18         select GENERIC_IDLE_POLL_SETUP
  19         select GENERIC_STRNCPY_FROM_USER
  20         select GENERIC_STRNLEN_USER
  21         select HARDIRQS_SW_RESEND
  22         select HAVE_AOUT
  23         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  24         select HAVE_ARCH_KGDB
  25         select HAVE_ARCH_SECCOMP_FILTER
  26         select HAVE_ARCH_TRACEHOOK
  27         select HAVE_BPF_JIT
  28         select HAVE_C_RECORDMCOUNT
  29         select HAVE_DEBUG_KMEMLEAK
  30         select HAVE_DMA_API_DEBUG
  31         select HAVE_DMA_ATTRS
  32         select HAVE_DMA_CONTIGUOUS if MMU
  33         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  34         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  35         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  36         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  37         select HAVE_GENERIC_DMA_COHERENT
  38         select HAVE_GENERIC_HARDIRQS
  39         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  40         select HAVE_IDE if PCI || ISA || PCMCIA
  41         select HAVE_IRQ_TIME_ACCOUNTING
  42         select HAVE_KERNEL_GZIP
  43         select HAVE_KERNEL_LZMA
  44         select HAVE_KERNEL_LZO
  45         select HAVE_KERNEL_XZ
  46         select HAVE_KPROBES if !XIP_KERNEL
  47         select HAVE_KRETPROBES if (HAVE_KPROBES)
  48         select HAVE_MEMBLOCK
  49         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  50         select HAVE_PERF_EVENTS
  51         select HAVE_REGS_AND_STACK_ACCESS_API
  52         select HAVE_SYSCALL_TRACEPOINTS
  53         select HAVE_UID16
  54         select KTIME_SCALAR
  55         select PERF_USE_VMALLOC
  56         select RTC_LIB
  57         select SYS_SUPPORTS_APM_EMULATION
  58         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  59         select MODULES_USE_ELF_REL
  60         select CLONE_BACKWARDS
  61         select OLD_SIGSUSPEND3
  62         select OLD_SIGACTION
  63         select HAVE_CONTEXT_TRACKING
  64         help
  65           The ARM series is a line of low-power-consumption RISC chip designs
  66           licensed by ARM Ltd and targeted at embedded applications and
  67           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  68           manufactured, but legacy ARM-based PC hardware remains popular in
  69           Europe.  There is an ARM Linux project with a web page at
  70           <http://www.arm.linux.org.uk/>.
  71
  72 config ARM_HAS_SG_CHAIN
  73         bool
  74
  75 config NEED_SG_DMA_LENGTH
  76         bool
  77
  78 config ARM_DMA_USE_IOMMU
  79         bool
  80         select ARM_HAS_SG_CHAIN
  81         select NEED_SG_DMA_LENGTH
  82
  83 if ARM_DMA_USE_IOMMU
  84
  85 config ARM_DMA_IOMMU_ALIGNMENT
  86         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
  87         range 4 9
  88         default 8
  89         help
  90           DMA mapping framework by default aligns all buffers to the smallest
  91           PAGE_SIZE order which is greater than or equal to the requested buffer
  92           size. This works well for buffers up to a few hundreds kilobytes, but
  93           for larger buffers it just a waste of address space. Drivers which has
  94           relatively small addressing window (like 64Mib) might run out of
  95           virtual space with just a few allocations.
  96
  97           With this parameter you can specify the maximum PAGE_SIZE order for
  98           DMA IOMMU buffers. Larger buffers will be aligned only to this
  99           specified order. The order is expressed as a power of two multiplied
 100           by the PAGE_SIZE.
 101
 102 endif
 103
 104 config HAVE_PWM
 105         bool
 106
 107 config MIGHT_HAVE_PCI
 108         bool
 109
 110 config SYS_SUPPORTS_APM_EMULATION
 111         bool
 112
 113 config HAVE_TCM
 114         bool
 115         select GENERIC_ALLOCATOR
 116
 117 config HAVE_PROC_CPU
 118         bool
 119
 120 config NO_IOPORT
 121         bool
 122
 123 config EISA
 124         bool
 125         ---help---
 126           The Extended Industry Standard Architecture (EISA) bus was
 127           developed as an open alternative to the IBM MicroChannel bus.
 128
 129           The EISA bus provided some of the features of the IBM MicroChannel
 130           bus while maintaining backward compatibility with cards made for
 131           the older ISA bus.  The EISA bus saw limited use between 1988 and
 132           1995 when it was made obsolete by the PCI bus.
 133
 134           Say Y here if you are building a kernel for an EISA-based machine.
 135
 136           Otherwise, say N.
 137
 138 config SBUS
 139         bool
 140
 141 config STACKTRACE_SUPPORT
 142         bool
 143         default y
 144
 145 config HAVE_LATENCYTOP_SUPPORT
 146         bool
 147         depends on !SMP
 148         default y
 149
 150 config LOCKDEP_SUPPORT
 151         bool
 152         default y
 153
 154 config TRACE_IRQFLAGS_SUPPORT
 155         bool
 156         default y
 157
 158 config RWSEM_GENERIC_SPINLOCK
 159         bool
 160         default y
 161
 162 config RWSEM_XCHGADD_ALGORITHM
 163         bool
 164
 165 config ARCH_HAS_ILOG2_U32
 166         bool
 167
 168 config ARCH_HAS_ILOG2_U64
 169         bool
 170
 171 config ARCH_HAS_CPUFREQ
 172         bool
 173         help
 174           Internal node to signify that the ARCH has CPUFREQ support
 175           and that the relevant menu configurations are displayed for
 176           it.
 177
 178 config GENERIC_HWEIGHT
 179         bool
 180         default y
 181
 182 config GENERIC_CALIBRATE_DELAY
 183         bool
 184         default y
 185
 186 config ARCH_MAY_HAVE_PC_FDC
 187         bool
 188
 189 config ZONE_DMA
 190         bool
 191
 192 config NEED_DMA_MAP_STATE
 193        def_bool y
 194
 195 config ARCH_HAS_DMA_SET_COHERENT_MASK
 196         bool
 197
 198 config GENERIC_ISA_DMA
 199         bool
 200
 201 config FIQ
 202         bool
 203
 204 config NEED_RET_TO_USER
 205         bool
 206
 207 config ARCH_MTD_XIP
 208         bool
 209
 210 config VECTORS_BASE
 211         hex
 212         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 213         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 214         default 0x00000000
 215         help
 216           The base address of exception vectors.
 217
 218 config ARM_PATCH_PHYS_VIRT
 219         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 220         default y
 221         depends on !XIP_KERNEL && MMU
 222         depends on !ARCH_REALVIEW || !SPARSEMEM
 223         help
 224           Patch phys-to-virt and virt-to-phys translation functions at
 225           boot and module load time according to the position of the
 226           kernel in system memory.
 227
 228           This can only be used with non-XIP MMU kernels where the base
 229           of physical memory is at a 16MB boundary.
 230
 231           Only disable this option if you know that you do not require
 232           this feature (eg, building a kernel for a single machine) and
 233           you need to shrink the kernel to the minimal size.
 234
 235 config NEED_MACH_GPIO_H
 236         bool
 237         help
 238           Select this when mach/gpio.h is required to provide special
 239           definitions for this platform. The need for mach/gpio.h should
 240           be avoided when possible.
 241
 242 config NEED_MACH_IO_H
 243         bool
 244         help
 245           Select this when mach/io.h is required to provide special
 246           definitions for this platform.  The need for mach/io.h should
 247           be avoided when possible.
 248
 249 config NEED_MACH_MEMORY_H
 250         bool
 251         help
 252           Select this when mach/memory.h is required to provide special
 253           definitions for this platform.  The need for mach/memory.h should
 254           be avoided when possible.
 255
 256 config PHYS_OFFSET
 257         hex "Physical address of main memory" if MMU
 258         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 259         default DRAM_BASE if !MMU
 260         help
 261           Please provide the physical address corresponding to the
 262           location of main memory in your system.
 263
 264 config GENERIC_BUG
 265         def_bool y
 266         depends on BUG
 267
 268 source "init/Kconfig"
 269
 270 source "kernel/Kconfig.freezer"
 271
 272 menu "System Type"
 273
 274 config MMU
 275         bool "MMU-based Paged Memory Management Support"
 276         default y
 277         help
 278           Select if you want MMU-based virtualised addressing space
 279           support by paged memory management. If unsure, say 'Y'.
 280
 281 #
 282 # The "ARM system type" choice list is ordered alphabetically by option
 283 # text.  Please add new entries in the option alphabetic order.
 284 #
 285 choice
 286         prompt "ARM system type"
 287         default ARCH_VERSATILE if !MMU
 288         default ARCH_MULTIPLATFORM if MMU
 289
 290 config ARCH_MULTIPLATFORM
 291         bool "Allow multiple platforms to be selected"
 292         depends on MMU
 293         select ARM_PATCH_PHYS_VIRT
 294         select AUTO_ZRELADDR
 295         select COMMON_CLK
 296         select MULTI_IRQ_HANDLER
 297         select SPARSE_IRQ
 298         select USE_OF
 299
 300 config ARCH_INTEGRATOR
 301         bool "ARM Ltd. Integrator family"
 302         select ARCH_HAS_CPUFREQ
 303         select ARM_AMBA
 304         select COMMON_CLK
 305         select COMMON_CLK_VERSATILE
 306         select GENERIC_CLOCKEVENTS
 307         select HAVE_TCM
 308         select ICST
 309         select MULTI_IRQ_HANDLER
 310         select NEED_MACH_MEMORY_H
 311         select PLAT_VERSATILE
 312         select SPARSE_IRQ
 313         select VERSATILE_FPGA_IRQ
 314         help
 315           Support for ARM's Integrator platform.
 316
 317 config ARCH_REALVIEW
 318         bool "ARM Ltd. RealView family"
 319         select ARCH_WANT_OPTIONAL_GPIOLIB
 320         select ARM_AMBA
 321         select ARM_TIMER_SP804
 322         select COMMON_CLK
 323         select COMMON_CLK_VERSATILE
 324         select GENERIC_CLOCKEVENTS
 325         select GPIO_PL061 if GPIOLIB
 326         select ICST
 327         select NEED_MACH_MEMORY_H
 328         select PLAT_VERSATILE
 329         select PLAT_VERSATILE_CLCD
 330         help
 331           This enables support for ARM Ltd RealView boards.
 332
 333 config ARCH_VERSATILE
 334         bool "ARM Ltd. Versatile family"
 335         select ARCH_WANT_OPTIONAL_GPIOLIB
 336         select ARM_AMBA
 337         select ARM_TIMER_SP804
 338         select ARM_VIC
 339         select CLKDEV_LOOKUP
 340         select GENERIC_CLOCKEVENTS
 341         select HAVE_MACH_CLKDEV
 342         select ICST
 343         select PLAT_VERSATILE
 344         select PLAT_VERSATILE_CLCD
 345         select PLAT_VERSATILE_CLOCK
 346         select VERSATILE_FPGA_IRQ
 347         help
 348           This enables support for ARM Ltd Versatile board.
 349
 350 config ARCH_AT91
 351         bool "Atmel AT91"
 352         select ARCH_REQUIRE_GPIOLIB
 353         select CLKDEV_LOOKUP
 354         select HAVE_CLK
 355         select IRQ_DOMAIN
 356         select NEED_MACH_GPIO_H
 357         select NEED_MACH_IO_H if PCCARD
 358         select PINCTRL
 359         select PINCTRL_AT91 if USE_OF
 360         help
 361           This enables support for systems based on Atmel
 362           AT91RM9200 and AT91SAM9* processors.
 363
 364 config ARCH_CLPS711X
 365         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 366         select ARCH_REQUIRE_GPIOLIB
 367         select AUTO_ZRELADDR
 368         select CLKDEV_LOOKUP
 369         select COMMON_CLK
 370         select CPU_ARM720T
 371         select GENERIC_CLOCKEVENTS
 372         select MULTI_IRQ_HANDLER
 373         select NEED_MACH_MEMORY_H
 374         select SPARSE_IRQ
 375         help
 376           Support for Cirrus Logic 711x/721x/731x based boards.
 377
 378 config ARCH_GEMINI
 379         bool "Cortina Systems Gemini"
 380         select ARCH_REQUIRE_GPIOLIB
 381         select ARCH_USES_GETTIMEOFFSET
 382         select NEED_MACH_GPIO_H
 383         select CPU_FA526
 384         help
 385           Support for the Cortina Systems Gemini family SoCs
 386
 387 config ARCH_EBSA110
 388         bool "EBSA-110"
 389         select ARCH_USES_GETTIMEOFFSET
 390         select CPU_SA110
 391         select ISA
 392         select NEED_MACH_IO_H
 393         select NEED_MACH_MEMORY_H
 394         select NO_IOPORT
 395         help
 396           This is an evaluation board for the StrongARM processor available
 397           from Digital. It has limited hardware on-board, including an
 398           Ethernet interface, two PCMCIA sockets, two serial ports and a
 399           parallel port.
 400
 401 config ARCH_EP93XX
 402         bool "EP93xx-based"
 403         select ARCH_HAS_HOLES_MEMORYMODEL
 404         select ARCH_REQUIRE_GPIOLIB
 405         select ARCH_USES_GETTIMEOFFSET
 406         select ARM_AMBA
 407         select ARM_VIC
 408         select CLKDEV_LOOKUP
 409         select CPU_ARM920T
 410         select NEED_MACH_MEMORY_H
 411         help
 412           This enables support for the Cirrus EP93xx series of CPUs.
 413
 414 config ARCH_FOOTBRIDGE
 415         bool "FootBridge"
 416         select CPU_SA110
 417         select FOOTBRIDGE
 418         select GENERIC_CLOCKEVENTS
 419         select HAVE_IDE
 420         select NEED_MACH_IO_H if !MMU
 421         select NEED_MACH_MEMORY_H
 422         help
 423           Support for systems based on the DC21285 companion chip
 424           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 425
 426 config ARCH_NETX
 427         bool "Hilscher NetX based"
 428         select ARM_VIC
 429         select CLKSRC_MMIO
 430         select CPU_ARM926T
 431         select GENERIC_CLOCKEVENTS
 432         help
 433           This enables support for systems based on the Hilscher NetX Soc
 434
 435 config ARCH_IOP13XX
 436         bool "IOP13xx-based"
 437         depends on MMU
 438         select ARCH_SUPPORTS_MSI
 439         select CPU_XSC3
 440         select NEED_MACH_MEMORY_H
 441         select NEED_RET_TO_USER
 442         select PCI
 443         select PLAT_IOP
 444         select VMSPLIT_1G
 445         help
 446           Support for Intel's IOP13XX (XScale) family of processors.
 447
 448 config ARCH_IOP32X
 449         bool "IOP32x-based"
 450         depends on MMU
 451         select ARCH_REQUIRE_GPIOLIB
 452         select CPU_XSCALE
 453         select NEED_MACH_GPIO_H
 454         select NEED_RET_TO_USER
 455         select PCI
 456         select PLAT_IOP
 457         help
 458           Support for Intel's 80219 and IOP32X (XScale) family of
 459           processors.
 460
 461 config ARCH_IOP33X
 462         bool "IOP33x-based"
 463         depends on MMU
 464         select ARCH_REQUIRE_GPIOLIB
 465         select CPU_XSCALE
 466         select NEED_MACH_GPIO_H
 467         select NEED_RET_TO_USER
 468         select PCI
 469         select PLAT_IOP
 470         help
 471           Support for Intel's IOP33X (XScale) family of processors.
 472
 473 config ARCH_IXP4XX
 474         bool "IXP4xx-based"
 475         depends on MMU
 476         select ARCH_HAS_DMA_SET_COHERENT_MASK
 477         select ARCH_REQUIRE_GPIOLIB
 478         select CLKSRC_MMIO
 479         select CPU_XSCALE
 480         select DMABOUNCE if PCI
 481         select GENERIC_CLOCKEVENTS
 482         select MIGHT_HAVE_PCI
 483         select NEED_MACH_IO_H
 484         select USB_EHCI_BIG_ENDIAN_MMIO
 485         select USB_EHCI_BIG_ENDIAN_DESC
 486         help
 487           Support for Intel's IXP4XX (XScale) family of processors.
 488
 489 config ARCH_DOVE
 490         bool "Marvell Dove"
 491         select ARCH_REQUIRE_GPIOLIB
 492         select CPU_PJ4
 493         select GENERIC_CLOCKEVENTS
 494         select MIGHT_HAVE_PCI
 495         select PINCTRL
 496         select PINCTRL_DOVE
 497         select PLAT_ORION_LEGACY
 498         select USB_ARCH_HAS_EHCI
 499         select MVEBU_MBUS
 500         help
 501           Support for the Marvell Dove SoC 88AP510
 502
 503 config ARCH_KIRKWOOD
 504         bool "Marvell Kirkwood"
 505         select ARCH_REQUIRE_GPIOLIB
 506         select CPU_FEROCEON
 507         select GENERIC_CLOCKEVENTS
 508         select PCI
 509         select PCI_QUIRKS
 510         select PINCTRL
 511         select PINCTRL_KIRKWOOD
 512         select PLAT_ORION_LEGACY
 513         select MVEBU_MBUS
 514         help
 515           Support for the following Marvell Kirkwood series SoCs:
 516           88F6180, 88F6192 and 88F6281.
 517
 518 config ARCH_MV78XX0
 519         bool "Marvell MV78xx0"
 520         select ARCH_REQUIRE_GPIOLIB
 521         select CPU_FEROCEON
 522         select GENERIC_CLOCKEVENTS
 523         select PCI
 524         select PLAT_ORION_LEGACY
 525         select MVEBU_MBUS
 526         help
 527           Support for the following Marvell MV78xx0 series SoCs:
 528           MV781x0, MV782x0.
 529
 530 config ARCH_ORION5X
 531         bool "Marvell Orion"
 532         depends on MMU
 533         select ARCH_REQUIRE_GPIOLIB
 534         select CPU_FEROCEON
 535         select GENERIC_CLOCKEVENTS
 536         select PCI
 537         select PLAT_ORION_LEGACY
 538         select MVEBU_MBUS
 539         help
 540           Support for the following Marvell Orion 5x series SoCs:
 541           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 542           Orion-2 (5281), Orion-1-90 (6183).
 543
 544 config ARCH_MMP
 545         bool "Marvell PXA168/910/MMP2"
 546         depends on MMU
 547         select ARCH_REQUIRE_GPIOLIB
 548         select CLKDEV_LOOKUP
 549         select GENERIC_ALLOCATOR
 550         select GENERIC_CLOCKEVENTS
 551         select GPIO_PXA
 552         select IRQ_DOMAIN
 553         select NEED_MACH_GPIO_H
 554         select PINCTRL
 555         select PLAT_PXA
 556         select SPARSE_IRQ
 557         help
 558           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 559
 560 config ARCH_KS8695
 561         bool "Micrel/Kendin KS8695"
 562         select ARCH_REQUIRE_GPIOLIB
 563         select CLKSRC_MMIO
 564         select CPU_ARM922T
 565         select GENERIC_CLOCKEVENTS
 566         select NEED_MACH_MEMORY_H
 567         help
 568           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 569           System-on-Chip devices.
 570
 571 config ARCH_W90X900
 572         bool "Nuvoton W90X900 CPU"
 573         select ARCH_REQUIRE_GPIOLIB
 574         select CLKDEV_LOOKUP
 575         select CLKSRC_MMIO
 576         select CPU_ARM926T
 577         select GENERIC_CLOCKEVENTS
 578         help
 579           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 580           At present, the w90x900 has been renamed nuc900, regarding
 581           the ARM series product line, you can login the following
 582           link address to know more.
 583
 584           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 585                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 586
 587 config ARCH_LPC32XX
 588         bool "NXP LPC32XX"
 589         select ARCH_REQUIRE_GPIOLIB
 590         select ARM_AMBA
 591         select CLKDEV_LOOKUP
 592         select CLKSRC_MMIO
 593         select CPU_ARM926T
 594         select GENERIC_CLOCKEVENTS
 595         select HAVE_IDE
 596         select HAVE_PWM
 597         select USB_ARCH_HAS_OHCI
 598         select USE_OF
 599         help
 600           Support for the NXP LPC32XX family of processors
 601
 602 config ARCH_PXA
 603         bool "PXA2xx/PXA3xx-based"
 604         depends on MMU
 605         select ARCH_HAS_CPUFREQ
 606         select ARCH_MTD_XIP
 607         select ARCH_REQUIRE_GPIOLIB
 608         select ARM_CPU_SUSPEND if PM
 609         select AUTO_ZRELADDR
 610         select CLKDEV_LOOKUP
 611         select CLKSRC_MMIO
 612         select GENERIC_CLOCKEVENTS
 613         select GPIO_PXA
 614         select HAVE_IDE
 615         select MULTI_IRQ_HANDLER
 616         select NEED_MACH_GPIO_H
 617         select PLAT_PXA
 618         select SPARSE_IRQ
 619         help
 620           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 621
 622 config ARCH_MSM
 623         bool "Qualcomm MSM"
 624         select ARCH_REQUIRE_GPIOLIB
 625         select CLKDEV_LOOKUP
 626         select GENERIC_CLOCKEVENTS
 627         select HAVE_CLK
 628         help
 629           Support for Qualcomm MSM/QSD based systems.  This runs on the
 630           apps processor of the MSM/QSD and depends on a shared memory
 631           interface to the modem processor which runs the baseband
 632           stack and controls some vital subsystems
 633           (clock and power control, etc).
 634
 635 config ARCH_SHMOBILE
 636         bool "Renesas SH-Mobile / R-Mobile"
 637         select CLKDEV_LOOKUP
 638         select GENERIC_CLOCKEVENTS
 639         select HAVE_ARM_SCU if SMP
 640         select HAVE_ARM_TWD if LOCAL_TIMERS
 641         select HAVE_CLK
 642         select HAVE_MACH_CLKDEV
 643         select HAVE_SMP
 644         select MIGHT_HAVE_CACHE_L2X0
 645         select MULTI_IRQ_HANDLER
 646         select NEED_MACH_MEMORY_H
 647         select NO_IOPORT
 648         select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
 649         select PM_GENERIC_DOMAINS if PM
 650         select SPARSE_IRQ
 651         help
 652           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 653
 654 config ARCH_RPC
 655         bool "RiscPC"
 656         select ARCH_ACORN
 657         select ARCH_MAY_HAVE_PC_FDC
 658         select ARCH_SPARSEMEM_ENABLE
 659         select ARCH_USES_GETTIMEOFFSET
 660         select FIQ
 661         select HAVE_IDE
 662         select HAVE_PATA_PLATFORM
 663         select ISA_DMA_API
 664         select NEED_MACH_IO_H
 665         select NEED_MACH_MEMORY_H
 666         select NO_IOPORT
 667         select VIRT_TO_BUS
 668         help
 669           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 670           CD-ROM interface, serial and parallel port, and the floppy drive.
 671
 672 config ARCH_SA1100
 673         bool "SA1100-based"
 674         select ARCH_HAS_CPUFREQ
 675         select ARCH_MTD_XIP
 676         select ARCH_REQUIRE_GPIOLIB
 677         select ARCH_SPARSEMEM_ENABLE
 678         select CLKDEV_LOOKUP
 679         select CLKSRC_MMIO
 680         select CPU_FREQ
 681         select CPU_SA1100
 682         select GENERIC_CLOCKEVENTS
 683         select HAVE_IDE
 684         select ISA
 685         select NEED_MACH_GPIO_H
 686         select NEED_MACH_MEMORY_H
 687         select SPARSE_IRQ
 688         help
 689           Support for StrongARM 11x0 based boards.
 690
 691 config ARCH_S3C24XX
 692         bool "Samsung S3C24XX SoCs"
 693         select ARCH_HAS_CPUFREQ
 694         select ARCH_REQUIRE_GPIOLIB
 695         select CLKDEV_LOOKUP
 696         select CLKSRC_MMIO
 697         select GENERIC_CLOCKEVENTS
 698         select HAVE_CLK
 699         select HAVE_S3C2410_I2C if I2C
 700         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 701         select HAVE_S3C_RTC if RTC_CLASS
 702         select MULTI_IRQ_HANDLER
 703         select NEED_MACH_GPIO_H
 704         select NEED_MACH_IO_H
 705         help
 706           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 707           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 708           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 709           Samsung SMDK2410 development board (and derivatives).
 710
 711 config ARCH_S3C64XX
 712         bool "Samsung S3C64XX"
 713         select ARCH_HAS_CPUFREQ
 714         select ARCH_REQUIRE_GPIOLIB
 715         select ARM_VIC
 716         select CLKDEV_LOOKUP
 717         select CLKSRC_MMIO
 718         select CPU_V6
 719         select GENERIC_CLOCKEVENTS
 720         select HAVE_CLK
 721         select HAVE_S3C2410_I2C if I2C
 722         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 723         select HAVE_TCM
 724         select NEED_MACH_GPIO_H
 725         select NO_IOPORT
 726         select PLAT_SAMSUNG
 727         select S3C_DEV_NAND
 728         select S3C_GPIO_TRACK
 729         select SAMSUNG_CLKSRC
 730         select SAMSUNG_GPIOLIB_4BIT
 731         select SAMSUNG_IRQ_VIC_TIMER
 732         select USB_ARCH_HAS_OHCI
 733         help
 734           Samsung S3C64XX series based systems
 735
 736 config ARCH_S5P64X0
 737         bool "Samsung S5P6440 S5P6450"
 738         select CLKDEV_LOOKUP
 739         select CLKSRC_MMIO
 740         select CPU_V6
 741         select GENERIC_CLOCKEVENTS
 742         select HAVE_CLK
 743         select HAVE_S3C2410_I2C if I2C
 744         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 745         select HAVE_S3C_RTC if RTC_CLASS
 746         select NEED_MACH_GPIO_H
 747         help
 748           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 749           SMDK6450.
 750
 751 config ARCH_S5PC100
 752         bool "Samsung S5PC100"
 753         select ARCH_REQUIRE_GPIOLIB
 754         select CLKDEV_LOOKUP
 755         select CLKSRC_MMIO
 756         select CPU_V7
 757         select GENERIC_CLOCKEVENTS
 758         select HAVE_CLK
 759         select HAVE_S3C2410_I2C if I2C
 760         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 761         select HAVE_S3C_RTC if RTC_CLASS
 762         select NEED_MACH_GPIO_H
 763         help
 764           Samsung S5PC100 series based systems
 765
 766 config ARCH_S5PV210
 767         bool "Samsung S5PV210/S5PC110"
 768         select ARCH_HAS_CPUFREQ
 769         select ARCH_HAS_HOLES_MEMORYMODEL
 770         select ARCH_SPARSEMEM_ENABLE
 771         select CLKDEV_LOOKUP
 772         select CLKSRC_MMIO
 773         select CPU_V7
 774         select GENERIC_CLOCKEVENTS
 775         select HAVE_CLK
 776         select HAVE_S3C2410_I2C if I2C
 777         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 778         select HAVE_S3C_RTC if RTC_CLASS
 779         select NEED_MACH_GPIO_H
 780         select NEED_MACH_MEMORY_H
 781         help
 782           Samsung S5PV210/S5PC110 series based systems
 783
 784 config ARCH_EXYNOS
 785         bool "Samsung EXYNOS"
 786         select ARCH_HAS_CPUFREQ
 787         select ARCH_HAS_HOLES_MEMORYMODEL
 788         select ARCH_SPARSEMEM_ENABLE
 789         select CLKDEV_LOOKUP
 790         select COMMON_CLK
 791         select CPU_V7
 792         select GENERIC_CLOCKEVENTS
 793         select HAVE_CLK
 794         select HAVE_S3C2410_I2C if I2C
 795         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 796         select HAVE_S3C_RTC if RTC_CLASS
 797         select NEED_MACH_GPIO_H
 798         select NEED_MACH_MEMORY_H
 799         help
 800           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 801
 802 config ARCH_SHARK
 803         bool "Shark"
 804         select ARCH_USES_GETTIMEOFFSET
 805         select CPU_SA110
 806         select ISA
 807         select ISA_DMA
 808         select NEED_MACH_MEMORY_H
 809         select PCI
 810         select VIRT_TO_BUS
 811         select ZONE_DMA
 812         help
 813           Support for the StrongARM based Digital DNARD machine, also known
 814           as "Shark" (<http://www.shark-linux.de/shark.html>).
 815
 816 config ARCH_U300
 817         bool "ST-Ericsson U300 Series"
 818         depends on MMU
 819         select ARCH_REQUIRE_GPIOLIB
 820         select ARM_AMBA
 821         select ARM_PATCH_PHYS_VIRT
 822         select ARM_VIC
 823         select CLKDEV_LOOKUP
 824         select CLKSRC_MMIO
 825         select COMMON_CLK
 826         select CPU_ARM926T
 827         select GENERIC_CLOCKEVENTS
 828         select HAVE_TCM
 829         select SPARSE_IRQ
 830         help
 831           Support for ST-Ericsson U300 series mobile platforms.
 832
 833 config ARCH_DAVINCI
 834         bool "TI DaVinci"
 835         select ARCH_HAS_HOLES_MEMORYMODEL
 836         select ARCH_REQUIRE_GPIOLIB
 837         select CLKDEV_LOOKUP
 838         select GENERIC_ALLOCATOR
 839         select GENERIC_CLOCKEVENTS
 840         select GENERIC_IRQ_CHIP
 841         select HAVE_IDE
 842         select NEED_MACH_GPIO_H
 843         select USE_OF
 844         select ZONE_DMA
 845         help
 846           Support for TI's DaVinci platform.
 847
 848 config ARCH_OMAP1
 849         bool "TI OMAP1"
 850         depends on MMU
 851         select ARCH_HAS_CPUFREQ
 852         select ARCH_HAS_HOLES_MEMORYMODEL
 853         select ARCH_OMAP
 854         select ARCH_REQUIRE_GPIOLIB
 855         select CLKDEV_LOOKUP
 856         select CLKSRC_MMIO
 857         select GENERIC_CLOCKEVENTS
 858         select GENERIC_IRQ_CHIP
 859         select HAVE_CLK
 860         select HAVE_IDE
 861         select IRQ_DOMAIN
 862         select NEED_MACH_IO_H if PCCARD
 863         select NEED_MACH_MEMORY_H
 864         help
 865           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 866
 867 endchoice
 868
 869 menu "Multiple platform selection"
 870         depends on ARCH_MULTIPLATFORM
 871
 872 comment "CPU Core family selection"
 873
 874 config ARCH_MULTI_V4
 875         bool "ARMv4 based platforms (FA526, StrongARM)"
 876         depends on !ARCH_MULTI_V6_V7
 877         select ARCH_MULTI_V4_V5
 878
 879 config ARCH_MULTI_V4T
 880         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 881         depends on !ARCH_MULTI_V6_V7
 882         select ARCH_MULTI_V4_V5
 883
 884 config ARCH_MULTI_V5
 885         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 886         depends on !ARCH_MULTI_V6_V7
 887         select ARCH_MULTI_V4_V5
 888
 889 config ARCH_MULTI_V4_V5
 890         bool
 891
 892 config ARCH_MULTI_V6
 893         bool "ARMv6 based platforms (ARM11)"
 894         select ARCH_MULTI_V6_V7
 895         select CPU_V6
 896
 897 config ARCH_MULTI_V7
 898         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 899         default y
 900         select ARCH_MULTI_V6_V7
 901         select CPU_V7
 902
 903 config ARCH_MULTI_V6_V7
 904         bool
 905
 906 config ARCH_MULTI_CPU_AUTO
 907         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 908         select ARCH_MULTI_V5
 909
 910 endmenu
 911
 912 #
 913 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 914 # Kconfigs may be included either alphabetically (according to the
 915 # plat- suffix) or along side the corresponding mach-* source.
 916 #
 917 source "arch/arm/mach-mvebu/Kconfig"
 918
 919 source "arch/arm/mach-at91/Kconfig"
 920
 921 source "arch/arm/mach-bcm/Kconfig"
 922
 923 source "arch/arm/mach-bcm2835/Kconfig"
 924
 925 source "arch/arm/mach-clps711x/Kconfig"
 926
 927 source "arch/arm/mach-cns3xxx/Kconfig"
 928
 929 source "arch/arm/mach-davinci/Kconfig"
 930
 931 source "arch/arm/mach-dove/Kconfig"
 932
 933 source "arch/arm/mach-ep93xx/Kconfig"
 934
 935 source "arch/arm/mach-footbridge/Kconfig"
 936
 937 source "arch/arm/mach-gemini/Kconfig"
 938
 939 source "arch/arm/mach-highbank/Kconfig"
 940
 941 source "arch/arm/mach-integrator/Kconfig"
 942
 943 source "arch/arm/mach-iop32x/Kconfig"
 944
 945 source "arch/arm/mach-iop33x/Kconfig"
 946
 947 source "arch/arm/mach-iop13xx/Kconfig"
 948
 949 source "arch/arm/mach-ixp4xx/Kconfig"
 950
 951 source "arch/arm/mach-kirkwood/Kconfig"
 952
 953 source "arch/arm/mach-ks8695/Kconfig"
 954
 955 source "arch/arm/mach-msm/Kconfig"
 956
 957 source "arch/arm/mach-mv78xx0/Kconfig"
 958
 959 source "arch/arm/mach-imx/Kconfig"
 960
 961 source "arch/arm/mach-mxs/Kconfig"
 962
 963 source "arch/arm/mach-netx/Kconfig"
 964
 965 source "arch/arm/mach-nomadik/Kconfig"
 966
 967 source "arch/arm/plat-omap/Kconfig"
 968
 969 source "arch/arm/mach-omap1/Kconfig"
 970
 971 source "arch/arm/mach-omap2/Kconfig"
 972
 973 source "arch/arm/mach-orion5x/Kconfig"
 974
 975 source "arch/arm/mach-picoxcell/Kconfig"
 976
 977 source "arch/arm/mach-pxa/Kconfig"
 978 source "arch/arm/plat-pxa/Kconfig"
 979
 980 source "arch/arm/mach-mmp/Kconfig"
 981
 982 source "arch/arm/mach-realview/Kconfig"
 983
 984 source "arch/arm/mach-sa1100/Kconfig"
 985
 986 source "arch/arm/plat-samsung/Kconfig"
 987
 988 source "arch/arm/mach-socfpga/Kconfig"
 989
 990 source "arch/arm/mach-spear/Kconfig"
 991
 992 source "arch/arm/mach-s3c24xx/Kconfig"
 993
 994 if ARCH_S3C64XX
 995 source "arch/arm/mach-s3c64xx/Kconfig"
 996 endif
 997
 998 source "arch/arm/mach-s5p64x0/Kconfig"
 999
1000 source "arch/arm/mach-s5pc100/Kconfig"
1001
1002 source "arch/arm/mach-s5pv210/Kconfig"
1003
1004 source "arch/arm/mach-exynos/Kconfig"
1005
1006 source "arch/arm/mach-shmobile/Kconfig"
1007
1008 source "arch/arm/mach-sunxi/Kconfig"
1009
1010 source "arch/arm/mach-prima2/Kconfig"
1011
1012 source "arch/arm/mach-tegra/Kconfig"
1013
1014 source "arch/arm/mach-u300/Kconfig"
1015
1016 source "arch/arm/mach-ux500/Kconfig"
1017
1018 source "arch/arm/mach-versatile/Kconfig"
1019
1020 source "arch/arm/mach-vexpress/Kconfig"
1021 source "arch/arm/plat-versatile/Kconfig"
1022
1023 source "arch/arm/mach-virt/Kconfig"
1024
1025 source "arch/arm/mach-vt8500/Kconfig"
1026
1027 source "arch/arm/mach-w90x900/Kconfig"
1028
1029 source "arch/arm/mach-zynq/Kconfig"
1030
1031 # Definitions to make life easier
1032 config ARCH_ACORN
1033         bool
1034
1035 config PLAT_IOP
1036         bool
1037         select GENERIC_CLOCKEVENTS
1038
1039 config PLAT_ORION
1040         bool
1041         select CLKSRC_MMIO
1042         select COMMON_CLK
1043         select GENERIC_IRQ_CHIP
1044         select IRQ_DOMAIN
1045
1046 config PLAT_ORION_LEGACY
1047         bool
1048         select PLAT_ORION
1049
1050 config PLAT_PXA
1051         bool
1052
1053 config PLAT_VERSATILE
1054         bool
1055
1056 config ARM_TIMER_SP804
1057         bool
1058         select CLKSRC_MMIO
1059         select CLKSRC_OF if OF
1060
1061 source arch/arm/mm/Kconfig
1062
1063 config ARM_NR_BANKS
1064         int
1065         default 16 if ARCH_EP93XX
1066         default 8
1067
1068 config IWMMXT
1069         bool "Enable iWMMXt support" if !CPU_PJ4
1070         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1071         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1072         help
1073           Enable support for iWMMXt context switching at run time if
1074           running on a CPU that supports it.
1075
1076 config XSCALE_PMU
1077         bool
1078         depends on CPU_XSCALE
1079         default y
1080
1081 config MULTI_IRQ_HANDLER
1082         bool
1083         help
1084           Allow each machine to specify it's own IRQ handler at run time.
1085
1086 if !MMU
1087 source "arch/arm/Kconfig-nommu"
1088 endif
1089
1090 config PJ4B_ERRATA_4742
1091         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1092         depends on CPU_PJ4B && MACH_ARMADA_370
1093         default y
1094         help
1095           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1096           Event (WFE) IDLE states, a specific timing sensitivity exists between
1097           the retiring WFI/WFE instructions and the newly issued subsequent
1098           instructions.  This sensitivity can result in a CPU hang scenario.
1099           Workaround:
1100           The software must insert either a Data Synchronization Barrier (DSB)
1101           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1102           instruction
1103
1104 config ARM_ERRATA_326103
1105         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1106         depends on CPU_V6
1107         help
1108           Executing a SWP instruction to read-only memory does not set bit 11
1109           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1110           treat the access as a read, preventing a COW from occurring and
1111           causing the faulting task to livelock.
1112
1113 config ARM_ERRATA_411920
1114         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1115         depends on CPU_V6 || CPU_V6K
1116         help
1117           Invalidation of the Instruction Cache operation can
1118           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1119           It does not affect the MPCore. This option enables the ARM Ltd.
1120           recommended workaround.
1121
1122 config ARM_ERRATA_430973
1123         bool "ARM errata: Stale prediction on replaced interworking branch"
1124         depends on CPU_V7
1125         help
1126           This option enables the workaround for the 430973 Cortex-A8
1127           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1128           interworking branch is replaced with another code sequence at the
1129           same virtual address, whether due to self-modifying code or virtual
1130           to physical address re-mapping, Cortex-A8 does not recover from the
1131           stale interworking branch prediction. This results in Cortex-A8
1132           executing the new code sequence in the incorrect ARM or Thumb state.
1133           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1134           and also flushes the branch target cache at every context switch.
1135           Note that setting specific bits in the ACTLR register may not be
1136           available in non-secure mode.
1137
1138 config ARM_ERRATA_458693
1139         bool "ARM errata: Processor deadlock when a false hazard is created"
1140         depends on CPU_V7
1141         depends on !ARCH_MULTIPLATFORM
1142         help
1143           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1144           erratum. For very specific sequences of memory operations, it is
1145           possible for a hazard condition intended for a cache line to instead
1146           be incorrectly associated with a different cache line. This false
1147           hazard might then cause a processor deadlock. The workaround enables
1148           the L1 caching of the NEON accesses and disables the PLD instruction
1149           in the ACTLR register. Note that setting specific bits in the ACTLR
1150           register may not be available in non-secure mode.
1151
1152 config ARM_ERRATA_460075
1153         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1154         depends on CPU_V7
1155         depends on !ARCH_MULTIPLATFORM
1156         help
1157           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1158           erratum. Any asynchronous access to the L2 cache may encounter a
1159           situation in which recent store transactions to the L2 cache are lost
1160           and overwritten with stale memory contents from external memory. The
1161           workaround disables the write-allocate mode for the L2 cache via the
1162           ACTLR register. Note that setting specific bits in the ACTLR register
1163           may not be available in non-secure mode.
1164
1165 config ARM_ERRATA_742230
1166         bool "ARM errata: DMB operation may be faulty"
1167         depends on CPU_V7 && SMP
1168         depends on !ARCH_MULTIPLATFORM
1169         help
1170           This option enables the workaround for the 742230 Cortex-A9
1171           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1172           between two write operations may not ensure the correct visibility
1173           ordering of the two writes. This workaround sets a specific bit in
1174           the diagnostic register of the Cortex-A9 which causes the DMB
1175           instruction to behave as a DSB, ensuring the correct behaviour of
1176           the two writes.
1177
1178 config ARM_ERRATA_742231
1179         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1180         depends on CPU_V7 && SMP
1181         depends on !ARCH_MULTIPLATFORM
1182         help
1183           This option enables the workaround for the 742231 Cortex-A9
1184           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1185           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1186           accessing some data located in the same cache line, may get corrupted
1187           data due to bad handling of the address hazard when the line gets
1188           replaced from one of the CPUs at the same time as another CPU is
1189           accessing it. This workaround sets specific bits in the diagnostic
1190           register of the Cortex-A9 which reduces the linefill issuing
1191           capabilities of the processor.
1192
1193 config PL310_ERRATA_588369
1194         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1195         depends on CACHE_L2X0
1196         help
1197            The PL310 L2 cache controller implements three types of Clean &
1198            Invalidate maintenance operations: by Physical Address
1199            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1200            They are architecturally defined to behave as the execution of a
1201            clean operation followed immediately by an invalidate operation,
1202            both performing to the same memory location. This functionality
1203            is not correctly implemented in PL310 as clean lines are not
1204            invalidated as a result of these operations.
1205
1206 config ARM_ERRATA_643719
1207         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1208         depends on CPU_V7 && SMP
1209         help
1210           This option enables the workaround for the 643719 Cortex-A9 (prior to
1211           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1212           register returns zero when it should return one. The workaround
1213           corrects this value, ensuring cache maintenance operations which use
1214           it behave as intended and avoiding data corruption.
1215
1216 config ARM_ERRATA_720789
1217         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1218         depends on CPU_V7
1219         help
1220           This option enables the workaround for the 720789 Cortex-A9 (prior to
1221           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1222           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1223           As a consequence of this erratum, some TLB entries which should be
1224           invalidated are not, resulting in an incoherency in the system page
1225           tables. The workaround changes the TLB flushing routines to invalidate
1226           entries regardless of the ASID.
1227
1228 config PL310_ERRATA_727915
1229         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1230         depends on CACHE_L2X0
1231         help
1232           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1233           operation (offset 0x7FC). This operation runs in background so that
1234           PL310 can handle normal accesses while it is in progress. Under very
1235           rare circumstances, due to this erratum, write data can be lost when
1236           PL310 treats a cacheable write transaction during a Clean &
1237           Invalidate by Way operation.
1238
1239 config ARM_ERRATA_743622
1240         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1241         depends on CPU_V7
1242         depends on !ARCH_MULTIPLATFORM
1243         help
1244           This option enables the workaround for the 743622 Cortex-A9
1245           (r2p*) erratum. Under very rare conditions, a faulty
1246           optimisation in the Cortex-A9 Store Buffer may lead to data
1247           corruption. This workaround sets a specific bit in the diagnostic
1248           register of the Cortex-A9 which disables the Store Buffer
1249           optimisation, preventing the defect from occurring. This has no
1250           visible impact on the overall performance or power consumption of the
1251           processor.
1252
1253 config ARM_ERRATA_751472
1254         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1255         depends on CPU_V7
1256         depends on !ARCH_MULTIPLATFORM
1257         help
1258           This option enables the workaround for the 751472 Cortex-A9 (prior
1259           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1260           completion of a following broadcasted operation if the second
1261           operation is received by a CPU before the ICIALLUIS has completed,
1262           potentially leading to corrupted entries in the cache or TLB.
1263
1264 config PL310_ERRATA_753970
1265         bool "PL310 errata: cache sync operation may be faulty"
1266         depends on CACHE_PL310
1267         help
1268           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1269
1270           Under some condition the effect of cache sync operation on
1271           the store buffer still remains when the operation completes.
1272           This means that the store buffer is always asked to drain and
1273           this prevents it from merging any further writes. The workaround
1274           is to replace the normal offset of cache sync operation (0x730)
1275           by another offset targeting an unmapped PL310 register 0x740.
1276           This has the same effect as the cache sync operation: store buffer
1277           drain and waiting for all buffers empty.
1278
1279 config ARM_ERRATA_754322
1280         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1281         depends on CPU_V7
1282         help
1283           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1284           r3p*) erratum. A speculative memory access may cause a page table walk
1285           which starts prior to an ASID switch but completes afterwards. This
1286           can populate the micro-TLB with a stale entry which may be hit with
1287           the new ASID. This workaround places two dsb instructions in the mm
1288           switching code so that no page table walks can cross the ASID switch.
1289
1290 config ARM_ERRATA_754327
1291         bool "ARM errata: no automatic Store Buffer drain"
1292         depends on CPU_V7 && SMP
1293         help
1294           This option enables the workaround for the 754327 Cortex-A9 (prior to
1295           r2p0) erratum. The Store Buffer does not have any automatic draining
1296           mechanism and therefore a livelock may occur if an external agent
1297           continuously polls a memory location waiting to observe an update.
1298           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1299           written polling loops from denying visibility of updates to memory.
1300
1301 config ARM_ERRATA_364296
1302         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1303         depends on CPU_V6 && !SMP
1304         help
1305           This options enables the workaround for the 364296 ARM1136
1306           r0p2 erratum (possible cache data corruption with
1307           hit-under-miss enabled). It sets the undocumented bit 31 in
1308           the auxiliary control register and the FI bit in the control
1309           register, thus disabling hit-under-miss without putting the
1310           processor into full low interrupt latency mode. ARM11MPCore
1311           is not affected.
1312
1313 config ARM_ERRATA_764369
1314         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1315         depends on CPU_V7 && SMP
1316         help
1317           This option enables the workaround for erratum 764369
1318           affecting Cortex-A9 MPCore with two or more processors (all
1319           current revisions). Under certain timing circumstances, a data
1320           cache line maintenance operation by MVA targeting an Inner
1321           Shareable memory region may fail to proceed up to either the
1322           Point of Coherency or to the Point of Unification of the
1323           system. This workaround adds a DSB instruction before the
1324           relevant cache maintenance functions and sets a specific bit
1325           in the diagnostic control register of the SCU.
1326
1327 config PL310_ERRATA_769419
1328         bool "PL310 errata: no automatic Store Buffer drain"
1329         depends on CACHE_L2X0
1330         help
1331           On revisions of the PL310 prior to r3p2, the Store Buffer does
1332           not automatically drain. This can cause normal, non-cacheable
1333           writes to be retained when the memory system is idle, leading
1334           to suboptimal I/O performance for drivers using coherent DMA.
1335           This option adds a write barrier to the cpu_idle loop so that,
1336           on systems with an outer cache, the store buffer is drained
1337           explicitly.
1338
1339 config ARM_ERRATA_775420
1340        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1341        depends on CPU_V7
1342        help
1343          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1344          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1345          operation aborts with MMU exception, it might cause the processor
1346          to deadlock. This workaround puts DSB before executing ISB if
1347          an abort may occur on cache maintenance.
1348
1349 config ARM_ERRATA_798181
1350         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1351         depends on CPU_V7 && SMP
1352         help
1353           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1354           adequately shooting down all use of the old entries. This
1355           option enables the Linux kernel workaround for this erratum
1356           which sends an IPI to the CPUs that are running the same ASID
1357           as the one being invalidated.
1358
1359 endmenu
1360
1361 source "arch/arm/common/Kconfig"
1362
1363 menu "Bus support"
1364
1365 config ARM_AMBA
1366         bool
1367
1368 config ISA
1369         bool
1370         help
1371           Find out whether you have ISA slots on your motherboard.  ISA is the
1372           name of a bus system, i.e. the way the CPU talks to the other stuff
1373           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1374           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1375           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1376
1377 # Select ISA DMA controller support
1378 config ISA_DMA
1379         bool
1380         select ISA_DMA_API
1381
1382 # Select ISA DMA interface
1383 config ISA_DMA_API
1384         bool
1385
1386 config PCI
1387         bool "PCI support" if MIGHT_HAVE_PCI
1388         help
1389           Find out whether you have a PCI motherboard. PCI is the name of a
1390           bus system, i.e. the way the CPU talks to the other stuff inside
1391           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1392           VESA. If you have PCI, say Y, otherwise N.
1393
1394 config PCI_DOMAINS
1395         bool
1396         depends on PCI
1397
1398 config PCI_NANOENGINE
1399         bool "BSE nanoEngine PCI support"
1400         depends on SA1100_NANOENGINE
1401         help
1402           Enable PCI on the BSE nanoEngine board.
1403
1404 config PCI_SYSCALL
1405         def_bool PCI
1406
1407 # Select the host bridge type
1408 config PCI_HOST_VIA82C505
1409         bool
1410         depends on PCI && ARCH_SHARK
1411         default y
1412
1413 config PCI_HOST_ITE8152
1414         bool
1415         depends on PCI && MACH_ARMCORE
1416         default y
1417         select DMABOUNCE
1418
1419 source "drivers/pci/Kconfig"
1420
1421 source "drivers/pcmcia/Kconfig"
1422
1423 endmenu
1424
1425 menu "Kernel Features"
1426
1427 config HAVE_SMP
1428         bool
1429         help
1430           This option should be selected by machines which have an SMP-
1431           capable CPU.
1432
1433           The only effect of this option is to make the SMP-related
1434           options available to the user for configuration.
1435
1436 config SMP
1437         bool "Symmetric Multi-Processing"
1438         depends on CPU_V6K || CPU_V7
1439         depends on GENERIC_CLOCKEVENTS
1440         depends on HAVE_SMP
1441         depends on MMU
1442         select USE_GENERIC_SMP_HELPERS
1443         help
1444           This enables support for systems with more than one CPU. If you have
1445           a system with only one CPU, like most personal computers, say N. If
1446           you have a system with more than one CPU, say Y.
1447
1448           If you say N here, the kernel will run on single and multiprocessor
1449           machines, but will use only one CPU of a multiprocessor machine. If
1450           you say Y here, the kernel will run on many, but not all, single
1451           processor machines. On a single processor machine, the kernel will
1452           run faster if you say N here.
1453
1454           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1455           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1456           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1457
1458           If you don't know what to do here, say N.
1459
1460 config SMP_ON_UP
1461         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1462         depends on SMP && !XIP_KERNEL
1463         default y
1464         help
1465           SMP kernels contain instructions which fail on non-SMP processors.
1466           Enabling this option allows the kernel to modify itself to make
1467           these instructions safe.  Disabling it allows about 1K of space
1468           savings.
1469
1470           If you don't know what to do here, say Y.
1471
1472 config ARM_CPU_TOPOLOGY
1473         bool "Support cpu topology definition"
1474         depends on SMP && CPU_V7
1475         default y
1476         help
1477           Support ARM cpu topology definition. The MPIDR register defines
1478           affinity between processors which is then used to describe the cpu
1479           topology of an ARM System.
1480
1481 config SCHED_MC
1482         bool "Multi-core scheduler support"
1483         depends on ARM_CPU_TOPOLOGY
1484         help
1485           Multi-core scheduler support improves the CPU scheduler's decision
1486           making when dealing with multi-core CPU chips at a cost of slightly
1487           increased overhead in some places. If unsure say N here.
1488
1489 config SCHED_SMT
1490         bool "SMT scheduler support"
1491         depends on ARM_CPU_TOPOLOGY
1492         help
1493           Improves the CPU scheduler's decision making when dealing with
1494           MultiThreading at a cost of slightly increased overhead in some
1495           places. If unsure say N here.
1496
1497 config HAVE_ARM_SCU
1498         bool
1499         help
1500           This option enables support for the ARM system coherency unit
1501
1502 config HAVE_ARM_ARCH_TIMER
1503         bool "Architected timer support"
1504         depends on CPU_V7
1505         select ARM_ARCH_TIMER
1506         help
1507           This option enables support for the ARM architected timer
1508
1509 config HAVE_ARM_TWD
1510         bool
1511         depends on SMP
1512         select CLKSRC_OF if OF
1513         help
1514           This options enables support for the ARM timer and watchdog unit
1515
1516 config MCPM
1517         bool "Multi-Cluster Power Management"
1518         depends on CPU_V7 && SMP
1519         help
1520           This option provides the common power management infrastructure
1521           for (multi-)cluster based systems, such as big.LITTLE based
1522           systems.
1523
1524 choice
1525         prompt "Memory split"
1526         default VMSPLIT_3G
1527         help
1528           Select the desired split between kernel and user memory.
1529
1530           If you are not absolutely sure what you are doing, leave this
1531           option alone!
1532
1533         config VMSPLIT_3G
1534                 bool "3G/1G user/kernel split"
1535         config VMSPLIT_2G
1536                 bool "2G/2G user/kernel split"
1537         config VMSPLIT_1G
1538                 bool "1G/3G user/kernel split"
1539 endchoice
1540
1541 config PAGE_OFFSET
1542         hex
1543         default 0x40000000 if VMSPLIT_1G
1544         default 0x80000000 if VMSPLIT_2G
1545         default 0xC0000000
1546
1547 config NR_CPUS
1548         int "Maximum number of CPUs (2-32)"
1549         range 2 32
1550         depends on SMP
1551         default "4"
1552
1553 config HOTPLUG_CPU
1554         bool "Support for hot-pluggable CPUs"
1555         depends on SMP && HOTPLUG
1556         help
1557           Say Y here to experiment with turning CPUs off and on.  CPUs
1558           can be controlled through /sys/devices/system/cpu.
1559
1560 config ARM_PSCI
1561         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1562         depends on CPU_V7
1563         help
1564           Say Y here if you want Linux to communicate with system firmware
1565           implementing the PSCI specification for CPU-centric power
1566           management operations described in ARM document number ARM DEN
1567           0022A ("Power State Coordination Interface System Software on
1568           ARM processors").
1569
1570 config LOCAL_TIMERS
1571         bool "Use local timer interrupts"
1572         depends on SMP
1573         default y
1574         help
1575           Enable support for local timers on SMP platforms, rather then the
1576           legacy IPI broadcast method.  Local timers allows the system
1577           accounting to be spread across the timer interval, preventing a
1578           "thundering herd" at every timer tick.
1579
1580 # The GPIO number here must be sorted by descending number. In case of
1581 # a multiplatform kernel, we just want the highest value required by the
1582 # selected platforms.
1583 config ARCH_NR_GPIO
1584         int
1585         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1586         default 512 if SOC_OMAP5
1587         default 392 if ARCH_U8500
1588         default 352 if ARCH_VT8500
1589         default 288 if ARCH_SUNXI
1590         default 264 if MACH_H4700
1591         default 0
1592         help
1593           Maximum number of GPIOs in the system.
1594
1595           If unsure, leave the default value.
1596
1597 source kernel/Kconfig.preempt
1598
1599 config HZ
1600         int
1601         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1602                 ARCH_S5PV210 || ARCH_EXYNOS4
1603         default AT91_TIMER_HZ if ARCH_AT91
1604         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1605         default 100
1606
1607 config SCHED_HRTICK
1608         def_bool HIGH_RES_TIMERS
1609
1610 config THUMB2_KERNEL
1611         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1612         depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1613         default y if CPU_THUMBONLY
1614         select AEABI
1615         select ARM_ASM_UNIFIED
1616         select ARM_UNWIND
1617         help
1618           By enabling this option, the kernel will be compiled in
1619           Thumb-2 mode. A compiler/assembler that understand the unified
1620           ARM-Thumb syntax is needed.
1621
1622           If unsure, say N.
1623
1624 config THUMB2_AVOID_R_ARM_THM_JUMP11
1625         bool "Work around buggy Thumb-2 short branch relocations in gas"
1626         depends on THUMB2_KERNEL && MODULES
1627         default y
1628         help
1629           Various binutils versions can resolve Thumb-2 branches to
1630           locally-defined, preemptible global symbols as short-range "b.n"
1631           branch instructions.
1632
1633           This is a problem, because there's no guarantee the final
1634           destination of the symbol, or any candidate locations for a
1635           trampoline, are within range of the branch.  For this reason, the
1636           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1637           relocation in modules at all, and it makes little sense to add
1638           support.
1639
1640           The symptom is that the kernel fails with an "unsupported
1641           relocation" error when loading some modules.
1642
1643           Until fixed tools are available, passing
1644           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1645           code which hits this problem, at the cost of a bit of extra runtime
1646           stack usage in some cases.
1647
1648           The problem is described in more detail at:
1649               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1650
1651           Only Thumb-2 kernels are affected.
1652
1653           Unless you are sure your tools don't have this problem, say Y.
1654
1655 config ARM_ASM_UNIFIED
1656         bool
1657
1658 config AEABI
1659         bool "Use the ARM EABI to compile the kernel"
1660         help
1661           This option allows for the kernel to be compiled using the latest
1662           ARM ABI (aka EABI).  This is only useful if you are using a user
1663           space environment that is also compiled with EABI.
1664
1665           Since there are major incompatibilities between the legacy ABI and
1666           EABI, especially with regard to structure member alignment, this
1667           option also changes the kernel syscall calling convention to
1668           disambiguate both ABIs and allow for backward compatibility support
1669           (selected with CONFIG_OABI_COMPAT).
1670
1671           To use this you need GCC version 4.0.0 or later.
1672
1673 config OABI_COMPAT
1674         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1675         depends on AEABI && !THUMB2_KERNEL
1676         default y
1677         help
1678           This option preserves the old syscall interface along with the
1679           new (ARM EABI) one. It also provides a compatibility layer to
1680           intercept syscalls that have structure arguments which layout
1681           in memory differs between the legacy ABI and the new ARM EABI
1682           (only for non "thumb" binaries). This option adds a tiny
1683           overhead to all syscalls and produces a slightly larger kernel.
1684           If you know you'll be using only pure EABI user space then you
1685           can say N here. If this option is not selected and you attempt
1686           to execute a legacy ABI binary then the result will be
1687           UNPREDICTABLE (in fact it can be predicted that it won't work
1688           at all). If in doubt say Y.
1689
1690 config ARCH_HAS_HOLES_MEMORYMODEL
1691         bool
1692
1693 config ARCH_SPARSEMEM_ENABLE
1694         bool
1695
1696 config ARCH_SPARSEMEM_DEFAULT
1697         def_bool ARCH_SPARSEMEM_ENABLE
1698
1699 config ARCH_SELECT_MEMORY_MODEL
1700         def_bool ARCH_SPARSEMEM_ENABLE
1701
1702 config HAVE_ARCH_PFN_VALID
1703         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1704
1705 config HIGHMEM
1706         bool "High Memory Support"
1707         depends on MMU
1708         help
1709           The address space of ARM processors is only 4 Gigabytes large
1710           and it has to accommodate user address space, kernel address
1711           space as well as some memory mapped IO. That means that, if you
1712           have a large amount of physical memory and/or IO, not all of the
1713           memory can be "permanently mapped" by the kernel. The physical
1714           memory that is not permanently mapped is called "high memory".
1715
1716           Depending on the selected kernel/user memory split, minimum
1717           vmalloc space and actual amount of RAM, you may not need this
1718           option which should result in a slightly faster kernel.
1719
1720           If unsure, say n.
1721
1722 config HIGHPTE
1723         bool "Allocate 2nd-level pagetables from highmem"
1724         depends on HIGHMEM
1725
1726 config HW_PERF_EVENTS
1727         bool "Enable hardware performance counter support for perf events"
1728         depends on PERF_EVENTS
1729         default y
1730         help
1731           Enable hardware performance counter support for perf events. If
1732           disabled, perf events will use software events only.
1733
1734 source "mm/Kconfig"
1735
1736 config FORCE_MAX_ZONEORDER
1737         int "Maximum zone order" if ARCH_SHMOBILE
1738         range 11 64 if ARCH_SHMOBILE
1739         default "12" if SOC_AM33XX
1740         default "9" if SA1111
1741         default "11"
1742         help
1743           The kernel memory allocator divides physically contiguous memory
1744           blocks into "zones", where each zone is a power of two number of
1745           pages.  This option selects the largest power of two that the kernel
1746           keeps in the memory allocator.  If you need to allocate very large
1747           blocks of physically contiguous memory, then you may need to
1748           increase this value.
1749
1750           This config option is actually maximum order plus one. For example,
1751           a value of 11 means that the largest free memory block is 2^10 pages.
1752
1753 config ALIGNMENT_TRAP
1754         bool
1755         depends on CPU_CP15_MMU
1756         default y if !ARCH_EBSA110
1757         select HAVE_PROC_CPU if PROC_FS
1758         help
1759           ARM processors cannot fetch/store information which is not
1760           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1761           address divisible by 4. On 32-bit ARM processors, these non-aligned
1762           fetch/store instructions will be emulated in software if you say
1763           here, which has a severe performance impact. This is necessary for
1764           correct operation of some network protocols. With an IP-only
1765           configuration it is safe to say N, otherwise say Y.
1766
1767 config UACCESS_WITH_MEMCPY
1768         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1769         depends on MMU
1770         default y if CPU_FEROCEON
1771         help
1772           Implement faster copy_to_user and clear_user methods for CPU
1773           cores where a 8-word STM instruction give significantly higher
1774           memory write throughput than a sequence of individual 32bit stores.
1775
1776           A possible side effect is a slight increase in scheduling latency
1777           between threads sharing the same address space if they invoke
1778           such copy operations with large buffers.
1779
1780           However, if the CPU data cache is using a write-allocate mode,
1781           this option is unlikely to provide any performance gain.
1782
1783 config SECCOMP
1784         bool
1785         prompt "Enable seccomp to safely compute untrusted bytecode"
1786         ---help---
1787           This kernel feature is useful for number crunching applications
1788           that may need to compute untrusted bytecode during their
1789           execution. By using pipes or other transports made available to
1790           the process as file descriptors supporting the read/write
1791           syscalls, it's possible to isolate those applications in
1792           their own address space using seccomp. Once seccomp is
1793           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1794           and the task is only allowed to execute a few safe syscalls
1795           defined by each seccomp mode.
1796
1797 config CC_STACKPROTECTOR
1798         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1799         help
1800           This option turns on the -fstack-protector GCC feature. This
1801           feature puts, at the beginning of functions, a canary value on
1802           the stack just before the return address, and validates
1803           the value just before actually returning.  Stack based buffer
1804           overflows (that need to overwrite this return address) now also
1805           overwrite the canary, which gets detected and the attack is then
1806           neutralized via a kernel panic.
1807           This feature requires gcc version 4.2 or above.
1808
1809 config XEN_DOM0
1810         def_bool y
1811         depends on XEN
1812
1813 config XEN
1814         bool "Xen guest support on ARM (EXPERIMENTAL)"
1815         depends on ARM && AEABI && OF
1816         depends on CPU_V7 && !CPU_V6
1817         depends on !GENERIC_ATOMIC64
1818         select ARM_PSCI
1819         help
1820           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1821
1822 endmenu
1823
1824 menu "Boot options"
1825
1826 config USE_OF
1827         bool "Flattened Device Tree support"
1828         select IRQ_DOMAIN
1829         select OF
1830         select OF_EARLY_FLATTREE
1831         help
1832           Include support for flattened device tree machine descriptions.
1833
1834 config ATAGS
1835         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1836         default y
1837         help
1838           This is the traditional way of passing data to the kernel at boot
1839           time. If you are solely relying on the flattened device tree (or
1840           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1841           to remove ATAGS support from your kernel binary.  If unsure,
1842           leave this to y.
1843
1844 config DEPRECATED_PARAM_STRUCT
1845         bool "Provide old way to pass kernel parameters"
1846         depends on ATAGS
1847         help
1848           This was deprecated in 2001 and announced to live on for 5 years.
1849           Some old boot loaders still use this way.
1850
1851 # Compressed boot loader in ROM.  Yes, we really want to ask about
1852 # TEXT and BSS so we preserve their values in the config files.
1853 config ZBOOT_ROM_TEXT
1854         hex "Compressed ROM boot loader base address"
1855         default "0"
1856         help
1857           The physical address at which the ROM-able zImage is to be
1858           placed in the target.  Platforms which normally make use of
1859           ROM-able zImage formats normally set this to a suitable
1860           value in their defconfig file.
1861
1862           If ZBOOT_ROM is not enabled, this has no effect.
1863
1864 config ZBOOT_ROM_BSS
1865         hex "Compressed ROM boot loader BSS address"
1866         default "0"
1867         help
1868           The base address of an area of read/write memory in the target
1869           for the ROM-able zImage which must be available while the
1870           decompressor is running. It must be large enough to hold the
1871           entire decompressed kernel plus an additional 128 KiB.
1872           Platforms which normally make use of ROM-able zImage formats
1873           normally set this to a suitable value in their defconfig file.
1874
1875           If ZBOOT_ROM is not enabled, this has no effect.
1876
1877 config ZBOOT_ROM
1878         bool "Compressed boot loader in ROM/flash"
1879         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1880         help
1881           Say Y here if you intend to execute your compressed kernel image
1882           (zImage) directly from ROM or flash.  If unsure, say N.
1883
1884 choice
1885         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1886         depends on ZBOOT_ROM && ARCH_SH7372
1887         default ZBOOT_ROM_NONE
1888         help
1889           Include experimental SD/MMC loading code in the ROM-able zImage.
1890           With this enabled it is possible to write the ROM-able zImage
1891           kernel image to an MMC or SD card and boot the kernel straight
1892           from the reset vector. At reset the processor Mask ROM will load
1893           the first part of the ROM-able zImage which in turn loads the
1894           rest the kernel image to RAM.
1895
1896 config ZBOOT_ROM_NONE
1897         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1898         help
1899           Do not load image from SD or MMC
1900
1901 config ZBOOT_ROM_MMCIF
1902         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1903         help
1904           Load image from MMCIF hardware block.
1905
1906 config ZBOOT_ROM_SH_MOBILE_SDHI
1907         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1908         help
1909           Load image from SDHI hardware block
1910
1911 endchoice
1912
1913 config ARM_APPENDED_DTB
1914         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1915         depends on OF && !ZBOOT_ROM
1916         help
1917           With this option, the boot code will look for a device tree binary
1918           (DTB) appended to zImage
1919           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1920
1921           This is meant as a backward compatibility convenience for those
1922           systems with a bootloader that can't be upgraded to accommodate
1923           the documented boot protocol using a device tree.
1924
1925           Beware that there is very little in terms of protection against
1926           this option being confused by leftover garbage in memory that might
1927           look like a DTB header after a reboot if no actual DTB is appended
1928           to zImage.  Do not leave this option active in a production kernel
1929           if you don't intend to always append a DTB.  Proper passing of the
1930           location into r2 of a bootloader provided DTB is always preferable
1931           to this option.
1932
1933 config ARM_ATAG_DTB_COMPAT
1934         bool "Supplement the appended DTB with traditional ATAG information"
1935         depends on ARM_APPENDED_DTB
1936         help
1937           Some old bootloaders can't be updated to a DTB capable one, yet
1938           they provide ATAGs with memory configuration, the ramdisk address,
1939           the kernel cmdline string, etc.  Such information is dynamically
1940           provided by the bootloader and can't always be stored in a static
1941           DTB.  To allow a device tree enabled kernel to be used with such
1942           bootloaders, this option allows zImage to extract the information
1943           from the ATAG list and store it at run time into the appended DTB.
1944
1945 choice
1946         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1947         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1948
1949 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1950         bool "Use bootloader kernel arguments if available"
1951         help
1952           Uses the command-line options passed by the boot loader instead of
1953           the device tree bootargs property. If the boot loader doesn't provide
1954           any, the device tree bootargs property will be used.
1955
1956 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1957         bool "Extend with bootloader kernel arguments"
1958         help
1959           The command-line arguments provided by the boot loader will be
1960           appended to the the device tree bootargs property.
1961
1962 endchoice
1963
1964 config CMDLINE
1965         string "Default kernel command string"
1966         default ""
1967         help
1968           On some architectures (EBSA110 and CATS), there is currently no way
1969           for the boot loader to pass arguments to the kernel. For these
1970           architectures, you should supply some command-line options at build
1971           time by entering them here. As a minimum, you should specify the
1972           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1973
1974 choice
1975         prompt "Kernel command line type" if CMDLINE != ""
1976         default CMDLINE_FROM_BOOTLOADER
1977         depends on ATAGS
1978
1979 config CMDLINE_FROM_BOOTLOADER
1980         bool "Use bootloader kernel arguments if available"
1981         help
1982           Uses the command-line options passed by the boot loader. If
1983           the boot loader doesn't provide any, the default kernel command
1984           string provided in CMDLINE will be used.
1985
1986 config CMDLINE_EXTEND
1987         bool "Extend bootloader kernel arguments"
1988         help
1989           The command-line arguments provided by the boot loader will be
1990           appended to the default kernel command string.
1991
1992 config CMDLINE_FORCE
1993         bool "Always use the default kernel command string"
1994         help
1995           Always use the default kernel command string, even if the boot
1996           loader passes other arguments to the kernel.
1997           This is useful if you cannot or don't want to change the
1998           command-line options your boot loader passes to the kernel.
1999 endchoice
2000
2001 config XIP_KERNEL
2002         bool "Kernel Execute-In-Place from ROM"
2003         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2004         help
2005           Execute-In-Place allows the kernel to run from non-volatile storage
2006           directly addressable by the CPU, such as NOR flash. This saves RAM
2007           space since the text section of the kernel is not loaded from flash
2008           to RAM.  Read-write sections, such as the data section and stack,
2009           are still copied to RAM.  The XIP kernel is not compressed since
2010           it has to run directly from flash, so it will take more space to
2011           store it.  The flash address used to link the kernel object files,
2012           and for storing it, is configuration dependent. Therefore, if you
2013           say Y here, you must know the proper physical address where to
2014           store the kernel image depending on your own flash memory usage.
2015
2016           Also note that the make target becomes "make xipImage" rather than
2017           "make zImage" or "make Image".  The final kernel binary to put in
2018           ROM memory will be arch/arm/boot/xipImage.
2019
2020           If unsure, say N.
2021
2022 config XIP_PHYS_ADDR
2023         hex "XIP Kernel Physical Location"
2024         depends on XIP_KERNEL
2025         default "0x00080000"
2026         help
2027           This is the physical address in your flash memory the kernel will
2028           be linked for and stored to.  This address is dependent on your
2029           own flash usage.
2030
2031 config KEXEC
2032         bool "Kexec system call (EXPERIMENTAL)"
2033         depends on (!SMP || PM_SLEEP_SMP)
2034         help
2035           kexec is a system call that implements the ability to shutdown your
2036           current kernel, and to start another kernel.  It is like a reboot
2037           but it is independent of the system firmware.   And like a reboot
2038           you can start any kernel with it, not just Linux.
2039
2040           It is an ongoing process to be certain the hardware in a machine
2041           is properly shutdown, so do not be surprised if this code does not
2042           initially work for you.  It may help to enable device hotplugging
2043           support.
2044
2045 config ATAGS_PROC
2046         bool "Export atags in procfs"
2047         depends on ATAGS && KEXEC
2048         default y
2049         help
2050           Should the atags used to boot the kernel be exported in an "atags"
2051           file in procfs. Useful with kexec.
2052
2053 config CRASH_DUMP
2054         bool "Build kdump crash kernel (EXPERIMENTAL)"
2055         help
2056           Generate crash dump after being started by kexec. This should
2057           be normally only set in special crash dump kernels which are
2058           loaded in the main kernel with kexec-tools into a specially
2059           reserved region and then later executed after a crash by
2060           kdump/kexec. The crash dump kernel must be compiled to a
2061           memory address not used by the main kernel
2062
2063           For more details see Documentation/kdump/kdump.txt
2064
2065 config AUTO_ZRELADDR
2066         bool "Auto calculation of the decompressed kernel image address"
2067         depends on !ZBOOT_ROM && !ARCH_U300
2068         help
2069           ZRELADDR is the physical address where the decompressed kernel
2070           image will be placed. If AUTO_ZRELADDR is selected, the address
2071           will be determined at run-time by masking the current IP with
2072           0xf8000000. This assumes the zImage being placed in the first 128MB
2073           from start of memory.
2074
2075 endmenu
2076
2077 menu "CPU Power Management"
2078
2079 if ARCH_HAS_CPUFREQ
2080 source "drivers/cpufreq/Kconfig"
2081
2082 config CPU_FREQ_S3C
2083         bool
2084         help
2085           Internal configuration node for common cpufreq on Samsung SoC
2086
2087 config CPU_FREQ_S3C24XX
2088         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2089         depends on ARCH_S3C24XX && CPU_FREQ
2090         select CPU_FREQ_S3C
2091         help
2092           This enables the CPUfreq driver for the Samsung S3C24XX family
2093           of CPUs.
2094
2095           For details, take a look at <file:Documentation/cpu-freq>.
2096
2097           If in doubt, say N.
2098
2099 config CPU_FREQ_S3C24XX_PLL
2100         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2101         depends on CPU_FREQ_S3C24XX
2102         help
2103           Compile in support for changing the PLL frequency from the
2104           S3C24XX series CPUfreq driver. The PLL takes time to settle
2105           after a frequency change, so by default it is not enabled.
2106
2107           This also means that the PLL tables for the selected CPU(s) will
2108           be built which may increase the size of the kernel image.
2109
2110 config CPU_FREQ_S3C24XX_DEBUG
2111         bool "Debug CPUfreq Samsung driver core"
2112         depends on CPU_FREQ_S3C24XX
2113         help
2114           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2115
2116 config CPU_FREQ_S3C24XX_IODEBUG
2117         bool "Debug CPUfreq Samsung driver IO timing"
2118         depends on CPU_FREQ_S3C24XX
2119         help
2120           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2121
2122 config CPU_FREQ_S3C24XX_DEBUGFS
2123         bool "Export debugfs for CPUFreq"
2124         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2125         help
2126           Export status information via debugfs.
2127
2128 endif
2129
2130 source "drivers/cpuidle/Kconfig"
2131
2132 endmenu
2133
2134 menu "Floating point emulation"
2135
2136 comment "At least one emulation must be selected"
2137
2138 config FPE_NWFPE
2139         bool "NWFPE math emulation"
2140         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2141         ---help---
2142           Say Y to include the NWFPE floating point emulator in the kernel.
2143           This is necessary to run most binaries. Linux does not currently
2144           support floating point hardware so you need to say Y here even if
2145           your machine has an FPA or floating point co-processor podule.
2146
2147           You may say N here if you are going to load the Acorn FPEmulator
2148           early in the bootup.
2149
2150 config FPE_NWFPE_XP
2151         bool "Support extended precision"
2152         depends on FPE_NWFPE
2153         help
2154           Say Y to include 80-bit support in the kernel floating-point
2155           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2156           Note that gcc does not generate 80-bit operations by default,
2157           so in most cases this option only enlarges the size of the
2158           floating point emulator without any good reason.
2159
2160           You almost surely want to say N here.
2161
2162 config FPE_FASTFPE
2163         bool "FastFPE math emulation (EXPERIMENTAL)"
2164         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2165         ---help---
2166           Say Y here to include the FAST floating point emulator in the kernel.
2167           This is an experimental much faster emulator which now also has full
2168           precision for the mantissa.  It does not support any exceptions.
2169           It is very simple, and approximately 3-6 times faster than NWFPE.
2170
2171           It should be sufficient for most programs.  It may be not suitable
2172           for scientific calculations, but you have to check this for yourself.
2173           If you do not feel you need a faster FP emulation you should better
2174           choose NWFPE.
2175
2176 config VFP
2177         bool "VFP-format floating point maths"
2178         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2179         help
2180           Say Y to include VFP support code in the kernel. This is needed
2181           if your hardware includes a VFP unit.
2182
2183           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2184           release notes and additional status information.
2185
2186           Say N if your target does not have VFP hardware.
2187
2188 config VFPv3
2189         bool
2190         depends on VFP
2191         default y if CPU_V7
2192
2193 config NEON
2194         bool "Advanced SIMD (NEON) Extension support"
2195         depends on VFPv3 && CPU_V7
2196         help
2197           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2198           Extension.
2199
2200 endmenu
2201
2202 menu "Userspace binary formats"
2203
2204 source "fs/Kconfig.binfmt"
2205
2206 config ARTHUR
2207         tristate "RISC OS personality"
2208         depends on !AEABI
2209         help
2210           Say Y here to include the kernel code necessary if you want to run
2211           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2212           experimental; if this sounds frightening, say N and sleep in peace.
2213           You can also say M here to compile this support as a module (which
2214           will be called arthur).
2215
2216 endmenu
2217
2218 menu "Power management options"
2219
2220 source "kernel/power/Kconfig"
2221
2222 config ARCH_SUSPEND_POSSIBLE
2223         depends on !ARCH_S5PC100
2224         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2225                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2226         def_bool y
2227
2228 config ARM_CPU_SUSPEND
2229         def_bool PM_SLEEP
2230
2231 endmenu
2232
2233 source "net/Kconfig"
2234
2235 source "drivers/Kconfig"
2236
2237 source "fs/Kconfig"
2238
2239 source "arch/arm/Kconfig.debug"
2240
2241 source "security/Kconfig"
2242
2243 source "crypto/Kconfig"
2244
2245 source "lib/Kconfig"
2246
2247 source "arch/arm/kvm/Kconfig"