arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAVE_CUSTOM_GPIO_H
   5         select HAVE_AOUT
   6         select HAVE_DMA_API_DEBUG
   7         select HAVE_IDE if PCI || ISA || PCMCIA
   8         select HAVE_DMA_ATTRS
   9         select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
  10         select HAVE_MEMBLOCK
  11         select RTC_LIB
  12         select SYS_SUPPORTS_APM_EMULATION
  13         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  15         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  16         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  17         select HAVE_ARCH_KGDB
  18         select HAVE_ARCH_TRACEHOOK
  19         select HAVE_KPROBES if !XIP_KERNEL
  20         select HAVE_KRETPROBES if (HAVE_KPROBES)
  21         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  22         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  23         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  24         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  25         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  26         select HAVE_GENERIC_DMA_COHERENT
  27         select HAVE_KERNEL_GZIP
  28         select HAVE_KERNEL_LZO
  29         select HAVE_KERNEL_LZMA
  30         select HAVE_KERNEL_XZ
  31         select HAVE_IRQ_WORK
  32         select HAVE_PERF_EVENTS
  33         select PERF_USE_VMALLOC
  34         select HAVE_REGS_AND_STACK_ACCESS_API
  35         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  36         select HAVE_C_RECORDMCOUNT
  37         select HAVE_GENERIC_HARDIRQS
  38         select HARDIRQS_SW_RESEND
  39         select GENERIC_IRQ_PROBE
  40         select GENERIC_IRQ_SHOW
  41         select GENERIC_IRQ_PROBE
  42         select ARCH_WANT_IPC_PARSE_VERSION
  43         select HARDIRQS_SW_RESEND
  44         select CPU_PM if (SUSPEND || CPU_IDLE)
  45         select GENERIC_PCI_IOMAP
  46         select HAVE_BPF_JIT
  47         select GENERIC_SMP_IDLE_THREAD
  48         select KTIME_SCALAR
  49         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  50         select GENERIC_STRNCPY_FROM_USER
  51         select GENERIC_STRNLEN_USER
  52         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
  53         help
  54           The ARM series is a line of low-power-consumption RISC chip designs
  55           licensed by ARM Ltd and targeted at embedded applications and
  56           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  57           manufactured, but legacy ARM-based PC hardware remains popular in
  58           Europe.  There is an ARM Linux project with a web page at
  59           <http://www.arm.linux.org.uk/>.
  60
  61 config ARM_HAS_SG_CHAIN
  62         bool
  63
  64 config NEED_SG_DMA_LENGTH
  65         bool
  66
  67 config ARM_DMA_USE_IOMMU
  68         select NEED_SG_DMA_LENGTH
  69         select ARM_HAS_SG_CHAIN
  70         bool
  71
  72 config HAVE_PWM
  73         bool
  74
  75 config MIGHT_HAVE_PCI
  76         bool
  77
  78 config SYS_SUPPORTS_APM_EMULATION
  79         bool
  80
  81 config GENERIC_GPIO
  82         bool
  83
  84 config HAVE_TCM
  85         bool
  86         select GENERIC_ALLOCATOR
  87
  88 config HAVE_PROC_CPU
  89         bool
  90
  91 config NO_IOPORT
  92         bool
  93
  94 config EISA
  95         bool
  96         ---help---
  97           The Extended Industry Standard Architecture (EISA) bus was
  98           developed as an open alternative to the IBM MicroChannel bus.
  99
 100           The EISA bus provided some of the features of the IBM MicroChannel
 101           bus while maintaining backward compatibility with cards made for
 102           the older ISA bus.  The EISA bus saw limited use between 1988 and
 103           1995 when it was made obsolete by the PCI bus.
 104
 105           Say Y here if you are building a kernel for an EISA-based machine.
 106
 107           Otherwise, say N.
 108
 109 config SBUS
 110         bool
 111
 112 config STACKTRACE_SUPPORT
 113         bool
 114         default y
 115
 116 config HAVE_LATENCYTOP_SUPPORT
 117         bool
 118         depends on !SMP
 119         default y
 120
 121 config LOCKDEP_SUPPORT
 122         bool
 123         default y
 124
 125 config TRACE_IRQFLAGS_SUPPORT
 126         bool
 127         default y
 128
 129 config GENERIC_LOCKBREAK
 130         bool
 131         default y
 132         depends on SMP && PREEMPT
 133
 134 config RWSEM_GENERIC_SPINLOCK
 135         bool
 136         default y
 137
 138 config RWSEM_XCHGADD_ALGORITHM
 139         bool
 140
 141 config ARCH_HAS_ILOG2_U32
 142         bool
 143
 144 config ARCH_HAS_ILOG2_U64
 145         bool
 146
 147 config ARCH_HAS_CPUFREQ
 148         bool
 149         help
 150           Internal node to signify that the ARCH has CPUFREQ support
 151           and that the relevant menu configurations are displayed for
 152           it.
 153
 154 config GENERIC_HWEIGHT
 155         bool
 156         default y
 157
 158 config GENERIC_CALIBRATE_DELAY
 159         bool
 160         default y
 161
 162 config ARCH_MAY_HAVE_PC_FDC
 163         bool
 164
 165 config ZONE_DMA
 166         bool
 167
 168 config NEED_DMA_MAP_STATE
 169        def_bool y
 170
 171 config ARCH_HAS_DMA_SET_COHERENT_MASK
 172         bool
 173
 174 config GENERIC_ISA_DMA
 175         bool
 176
 177 config FIQ
 178         bool
 179
 180 config NEED_RET_TO_USER
 181         bool
 182
 183 config ARCH_MTD_XIP
 184         bool
 185
 186 config VECTORS_BASE
 187         hex
 188         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 189         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 190         default 0x00000000
 191         help
 192           The base address of exception vectors.
 193
 194 config ARM_PATCH_PHYS_VIRT
 195         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 196         default y
 197         depends on !XIP_KERNEL && MMU
 198         depends on !ARCH_REALVIEW || !SPARSEMEM
 199         help
 200           Patch phys-to-virt and virt-to-phys translation functions at
 201           boot and module load time according to the position of the
 202           kernel in system memory.
 203
 204           This can only be used with non-XIP MMU kernels where the base
 205           of physical memory is at a 16MB boundary.
 206
 207           Only disable this option if you know that you do not require
 208           this feature (eg, building a kernel for a single machine) and
 209           you need to shrink the kernel to the minimal size.
 210
 211 config NEED_MACH_IO_H
 212         bool
 213         help
 214           Select this when mach/io.h is required to provide special
 215           definitions for this platform.  The need for mach/io.h should
 216           be avoided when possible.
 217
 218 config NEED_MACH_MEMORY_H
 219         bool
 220         help
 221           Select this when mach/memory.h is required to provide special
 222           definitions for this platform.  The need for mach/memory.h should
 223           be avoided when possible.
 224
 225 config PHYS_OFFSET
 226         hex "Physical address of main memory" if MMU
 227         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 228         default DRAM_BASE if !MMU
 229         help
 230           Please provide the physical address corresponding to the
 231           location of main memory in your system.
 232
 233 config GENERIC_BUG
 234         def_bool y
 235         depends on BUG
 236
 237 source "init/Kconfig"
 238
 239 source "kernel/Kconfig.freezer"
 240
 241 menu "System Type"
 242
 243 config MMU
 244         bool "MMU-based Paged Memory Management Support"
 245         default y
 246         help
 247           Select if you want MMU-based virtualised addressing space
 248           support by paged memory management. If unsure, say 'Y'.
 249
 250 #
 251 # The "ARM system type" choice list is ordered alphabetically by option
 252 # text.  Please add new entries in the option alphabetic order.
 253 #
 254 choice
 255         prompt "ARM system type"
 256         default ARCH_VERSATILE
 257
 258 config ARCH_SOCFPGA
 259         bool "Altera SOCFPGA family"
 260         select ARCH_WANT_OPTIONAL_GPIOLIB
 261         select ARM_AMBA
 262         select ARM_GIC
 263         select CACHE_L2X0
 264         select CLKDEV_LOOKUP
 265         select COMMON_CLK
 266         select CPU_V7
 267         select DW_APB_TIMER
 268         select DW_APB_TIMER_OF
 269         select GENERIC_CLOCKEVENTS
 270         select GPIO_PL061 if GPIOLIB
 271         select HAVE_ARM_SCU
 272         select SPARSE_IRQ
 273         select USE_OF
 274         help
 275           This enables support for Altera SOCFPGA Cyclone V platform
 276
 277 config ARCH_INTEGRATOR
 278         bool "ARM Ltd. Integrator family"
 279         select ARM_AMBA
 280         select ARCH_HAS_CPUFREQ
 281         select COMMON_CLK
 282         select CLK_VERSATILE
 283         select HAVE_TCM
 284         select ICST
 285         select GENERIC_CLOCKEVENTS
 286         select PLAT_VERSATILE
 287         select PLAT_VERSATILE_FPGA_IRQ
 288         select NEED_MACH_IO_H
 289         select NEED_MACH_MEMORY_H
 290         select SPARSE_IRQ
 291         select MULTI_IRQ_HANDLER
 292         help
 293           Support for ARM's Integrator platform.
 294
 295 config ARCH_REALVIEW
 296         bool "ARM Ltd. RealView family"
 297         select ARM_AMBA
 298         select CLKDEV_LOOKUP
 299         select HAVE_MACH_CLKDEV
 300         select ICST
 301         select GENERIC_CLOCKEVENTS
 302         select ARCH_WANT_OPTIONAL_GPIOLIB
 303         select PLAT_VERSATILE
 304         select PLAT_VERSATILE_CLOCK
 305         select PLAT_VERSATILE_CLCD
 306         select ARM_TIMER_SP804
 307         select GPIO_PL061 if GPIOLIB
 308         select NEED_MACH_MEMORY_H
 309         help
 310           This enables support for ARM Ltd RealView boards.
 311
 312 config ARCH_VERSATILE
 313         bool "ARM Ltd. Versatile family"
 314         select ARM_AMBA
 315         select ARM_VIC
 316         select CLKDEV_LOOKUP
 317         select HAVE_MACH_CLKDEV
 318         select ICST
 319         select GENERIC_CLOCKEVENTS
 320         select ARCH_WANT_OPTIONAL_GPIOLIB
 321         select NEED_MACH_IO_H if PCI
 322         select PLAT_VERSATILE
 323         select PLAT_VERSATILE_CLOCK
 324         select PLAT_VERSATILE_CLCD
 325         select PLAT_VERSATILE_FPGA_IRQ
 326         select ARM_TIMER_SP804
 327         help
 328           This enables support for ARM Ltd Versatile board.
 329
 330 config ARCH_VEXPRESS
 331         bool "ARM Ltd. Versatile Express family"
 332         select ARCH_WANT_OPTIONAL_GPIOLIB
 333         select ARM_AMBA
 334         select ARM_TIMER_SP804
 335         select CLKDEV_LOOKUP
 336         select COMMON_CLK
 337         select GENERIC_CLOCKEVENTS
 338         select HAVE_CLK
 339         select HAVE_PATA_PLATFORM
 340         select ICST
 341         select NO_IOPORT
 342         select PLAT_VERSATILE
 343         select PLAT_VERSATILE_CLCD
 344         select REGULATOR_FIXED_VOLTAGE if REGULATOR
 345         help
 346           This enables support for the ARM Ltd Versatile Express boards.
 347
 348 config ARCH_AT91
 349         bool "Atmel AT91"
 350         select ARCH_REQUIRE_GPIOLIB
 351         select HAVE_CLK
 352         select CLKDEV_LOOKUP
 353         select IRQ_DOMAIN
 354         select NEED_MACH_IO_H if PCCARD
 355         help
 356           This enables support for systems based on Atmel
 357           AT91RM9200 and AT91SAM9* processors.
 358
 359 config ARCH_BCMRING
 360         bool "Broadcom BCMRING"
 361         depends on MMU
 362         select CPU_V6
 363         select ARM_AMBA
 364         select ARM_TIMER_SP804
 365         select CLKDEV_LOOKUP
 366         select GENERIC_CLOCKEVENTS
 367         select ARCH_WANT_OPTIONAL_GPIOLIB
 368         help
 369           Support for Broadcom's BCMRing platform.
 370
 371 config ARCH_HIGHBANK
 372         bool "Calxeda Highbank-based"
 373         select ARCH_WANT_OPTIONAL_GPIOLIB
 374         select ARM_AMBA
 375         select ARM_GIC
 376         select ARM_TIMER_SP804
 377         select CACHE_L2X0
 378         select CLKDEV_LOOKUP
 379         select COMMON_CLK
 380         select CPU_V7
 381         select GENERIC_CLOCKEVENTS
 382         select HAVE_ARM_SCU
 383         select HAVE_SMP
 384         select SPARSE_IRQ
 385         select USE_OF
 386         help
 387           Support for the Calxeda Highbank SoC based boards.
 388
 389 config ARCH_CLPS711X
 390         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 391         select CPU_ARM720T
 392         select ARCH_USES_GETTIMEOFFSET
 393         select NEED_MACH_MEMORY_H
 394         help
 395           Support for Cirrus Logic 711x/721x/731x based boards.
 396
 397 config ARCH_CNS3XXX
 398         bool "Cavium Networks CNS3XXX family"
 399         select CPU_V6K
 400         select GENERIC_CLOCKEVENTS
 401         select ARM_GIC
 402         select MIGHT_HAVE_CACHE_L2X0
 403         select MIGHT_HAVE_PCI
 404         select PCI_DOMAINS if PCI
 405         help
 406           Support for Cavium Networks CNS3XXX platform.
 407
 408 config ARCH_GEMINI
 409         bool "Cortina Systems Gemini"
 410         select CPU_FA526
 411         select ARCH_REQUIRE_GPIOLIB
 412         select ARCH_USES_GETTIMEOFFSET
 413         help
 414           Support for the Cortina Systems Gemini family SoCs
 415
 416 config ARCH_PRIMA2
 417         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 418         select CPU_V7
 419         select NO_IOPORT
 420         select ARCH_REQUIRE_GPIOLIB
 421         select GENERIC_CLOCKEVENTS
 422         select CLKDEV_LOOKUP
 423         select GENERIC_IRQ_CHIP
 424         select MIGHT_HAVE_CACHE_L2X0
 425         select PINCTRL
 426         select PINCTRL_SIRF
 427         select USE_OF
 428         select ZONE_DMA
 429         help
 430           Support for CSR SiRFSoC ARM Cortex A9 Platform
 431
 432 config ARCH_EBSA110
 433         bool "EBSA-110"
 434         select CPU_SA110
 435         select ISA
 436         select NO_IOPORT
 437         select ARCH_USES_GETTIMEOFFSET
 438         select NEED_MACH_IO_H
 439         select NEED_MACH_MEMORY_H
 440         help
 441           This is an evaluation board for the StrongARM processor available
 442           from Digital. It has limited hardware on-board, including an
 443           Ethernet interface, two PCMCIA sockets, two serial ports and a
 444           parallel port.
 445
 446 config ARCH_EP93XX
 447         bool "EP93xx-based"
 448         select CPU_ARM920T
 449         select ARM_AMBA
 450         select ARM_VIC
 451         select CLKDEV_LOOKUP
 452         select ARCH_REQUIRE_GPIOLIB
 453         select ARCH_HAS_HOLES_MEMORYMODEL
 454         select ARCH_USES_GETTIMEOFFSET
 455         select NEED_MACH_MEMORY_H
 456         help
 457           This enables support for the Cirrus EP93xx series of CPUs.
 458
 459 config ARCH_FOOTBRIDGE
 460         bool "FootBridge"
 461         select CPU_SA110
 462         select FOOTBRIDGE
 463         select GENERIC_CLOCKEVENTS
 464         select HAVE_IDE
 465         select NEED_MACH_IO_H
 466         select NEED_MACH_MEMORY_H
 467         help
 468           Support for systems based on the DC21285 companion chip
 469           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 470
 471 config ARCH_MXC
 472         bool "Freescale MXC/iMX-based"
 473         select GENERIC_CLOCKEVENTS
 474         select ARCH_REQUIRE_GPIOLIB
 475         select CLKDEV_LOOKUP
 476         select CLKSRC_MMIO
 477         select GENERIC_IRQ_CHIP
 478         select MULTI_IRQ_HANDLER
 479         select SPARSE_IRQ
 480         select USE_OF
 481         help
 482           Support for Freescale MXC/iMX-based family of processors
 483
 484 config ARCH_MXS
 485         bool "Freescale MXS-based"
 486         select GENERIC_CLOCKEVENTS
 487         select ARCH_REQUIRE_GPIOLIB
 488         select CLKDEV_LOOKUP
 489         select CLKSRC_MMIO
 490         select COMMON_CLK
 491         select HAVE_CLK_PREPARE
 492         select PINCTRL
 493         select USE_OF
 494         help
 495           Support for Freescale MXS-based family of processors
 496
 497 config ARCH_NETX
 498         bool "Hilscher NetX based"
 499         select CLKSRC_MMIO
 500         select CPU_ARM926T
 501         select ARM_VIC
 502         select GENERIC_CLOCKEVENTS
 503         help
 504           This enables support for systems based on the Hilscher NetX Soc
 505
 506 config ARCH_H720X
 507         bool "Hynix HMS720x-based"
 508         select CPU_ARM720T
 509         select ISA_DMA_API
 510         select ARCH_USES_GETTIMEOFFSET
 511         help
 512           This enables support for systems based on the Hynix HMS720x
 513
 514 config ARCH_IOP13XX
 515         bool "IOP13xx-based"
 516         depends on MMU
 517         select CPU_XSC3
 518         select PLAT_IOP
 519         select PCI
 520         select ARCH_SUPPORTS_MSI
 521         select VMSPLIT_1G
 522         select NEED_MACH_IO_H
 523         select NEED_MACH_MEMORY_H
 524         select NEED_RET_TO_USER
 525         help
 526           Support for Intel's IOP13XX (XScale) family of processors.
 527
 528 config ARCH_IOP32X
 529         bool "IOP32x-based"
 530         depends on MMU
 531         select CPU_XSCALE
 532         select NEED_MACH_IO_H
 533         select NEED_RET_TO_USER
 534         select PLAT_IOP
 535         select PCI
 536         select ARCH_REQUIRE_GPIOLIB
 537         help
 538           Support for Intel's 80219 and IOP32X (XScale) family of
 539           processors.
 540
 541 config ARCH_IOP33X
 542         bool "IOP33x-based"
 543         depends on MMU
 544         select CPU_XSCALE
 545         select NEED_MACH_IO_H
 546         select NEED_RET_TO_USER
 547         select PLAT_IOP
 548         select PCI
 549         select ARCH_REQUIRE_GPIOLIB
 550         help
 551           Support for Intel's IOP33X (XScale) family of processors.
 552
 553 config ARCH_IXP4XX
 554         bool "IXP4xx-based"
 555         depends on MMU
 556         select ARCH_HAS_DMA_SET_COHERENT_MASK
 557         select CLKSRC_MMIO
 558         select CPU_XSCALE
 559         select ARCH_REQUIRE_GPIOLIB
 560         select GENERIC_CLOCKEVENTS
 561         select MIGHT_HAVE_PCI
 562         select NEED_MACH_IO_H
 563         select DMABOUNCE if PCI
 564         help
 565           Support for Intel's IXP4XX (XScale) family of processors.
 566
 567 config ARCH_MVEBU
 568         bool "Marvell SOCs with Device Tree support"
 569         select GENERIC_CLOCKEVENTS
 570         select MULTI_IRQ_HANDLER
 571         select SPARSE_IRQ
 572         select CLKSRC_MMIO
 573         select GENERIC_IRQ_CHIP
 574         select IRQ_DOMAIN
 575         select COMMON_CLK
 576         help
 577           Support for the Marvell SoC Family with device tree support
 578
 579 config ARCH_DOVE
 580         bool "Marvell Dove"
 581         select CPU_V7
 582         select PCI
 583         select ARCH_REQUIRE_GPIOLIB
 584         select GENERIC_CLOCKEVENTS
 585         select NEED_MACH_IO_H
 586         select PLAT_ORION
 587         help
 588           Support for the Marvell Dove SoC 88AP510
 589
 590 config ARCH_KIRKWOOD
 591         bool "Marvell Kirkwood"
 592         select CPU_FEROCEON
 593         select PCI
 594         select ARCH_REQUIRE_GPIOLIB
 595         select GENERIC_CLOCKEVENTS
 596         select NEED_MACH_IO_H
 597         select PLAT_ORION
 598         help
 599           Support for the following Marvell Kirkwood series SoCs:
 600           88F6180, 88F6192 and 88F6281.
 601
 602 config ARCH_LPC32XX
 603         bool "NXP LPC32XX"
 604         select CLKSRC_MMIO
 605         select CPU_ARM926T
 606         select ARCH_REQUIRE_GPIOLIB
 607         select HAVE_IDE
 608         select ARM_AMBA
 609         select USB_ARCH_HAS_OHCI
 610         select CLKDEV_LOOKUP
 611         select GENERIC_CLOCKEVENTS
 612         select USE_OF
 613         select HAVE_PWM
 614         help
 615           Support for the NXP LPC32XX family of processors
 616
 617 config ARCH_MV78XX0
 618         bool "Marvell MV78xx0"
 619         select CPU_FEROCEON
 620         select PCI
 621         select ARCH_REQUIRE_GPIOLIB
 622         select GENERIC_CLOCKEVENTS
 623         select NEED_MACH_IO_H
 624         select PLAT_ORION
 625         help
 626           Support for the following Marvell MV78xx0 series SoCs:
 627           MV781x0, MV782x0.
 628
 629 config ARCH_ORION5X
 630         bool "Marvell Orion"
 631         depends on MMU
 632         select CPU_FEROCEON
 633         select PCI
 634         select ARCH_REQUIRE_GPIOLIB
 635         select GENERIC_CLOCKEVENTS
 636         select NEED_MACH_IO_H
 637         select PLAT_ORION
 638         help
 639           Support for the following Marvell Orion 5x series SoCs:
 640           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 641           Orion-2 (5281), Orion-1-90 (6183).
 642
 643 config ARCH_MMP
 644         bool "Marvell PXA168/910/MMP2"
 645         depends on MMU
 646         select ARCH_REQUIRE_GPIOLIB
 647         select CLKDEV_LOOKUP
 648         select GENERIC_CLOCKEVENTS
 649         select GPIO_PXA
 650         select IRQ_DOMAIN
 651         select PLAT_PXA
 652         select SPARSE_IRQ
 653         select GENERIC_ALLOCATOR
 654         help
 655           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 656
 657 config ARCH_KS8695
 658         bool "Micrel/Kendin KS8695"
 659         select CPU_ARM922T
 660         select ARCH_REQUIRE_GPIOLIB
 661         select ARCH_USES_GETTIMEOFFSET
 662         select NEED_MACH_MEMORY_H
 663         help
 664           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 665           System-on-Chip devices.
 666
 667 config ARCH_W90X900
 668         bool "Nuvoton W90X900 CPU"
 669         select CPU_ARM926T
 670         select ARCH_REQUIRE_GPIOLIB
 671         select CLKDEV_LOOKUP
 672         select CLKSRC_MMIO
 673         select GENERIC_CLOCKEVENTS
 674         help
 675           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 676           At present, the w90x900 has been renamed nuc900, regarding
 677           the ARM series product line, you can login the following
 678           link address to know more.
 679
 680           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 681                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 682
 683 config ARCH_TEGRA
 684         bool "NVIDIA Tegra"
 685         select CLKDEV_LOOKUP
 686         select CLKSRC_MMIO
 687         select GENERIC_CLOCKEVENTS
 688         select GENERIC_GPIO
 689         select HAVE_CLK
 690         select HAVE_SMP
 691         select MIGHT_HAVE_CACHE_L2X0
 692         select NEED_MACH_IO_H if PCI
 693         select ARCH_HAS_CPUFREQ
 694         select USE_OF
 695         help
 696           This enables support for NVIDIA Tegra based systems (Tegra APX,
 697           Tegra 6xx and Tegra 2 series).
 698
 699 config ARCH_PICOXCELL
 700         bool "Picochip picoXcell"
 701         select ARCH_REQUIRE_GPIOLIB
 702         select ARM_PATCH_PHYS_VIRT
 703         select ARM_VIC
 704         select CPU_V6K
 705         select DW_APB_TIMER
 706         select DW_APB_TIMER_OF
 707         select GENERIC_CLOCKEVENTS
 708         select GENERIC_GPIO
 709         select HAVE_TCM
 710         select NO_IOPORT
 711         select SPARSE_IRQ
 712         select USE_OF
 713         help
 714           This enables support for systems based on the Picochip picoXcell
 715           family of Femtocell devices.  The picoxcell support requires device tree
 716           for all boards.
 717
 718 config ARCH_PNX4008
 719         bool "Philips Nexperia PNX4008 Mobile"
 720         select CPU_ARM926T
 721         select CLKDEV_LOOKUP
 722         select ARCH_USES_GETTIMEOFFSET
 723         help
 724           This enables support for Philips PNX4008 mobile platform.
 725
 726 config ARCH_PXA
 727         bool "PXA2xx/PXA3xx-based"
 728         depends on MMU
 729         select ARCH_MTD_XIP
 730         select ARCH_HAS_CPUFREQ
 731         select CLKDEV_LOOKUP
 732         select CLKSRC_MMIO
 733         select ARCH_REQUIRE_GPIOLIB
 734         select GENERIC_CLOCKEVENTS
 735         select GPIO_PXA
 736         select PLAT_PXA
 737         select SPARSE_IRQ
 738         select AUTO_ZRELADDR
 739         select MULTI_IRQ_HANDLER
 740         select ARM_CPU_SUSPEND if PM
 741         select HAVE_IDE
 742         help
 743           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 744
 745 config ARCH_MSM
 746         bool "Qualcomm MSM"
 747         select HAVE_CLK
 748         select GENERIC_CLOCKEVENTS
 749         select ARCH_REQUIRE_GPIOLIB
 750         select CLKDEV_LOOKUP
 751         help
 752           Support for Qualcomm MSM/QSD based systems.  This runs on the
 753           apps processor of the MSM/QSD and depends on a shared memory
 754           interface to the modem processor which runs the baseband
 755           stack and controls some vital subsystems
 756           (clock and power control, etc).
 757
 758 config ARCH_SHMOBILE
 759         bool "Renesas SH-Mobile / R-Mobile"
 760         select HAVE_CLK
 761         select CLKDEV_LOOKUP
 762         select HAVE_MACH_CLKDEV
 763         select HAVE_SMP
 764         select GENERIC_CLOCKEVENTS
 765         select MIGHT_HAVE_CACHE_L2X0
 766         select NO_IOPORT
 767         select SPARSE_IRQ
 768         select MULTI_IRQ_HANDLER
 769         select PM_GENERIC_DOMAINS if PM
 770         select NEED_MACH_MEMORY_H
 771         help
 772           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 773
 774 config ARCH_RPC
 775         bool "RiscPC"
 776         select ARCH_ACORN
 777         select FIQ
 778         select ARCH_MAY_HAVE_PC_FDC
 779         select HAVE_PATA_PLATFORM
 780         select ISA_DMA_API
 781         select NO_IOPORT
 782         select ARCH_SPARSEMEM_ENABLE
 783         select ARCH_USES_GETTIMEOFFSET
 784         select HAVE_IDE
 785         select NEED_MACH_IO_H
 786         select NEED_MACH_MEMORY_H
 787         help
 788           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 789           CD-ROM interface, serial and parallel port, and the floppy drive.
 790
 791 config ARCH_SA1100
 792         bool "SA1100-based"
 793         select CLKSRC_MMIO
 794         select CPU_SA1100
 795         select ISA
 796         select ARCH_SPARSEMEM_ENABLE
 797         select ARCH_MTD_XIP
 798         select ARCH_HAS_CPUFREQ
 799         select CPU_FREQ
 800         select GENERIC_CLOCKEVENTS
 801         select CLKDEV_LOOKUP
 802         select ARCH_REQUIRE_GPIOLIB
 803         select HAVE_IDE
 804         select NEED_MACH_MEMORY_H
 805         select SPARSE_IRQ
 806         help
 807           Support for StrongARM 11x0 based boards.
 808
 809 config ARCH_S3C24XX
 810         bool "Samsung S3C24XX SoCs"
 811         select GENERIC_GPIO
 812         select ARCH_HAS_CPUFREQ
 813         select HAVE_CLK
 814         select CLKDEV_LOOKUP
 815         select ARCH_USES_GETTIMEOFFSET
 816         select HAVE_S3C2410_I2C if I2C
 817         select HAVE_S3C_RTC if RTC_CLASS
 818         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 819         select NEED_MACH_IO_H
 820         help
 821           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 822           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 823           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 824           Samsung SMDK2410 development board (and derivatives).
 825
 826 config ARCH_S3C64XX
 827         bool "Samsung S3C64XX"
 828         select PLAT_SAMSUNG
 829         select CPU_V6
 830         select ARM_VIC
 831         select HAVE_CLK
 832         select HAVE_TCM
 833         select CLKDEV_LOOKUP
 834         select NO_IOPORT
 835         select ARCH_USES_GETTIMEOFFSET
 836         select ARCH_HAS_CPUFREQ
 837         select ARCH_REQUIRE_GPIOLIB
 838         select SAMSUNG_CLKSRC
 839         select SAMSUNG_IRQ_VIC_TIMER
 840         select S3C_GPIO_TRACK
 841         select S3C_DEV_NAND
 842         select USB_ARCH_HAS_OHCI
 843         select SAMSUNG_GPIOLIB_4BIT
 844         select HAVE_S3C2410_I2C if I2C
 845         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 846         help
 847           Samsung S3C64XX series based systems
 848
 849 config ARCH_S5P64X0
 850         bool "Samsung S5P6440 S5P6450"
 851         select CPU_V6
 852         select GENERIC_GPIO
 853         select HAVE_CLK
 854         select CLKDEV_LOOKUP
 855         select CLKSRC_MMIO
 856         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 857         select GENERIC_CLOCKEVENTS
 858         select HAVE_S3C2410_I2C if I2C
 859         select HAVE_S3C_RTC if RTC_CLASS
 860         help
 861           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 862           SMDK6450.
 863
 864 config ARCH_S5PC100
 865         bool "Samsung S5PC100"
 866         select GENERIC_GPIO
 867         select HAVE_CLK
 868         select CLKDEV_LOOKUP
 869         select CPU_V7
 870         select ARCH_USES_GETTIMEOFFSET
 871         select HAVE_S3C2410_I2C if I2C
 872         select HAVE_S3C_RTC if RTC_CLASS
 873         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 874         help
 875           Samsung S5PC100 series based systems
 876
 877 config ARCH_S5PV210
 878         bool "Samsung S5PV210/S5PC110"
 879         select CPU_V7
 880         select ARCH_SPARSEMEM_ENABLE
 881         select ARCH_HAS_HOLES_MEMORYMODEL
 882         select GENERIC_GPIO
 883         select HAVE_CLK
 884         select CLKDEV_LOOKUP
 885         select CLKSRC_MMIO
 886         select ARCH_HAS_CPUFREQ
 887         select GENERIC_CLOCKEVENTS
 888         select HAVE_S3C2410_I2C if I2C
 889         select HAVE_S3C_RTC if RTC_CLASS
 890         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 891         select NEED_MACH_MEMORY_H
 892         help
 893           Samsung S5PV210/S5PC110 series based systems
 894
 895 config ARCH_EXYNOS
 896         bool "SAMSUNG EXYNOS"
 897         select CPU_V7
 898         select ARCH_SPARSEMEM_ENABLE
 899         select ARCH_HAS_HOLES_MEMORYMODEL
 900         select GENERIC_GPIO
 901         select HAVE_CLK
 902         select CLKDEV_LOOKUP
 903         select ARCH_HAS_CPUFREQ
 904         select GENERIC_CLOCKEVENTS
 905         select HAVE_S3C_RTC if RTC_CLASS
 906         select HAVE_S3C2410_I2C if I2C
 907         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 908         select NEED_MACH_MEMORY_H
 909         help
 910           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 911
 912 config ARCH_SHARK
 913         bool "Shark"
 914         select CPU_SA110
 915         select ISA
 916         select ISA_DMA
 917         select ZONE_DMA
 918         select PCI
 919         select ARCH_USES_GETTIMEOFFSET
 920         select NEED_MACH_MEMORY_H
 921         select NEED_MACH_IO_H
 922         help
 923           Support for the StrongARM based Digital DNARD machine, also known
 924           as "Shark" (<http://www.shark-linux.de/shark.html>).
 925
 926 config ARCH_U300
 927         bool "ST-Ericsson U300 Series"
 928         depends on MMU
 929         select CLKSRC_MMIO
 930         select CPU_ARM926T
 931         select HAVE_TCM
 932         select ARM_AMBA
 933         select ARM_PATCH_PHYS_VIRT
 934         select ARM_VIC
 935         select GENERIC_CLOCKEVENTS
 936         select CLKDEV_LOOKUP
 937         select COMMON_CLK
 938         select GENERIC_GPIO
 939         select ARCH_REQUIRE_GPIOLIB
 940         help
 941           Support for ST-Ericsson U300 series mobile platforms.
 942
 943 config ARCH_U8500
 944         bool "ST-Ericsson U8500 Series"
 945         depends on MMU
 946         select CPU_V7
 947         select ARM_AMBA
 948         select GENERIC_CLOCKEVENTS
 949         select CLKDEV_LOOKUP
 950         select ARCH_REQUIRE_GPIOLIB
 951         select ARCH_HAS_CPUFREQ
 952         select HAVE_SMP
 953         select MIGHT_HAVE_CACHE_L2X0
 954         help
 955           Support for ST-Ericsson's Ux500 architecture
 956
 957 config ARCH_NOMADIK
 958         bool "STMicroelectronics Nomadik"
 959         select ARM_AMBA
 960         select ARM_VIC
 961         select CPU_ARM926T
 962         select COMMON_CLK
 963         select GENERIC_CLOCKEVENTS
 964         select PINCTRL
 965         select MIGHT_HAVE_CACHE_L2X0
 966         select ARCH_REQUIRE_GPIOLIB
 967         help
 968           Support for the Nomadik platform by ST-Ericsson
 969
 970 config ARCH_DAVINCI
 971         bool "TI DaVinci"
 972         select GENERIC_CLOCKEVENTS
 973         select ARCH_REQUIRE_GPIOLIB
 974         select ZONE_DMA
 975         select HAVE_IDE
 976         select CLKDEV_LOOKUP
 977         select GENERIC_ALLOCATOR
 978         select GENERIC_IRQ_CHIP
 979         select ARCH_HAS_HOLES_MEMORYMODEL
 980         help
 981           Support for TI's DaVinci platform.
 982
 983 config ARCH_OMAP
 984         bool "TI OMAP"
 985         depends on MMU
 986         select HAVE_CLK
 987         select ARCH_REQUIRE_GPIOLIB
 988         select ARCH_HAS_CPUFREQ
 989         select CLKSRC_MMIO
 990         select GENERIC_CLOCKEVENTS
 991         select ARCH_HAS_HOLES_MEMORYMODEL
 992         help
 993           Support for TI's OMAP platform (OMAP1/2/3/4).
 994
 995 config PLAT_SPEAR
 996         bool "ST SPEAr"
 997         select ARM_AMBA
 998         select ARCH_REQUIRE_GPIOLIB
 999         select CLKDEV_LOOKUP
1000         select COMMON_CLK
1001         select CLKSRC_MMIO
1002         select GENERIC_CLOCKEVENTS
1003         select HAVE_CLK
1004         help
1005           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1006
1007 config ARCH_VT8500
1008         bool "VIA/WonderMedia 85xx"
1009         select CPU_ARM926T
1010         select GENERIC_GPIO
1011         select ARCH_HAS_CPUFREQ
1012         select GENERIC_CLOCKEVENTS
1013         select ARCH_REQUIRE_GPIOLIB
1014         help
1015           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1016
1017 config ARCH_ZYNQ
1018         bool "Xilinx Zynq ARM Cortex A9 Platform"
1019         select CPU_V7
1020         select GENERIC_CLOCKEVENTS
1021         select CLKDEV_LOOKUP
1022         select ARM_GIC
1023         select ARM_AMBA
1024         select ICST
1025         select MIGHT_HAVE_CACHE_L2X0
1026         select USE_OF
1027         help
1028           Support for Xilinx Zynq ARM Cortex A9 Platform
1029 endchoice
1030
1031 #
1032 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1033 # Kconfigs may be included either alphabetically (according to the
1034 # plat- suffix) or along side the corresponding mach-* source.
1035 #
1036 source "arch/arm/mach-mvebu/Kconfig"
1037
1038 source "arch/arm/mach-at91/Kconfig"
1039
1040 source "arch/arm/mach-bcmring/Kconfig"
1041
1042 source "arch/arm/mach-clps711x/Kconfig"
1043
1044 source "arch/arm/mach-cns3xxx/Kconfig"
1045
1046 source "arch/arm/mach-davinci/Kconfig"
1047
1048 source "arch/arm/mach-dove/Kconfig"
1049
1050 source "arch/arm/mach-ep93xx/Kconfig"
1051
1052 source "arch/arm/mach-footbridge/Kconfig"
1053
1054 source "arch/arm/mach-gemini/Kconfig"
1055
1056 source "arch/arm/mach-h720x/Kconfig"
1057
1058 source "arch/arm/mach-integrator/Kconfig"
1059
1060 source "arch/arm/mach-iop32x/Kconfig"
1061
1062 source "arch/arm/mach-iop33x/Kconfig"
1063
1064 source "arch/arm/mach-iop13xx/Kconfig"
1065
1066 source "arch/arm/mach-ixp4xx/Kconfig"
1067
1068 source "arch/arm/mach-kirkwood/Kconfig"
1069
1070 source "arch/arm/mach-ks8695/Kconfig"
1071
1072 source "arch/arm/mach-msm/Kconfig"
1073
1074 source "arch/arm/mach-mv78xx0/Kconfig"
1075
1076 source "arch/arm/plat-mxc/Kconfig"
1077
1078 source "arch/arm/mach-mxs/Kconfig"
1079
1080 source "arch/arm/mach-netx/Kconfig"
1081
1082 source "arch/arm/mach-nomadik/Kconfig"
1083 source "arch/arm/plat-nomadik/Kconfig"
1084
1085 source "arch/arm/plat-omap/Kconfig"
1086
1087 source "arch/arm/mach-omap1/Kconfig"
1088
1089 source "arch/arm/mach-omap2/Kconfig"
1090
1091 source "arch/arm/mach-orion5x/Kconfig"
1092
1093 source "arch/arm/mach-pxa/Kconfig"
1094 source "arch/arm/plat-pxa/Kconfig"
1095
1096 source "arch/arm/mach-mmp/Kconfig"
1097
1098 source "arch/arm/mach-realview/Kconfig"
1099
1100 source "arch/arm/mach-sa1100/Kconfig"
1101
1102 source "arch/arm/plat-samsung/Kconfig"
1103 source "arch/arm/plat-s3c24xx/Kconfig"
1104
1105 source "arch/arm/plat-spear/Kconfig"
1106
1107 source "arch/arm/mach-s3c24xx/Kconfig"
1108 if ARCH_S3C24XX
1109 source "arch/arm/mach-s3c2412/Kconfig"
1110 source "arch/arm/mach-s3c2440/Kconfig"
1111 endif
1112
1113 if ARCH_S3C64XX
1114 source "arch/arm/mach-s3c64xx/Kconfig"
1115 endif
1116
1117 source "arch/arm/mach-s5p64x0/Kconfig"
1118
1119 source "arch/arm/mach-s5pc100/Kconfig"
1120
1121 source "arch/arm/mach-s5pv210/Kconfig"
1122
1123 source "arch/arm/mach-exynos/Kconfig"
1124
1125 source "arch/arm/mach-shmobile/Kconfig"
1126
1127 source "arch/arm/mach-tegra/Kconfig"
1128
1129 source "arch/arm/mach-u300/Kconfig"
1130
1131 source "arch/arm/mach-ux500/Kconfig"
1132
1133 source "arch/arm/mach-versatile/Kconfig"
1134
1135 source "arch/arm/mach-vexpress/Kconfig"
1136 source "arch/arm/plat-versatile/Kconfig"
1137
1138 source "arch/arm/mach-vt8500/Kconfig"
1139
1140 source "arch/arm/mach-w90x900/Kconfig"
1141
1142 # Definitions to make life easier
1143 config ARCH_ACORN
1144         bool
1145
1146 config PLAT_IOP
1147         bool
1148         select GENERIC_CLOCKEVENTS
1149
1150 config PLAT_ORION
1151         bool
1152         select CLKSRC_MMIO
1153         select GENERIC_IRQ_CHIP
1154         select IRQ_DOMAIN
1155         select COMMON_CLK
1156
1157 config PLAT_PXA
1158         bool
1159
1160 config PLAT_VERSATILE
1161         bool
1162
1163 config ARM_TIMER_SP804
1164         bool
1165         select CLKSRC_MMIO
1166         select HAVE_SCHED_CLOCK
1167
1168 source arch/arm/mm/Kconfig
1169
1170 config ARM_NR_BANKS
1171         int
1172         default 16 if ARCH_EP93XX
1173         default 8
1174
1175 config IWMMXT
1176         bool "Enable iWMMXt support"
1177         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1178         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1179         help
1180           Enable support for iWMMXt context switching at run time if
1181           running on a CPU that supports it.
1182
1183 config XSCALE_PMU
1184         bool
1185         depends on CPU_XSCALE
1186         default y
1187
1188 config CPU_HAS_PMU
1189         depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1190                    (!ARCH_OMAP3 || OMAP3_EMU)
1191         default y
1192         bool
1193
1194 config MULTI_IRQ_HANDLER
1195         bool
1196         help
1197           Allow each machine to specify it's own IRQ handler at run time.
1198
1199 if !MMU
1200 source "arch/arm/Kconfig-nommu"
1201 endif
1202
1203 config ARM_ERRATA_326103
1204         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1205         depends on CPU_V6
1206         help
1207           Executing a SWP instruction to read-only memory does not set bit 11
1208           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1209           treat the access as a read, preventing a COW from occurring and
1210           causing the faulting task to livelock.
1211
1212 config ARM_ERRATA_411920
1213         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1214         depends on CPU_V6 || CPU_V6K
1215         help
1216           Invalidation of the Instruction Cache operation can
1217           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1218           It does not affect the MPCore. This option enables the ARM Ltd.
1219           recommended workaround.
1220
1221 config ARM_ERRATA_430973
1222         bool "ARM errata: Stale prediction on replaced interworking branch"
1223         depends on CPU_V7
1224         help
1225           This option enables the workaround for the 430973 Cortex-A8
1226           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1227           interworking branch is replaced with another code sequence at the
1228           same virtual address, whether due to self-modifying code or virtual
1229           to physical address re-mapping, Cortex-A8 does not recover from the
1230           stale interworking branch prediction. This results in Cortex-A8
1231           executing the new code sequence in the incorrect ARM or Thumb state.
1232           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1233           and also flushes the branch target cache at every context switch.
1234           Note that setting specific bits in the ACTLR register may not be
1235           available in non-secure mode.
1236
1237 config ARM_ERRATA_458693
1238         bool "ARM errata: Processor deadlock when a false hazard is created"
1239         depends on CPU_V7
1240         help
1241           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1242           erratum. For very specific sequences of memory operations, it is
1243           possible for a hazard condition intended for a cache line to instead
1244           be incorrectly associated with a different cache line. This false
1245           hazard might then cause a processor deadlock. The workaround enables
1246           the L1 caching of the NEON accesses and disables the PLD instruction
1247           in the ACTLR register. Note that setting specific bits in the ACTLR
1248           register may not be available in non-secure mode.
1249
1250 config ARM_ERRATA_460075
1251         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1252         depends on CPU_V7
1253         help
1254           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1255           erratum. Any asynchronous access to the L2 cache may encounter a
1256           situation in which recent store transactions to the L2 cache are lost
1257           and overwritten with stale memory contents from external memory. The
1258           workaround disables the write-allocate mode for the L2 cache via the
1259           ACTLR register. Note that setting specific bits in the ACTLR register
1260           may not be available in non-secure mode.
1261
1262 config ARM_ERRATA_742230
1263         bool "ARM errata: DMB operation may be faulty"
1264         depends on CPU_V7 && SMP
1265         help
1266           This option enables the workaround for the 742230 Cortex-A9
1267           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1268           between two write operations may not ensure the correct visibility
1269           ordering of the two writes. This workaround sets a specific bit in
1270           the diagnostic register of the Cortex-A9 which causes the DMB
1271           instruction to behave as a DSB, ensuring the correct behaviour of
1272           the two writes.
1273
1274 config ARM_ERRATA_742231
1275         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1276         depends on CPU_V7 && SMP
1277         help
1278           This option enables the workaround for the 742231 Cortex-A9
1279           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1280           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1281           accessing some data located in the same cache line, may get corrupted
1282           data due to bad handling of the address hazard when the line gets
1283           replaced from one of the CPUs at the same time as another CPU is
1284           accessing it. This workaround sets specific bits in the diagnostic
1285           register of the Cortex-A9 which reduces the linefill issuing
1286           capabilities of the processor.
1287
1288 config PL310_ERRATA_588369
1289         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1290         depends on CACHE_L2X0
1291         help
1292            The PL310 L2 cache controller implements three types of Clean &
1293            Invalidate maintenance operations: by Physical Address
1294            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1295            They are architecturally defined to behave as the execution of a
1296            clean operation followed immediately by an invalidate operation,
1297            both performing to the same memory location. This functionality
1298            is not correctly implemented in PL310 as clean lines are not
1299            invalidated as a result of these operations.
1300
1301 config ARM_ERRATA_720789
1302         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1303         depends on CPU_V7
1304         help
1305           This option enables the workaround for the 720789 Cortex-A9 (prior to
1306           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1307           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1308           As a consequence of this erratum, some TLB entries which should be
1309           invalidated are not, resulting in an incoherency in the system page
1310           tables. The workaround changes the TLB flushing routines to invalidate
1311           entries regardless of the ASID.
1312
1313 config PL310_ERRATA_727915
1314         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1315         depends on CACHE_L2X0
1316         help
1317           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1318           operation (offset 0x7FC). This operation runs in background so that
1319           PL310 can handle normal accesses while it is in progress. Under very
1320           rare circumstances, due to this erratum, write data can be lost when
1321           PL310 treats a cacheable write transaction during a Clean &
1322           Invalidate by Way operation.
1323
1324 config ARM_ERRATA_743622
1325         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1326         depends on CPU_V7
1327         help
1328           This option enables the workaround for the 743622 Cortex-A9
1329           (r2p*) erratum. Under very rare conditions, a faulty
1330           optimisation in the Cortex-A9 Store Buffer may lead to data
1331           corruption. This workaround sets a specific bit in the diagnostic
1332           register of the Cortex-A9 which disables the Store Buffer
1333           optimisation, preventing the defect from occurring. This has no
1334           visible impact on the overall performance or power consumption of the
1335           processor.
1336
1337 config ARM_ERRATA_751472
1338         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1339         depends on CPU_V7
1340         help
1341           This option enables the workaround for the 751472 Cortex-A9 (prior
1342           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1343           completion of a following broadcasted operation if the second
1344           operation is received by a CPU before the ICIALLUIS has completed,
1345           potentially leading to corrupted entries in the cache or TLB.
1346
1347 config PL310_ERRATA_753970
1348         bool "PL310 errata: cache sync operation may be faulty"
1349         depends on CACHE_PL310
1350         help
1351           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1352
1353           Under some condition the effect of cache sync operation on
1354           the store buffer still remains when the operation completes.
1355           This means that the store buffer is always asked to drain and
1356           this prevents it from merging any further writes. The workaround
1357           is to replace the normal offset of cache sync operation (0x730)
1358           by another offset targeting an unmapped PL310 register 0x740.
1359           This has the same effect as the cache sync operation: store buffer
1360           drain and waiting for all buffers empty.
1361
1362 config ARM_ERRATA_754322
1363         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1364         depends on CPU_V7
1365         help
1366           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1367           r3p*) erratum. A speculative memory access may cause a page table walk
1368           which starts prior to an ASID switch but completes afterwards. This
1369           can populate the micro-TLB with a stale entry which may be hit with
1370           the new ASID. This workaround places two dsb instructions in the mm
1371           switching code so that no page table walks can cross the ASID switch.
1372
1373 config ARM_ERRATA_754327
1374         bool "ARM errata: no automatic Store Buffer drain"
1375         depends on CPU_V7 && SMP
1376         help
1377           This option enables the workaround for the 754327 Cortex-A9 (prior to
1378           r2p0) erratum. The Store Buffer does not have any automatic draining
1379           mechanism and therefore a livelock may occur if an external agent
1380           continuously polls a memory location waiting to observe an update.
1381           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1382           written polling loops from denying visibility of updates to memory.
1383
1384 config ARM_ERRATA_364296
1385         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1386         depends on CPU_V6 && !SMP
1387         help
1388           This options enables the workaround for the 364296 ARM1136
1389           r0p2 erratum (possible cache data corruption with
1390           hit-under-miss enabled). It sets the undocumented bit 31 in
1391           the auxiliary control register and the FI bit in the control
1392           register, thus disabling hit-under-miss without putting the
1393           processor into full low interrupt latency mode. ARM11MPCore
1394           is not affected.
1395
1396 config ARM_ERRATA_764369
1397         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1398         depends on CPU_V7 && SMP
1399         help
1400           This option enables the workaround for erratum 764369
1401           affecting Cortex-A9 MPCore with two or more processors (all
1402           current revisions). Under certain timing circumstances, a data
1403           cache line maintenance operation by MVA targeting an Inner
1404           Shareable memory region may fail to proceed up to either the
1405           Point of Coherency or to the Point of Unification of the
1406           system. This workaround adds a DSB instruction before the
1407           relevant cache maintenance functions and sets a specific bit
1408           in the diagnostic control register of the SCU.
1409
1410 config PL310_ERRATA_769419
1411         bool "PL310 errata: no automatic Store Buffer drain"
1412         depends on CACHE_L2X0
1413         help
1414           On revisions of the PL310 prior to r3p2, the Store Buffer does
1415           not automatically drain. This can cause normal, non-cacheable
1416           writes to be retained when the memory system is idle, leading
1417           to suboptimal I/O performance for drivers using coherent DMA.
1418           This option adds a write barrier to the cpu_idle loop so that,
1419           on systems with an outer cache, the store buffer is drained
1420           explicitly.
1421
1422 endmenu
1423
1424 source "arch/arm/common/Kconfig"
1425
1426 menu "Bus support"
1427
1428 config ARM_AMBA
1429         bool
1430
1431 config ISA
1432         bool
1433         help
1434           Find out whether you have ISA slots on your motherboard.  ISA is the
1435           name of a bus system, i.e. the way the CPU talks to the other stuff
1436           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1437           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1438           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1439
1440 # Select ISA DMA controller support
1441 config ISA_DMA
1442         bool
1443         select ISA_DMA_API
1444
1445 # Select ISA DMA interface
1446 config ISA_DMA_API
1447         bool
1448
1449 config PCI
1450         bool "PCI support" if MIGHT_HAVE_PCI
1451         help
1452           Find out whether you have a PCI motherboard. PCI is the name of a
1453           bus system, i.e. the way the CPU talks to the other stuff inside
1454           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1455           VESA. If you have PCI, say Y, otherwise N.
1456
1457 config PCI_DOMAINS
1458         bool
1459         depends on PCI
1460
1461 config PCI_NANOENGINE
1462         bool "BSE nanoEngine PCI support"
1463         depends on SA1100_NANOENGINE
1464         help
1465           Enable PCI on the BSE nanoEngine board.
1466
1467 config PCI_SYSCALL
1468         def_bool PCI
1469
1470 # Select the host bridge type
1471 config PCI_HOST_VIA82C505
1472         bool
1473         depends on PCI && ARCH_SHARK
1474         default y
1475
1476 config PCI_HOST_ITE8152
1477         bool
1478         depends on PCI && MACH_ARMCORE
1479         default y
1480         select DMABOUNCE
1481
1482 source "drivers/pci/Kconfig"
1483
1484 source "drivers/pcmcia/Kconfig"
1485
1486 endmenu
1487
1488 menu "Kernel Features"
1489
1490 config HAVE_SMP
1491         bool
1492         help
1493           This option should be selected by machines which have an SMP-
1494           capable CPU.
1495
1496           The only effect of this option is to make the SMP-related
1497           options available to the user for configuration.
1498
1499 config SMP
1500         bool "Symmetric Multi-Processing"
1501         depends on CPU_V6K || CPU_V7
1502         depends on GENERIC_CLOCKEVENTS
1503         depends on HAVE_SMP
1504         depends on MMU
1505         select USE_GENERIC_SMP_HELPERS
1506         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1507         help
1508           This enables support for systems with more than one CPU. If you have
1509           a system with only one CPU, like most personal computers, say N. If
1510           you have a system with more than one CPU, say Y.
1511
1512           If you say N here, the kernel will run on single and multiprocessor
1513           machines, but will use only one CPU of a multiprocessor machine. If
1514           you say Y here, the kernel will run on many, but not all, single
1515           processor machines. On a single processor machine, the kernel will
1516           run faster if you say N here.
1517
1518           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1519           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1520           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1521
1522           If you don't know what to do here, say N.
1523
1524 config SMP_ON_UP
1525         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1526         depends on EXPERIMENTAL
1527         depends on SMP && !XIP_KERNEL
1528         default y
1529         help
1530           SMP kernels contain instructions which fail on non-SMP processors.
1531           Enabling this option allows the kernel to modify itself to make
1532           these instructions safe.  Disabling it allows about 1K of space
1533           savings.
1534
1535           If you don't know what to do here, say Y.
1536
1537 config ARM_CPU_TOPOLOGY
1538         bool "Support cpu topology definition"
1539         depends on SMP && CPU_V7
1540         default y
1541         help
1542           Support ARM cpu topology definition. The MPIDR register defines
1543           affinity between processors which is then used to describe the cpu
1544           topology of an ARM System.
1545
1546 config SCHED_MC
1547         bool "Multi-core scheduler support"
1548         depends on ARM_CPU_TOPOLOGY
1549         help
1550           Multi-core scheduler support improves the CPU scheduler's decision
1551           making when dealing with multi-core CPU chips at a cost of slightly
1552           increased overhead in some places. If unsure say N here.
1553
1554 config SCHED_SMT
1555         bool "SMT scheduler support"
1556         depends on ARM_CPU_TOPOLOGY
1557         help
1558           Improves the CPU scheduler's decision making when dealing with
1559           MultiThreading at a cost of slightly increased overhead in some
1560           places. If unsure say N here.
1561
1562 config HAVE_ARM_SCU
1563         bool
1564         help
1565           This option enables support for the ARM system coherency unit
1566
1567 config ARM_ARCH_TIMER
1568         bool "Architected timer support"
1569         depends on CPU_V7
1570         help
1571           This option enables support for the ARM architected timer
1572
1573 config HAVE_ARM_TWD
1574         bool
1575         depends on SMP
1576         help
1577           This options enables support for the ARM timer and watchdog unit
1578
1579 choice
1580         prompt "Memory split"
1581         default VMSPLIT_3G
1582         help
1583           Select the desired split between kernel and user memory.
1584
1585           If you are not absolutely sure what you are doing, leave this
1586           option alone!
1587
1588         config VMSPLIT_3G
1589                 bool "3G/1G user/kernel split"
1590         config VMSPLIT_2G
1591                 bool "2G/2G user/kernel split"
1592         config VMSPLIT_1G
1593                 bool "1G/3G user/kernel split"
1594 endchoice
1595
1596 config PAGE_OFFSET
1597         hex
1598         default 0x40000000 if VMSPLIT_1G
1599         default 0x80000000 if VMSPLIT_2G
1600         default 0xC0000000
1601
1602 config NR_CPUS
1603         int "Maximum number of CPUs (2-32)"
1604         range 2 32
1605         depends on SMP
1606         default "4"
1607
1608 config HOTPLUG_CPU
1609         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1610         depends on SMP && HOTPLUG && EXPERIMENTAL
1611         help
1612           Say Y here to experiment with turning CPUs off and on.  CPUs
1613           can be controlled through /sys/devices/system/cpu.
1614
1615 config LOCAL_TIMERS
1616         bool "Use local timer interrupts"
1617         depends on SMP
1618         default y
1619         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1620         help
1621           Enable support for local timers on SMP platforms, rather then the
1622           legacy IPI broadcast method.  Local timers allows the system
1623           accounting to be spread across the timer interval, preventing a
1624           "thundering herd" at every timer tick.
1625
1626 config ARCH_NR_GPIO
1627         int
1628         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1629         default 355 if ARCH_U8500
1630         default 264 if MACH_H4700
1631         default 512 if SOC_OMAP5
1632         default 0
1633         help
1634           Maximum number of GPIOs in the system.
1635
1636           If unsure, leave the default value.
1637
1638 source kernel/Kconfig.preempt
1639
1640 config HZ
1641         int
1642         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1643                 ARCH_S5PV210 || ARCH_EXYNOS4
1644         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1645         default AT91_TIMER_HZ if ARCH_AT91
1646         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1647         default 100
1648
1649 config THUMB2_KERNEL
1650         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1651         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1652         select AEABI
1653         select ARM_ASM_UNIFIED
1654         select ARM_UNWIND
1655         help
1656           By enabling this option, the kernel will be compiled in
1657           Thumb-2 mode. A compiler/assembler that understand the unified
1658           ARM-Thumb syntax is needed.
1659
1660           If unsure, say N.
1661
1662 config THUMB2_AVOID_R_ARM_THM_JUMP11
1663         bool "Work around buggy Thumb-2 short branch relocations in gas"
1664         depends on THUMB2_KERNEL && MODULES
1665         default y
1666         help
1667           Various binutils versions can resolve Thumb-2 branches to
1668           locally-defined, preemptible global symbols as short-range "b.n"
1669           branch instructions.
1670
1671           This is a problem, because there's no guarantee the final
1672           destination of the symbol, or any candidate locations for a
1673           trampoline, are within range of the branch.  For this reason, the
1674           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1675           relocation in modules at all, and it makes little sense to add
1676           support.
1677
1678           The symptom is that the kernel fails with an "unsupported
1679           relocation" error when loading some modules.
1680
1681           Until fixed tools are available, passing
1682           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1683           code which hits this problem, at the cost of a bit of extra runtime
1684           stack usage in some cases.
1685
1686           The problem is described in more detail at:
1687               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1688
1689           Only Thumb-2 kernels are affected.
1690
1691           Unless you are sure your tools don't have this problem, say Y.
1692
1693 config ARM_ASM_UNIFIED
1694         bool
1695
1696 config AEABI
1697         bool "Use the ARM EABI to compile the kernel"
1698         help
1699           This option allows for the kernel to be compiled using the latest
1700           ARM ABI (aka EABI).  This is only useful if you are using a user
1701           space environment that is also compiled with EABI.
1702
1703           Since there are major incompatibilities between the legacy ABI and
1704           EABI, especially with regard to structure member alignment, this
1705           option also changes the kernel syscall calling convention to
1706           disambiguate both ABIs and allow for backward compatibility support
1707           (selected with CONFIG_OABI_COMPAT).
1708
1709           To use this you need GCC version 4.0.0 or later.
1710
1711 config OABI_COMPAT
1712         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1713         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1714         default y
1715         help
1716           This option preserves the old syscall interface along with the
1717           new (ARM EABI) one. It also provides a compatibility layer to
1718           intercept syscalls that have structure arguments which layout
1719           in memory differs between the legacy ABI and the new ARM EABI
1720           (only for non "thumb" binaries). This option adds a tiny
1721           overhead to all syscalls and produces a slightly larger kernel.
1722           If you know you'll be using only pure EABI user space then you
1723           can say N here. If this option is not selected and you attempt
1724           to execute a legacy ABI binary then the result will be
1725           UNPREDICTABLE (in fact it can be predicted that it won't work
1726           at all). If in doubt say Y.
1727
1728 config ARCH_HAS_HOLES_MEMORYMODEL
1729         bool
1730
1731 config ARCH_SPARSEMEM_ENABLE
1732         bool
1733
1734 config ARCH_SPARSEMEM_DEFAULT
1735         def_bool ARCH_SPARSEMEM_ENABLE
1736
1737 config ARCH_SELECT_MEMORY_MODEL
1738         def_bool ARCH_SPARSEMEM_ENABLE
1739
1740 config HAVE_ARCH_PFN_VALID
1741         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1742
1743 config HIGHMEM
1744         bool "High Memory Support"
1745         depends on MMU
1746         help
1747           The address space of ARM processors is only 4 Gigabytes large
1748           and it has to accommodate user address space, kernel address
1749           space as well as some memory mapped IO. That means that, if you
1750           have a large amount of physical memory and/or IO, not all of the
1751           memory can be "permanently mapped" by the kernel. The physical
1752           memory that is not permanently mapped is called "high memory".
1753
1754           Depending on the selected kernel/user memory split, minimum
1755           vmalloc space and actual amount of RAM, you may not need this
1756           option which should result in a slightly faster kernel.
1757
1758           If unsure, say n.
1759
1760 config HIGHPTE
1761         bool "Allocate 2nd-level pagetables from highmem"
1762         depends on HIGHMEM
1763
1764 config HW_PERF_EVENTS
1765         bool "Enable hardware performance counter support for perf events"
1766         depends on PERF_EVENTS && CPU_HAS_PMU
1767         default y
1768         help
1769           Enable hardware performance counter support for perf events. If
1770           disabled, perf events will use software events only.
1771
1772 source "mm/Kconfig"
1773
1774 config FORCE_MAX_ZONEORDER
1775         int "Maximum zone order" if ARCH_SHMOBILE
1776         range 11 64 if ARCH_SHMOBILE
1777         default "9" if SA1111
1778         default "11"
1779         help
1780           The kernel memory allocator divides physically contiguous memory
1781           blocks into "zones", where each zone is a power of two number of
1782           pages.  This option selects the largest power of two that the kernel
1783           keeps in the memory allocator.  If you need to allocate very large
1784           blocks of physically contiguous memory, then you may need to
1785           increase this value.
1786
1787           This config option is actually maximum order plus one. For example,
1788           a value of 11 means that the largest free memory block is 2^10 pages.
1789
1790 config LEDS
1791         bool "Timer and CPU usage LEDs"
1792         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1793                    ARCH_EBSA285 || ARCH_INTEGRATOR || \
1794                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1795                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1796                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1797                    ARCH_AT91 || ARCH_DAVINCI || \
1798                    ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1799         help
1800           If you say Y here, the LEDs on your machine will be used
1801           to provide useful information about your current system status.
1802
1803           If you are compiling a kernel for a NetWinder or EBSA-285, you will
1804           be able to select which LEDs are active using the options below. If
1805           you are compiling a kernel for the EBSA-110 or the LART however, the
1806           red LED will simply flash regularly to indicate that the system is
1807           still functional. It is safe to say Y here if you have a CATS
1808           system, but the driver will do nothing.
1809
1810 config LEDS_TIMER
1811         bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1812                             OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1813                             || MACH_OMAP_PERSEUS2
1814         depends on LEDS
1815         depends on !GENERIC_CLOCKEVENTS
1816         default y if ARCH_EBSA110
1817         help
1818           If you say Y here, one of the system LEDs (the green one on the
1819           NetWinder, the amber one on the EBSA285, or the red one on the LART)
1820           will flash regularly to indicate that the system is still
1821           operational. This is mainly useful to kernel hackers who are
1822           debugging unstable kernels.
1823
1824           The LART uses the same LED for both Timer LED and CPU usage LED
1825           functions. You may choose to use both, but the Timer LED function
1826           will overrule the CPU usage LED.
1827
1828 config LEDS_CPU
1829         bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1830                         !ARCH_OMAP) \
1831                         || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1832                         || MACH_OMAP_PERSEUS2
1833         depends on LEDS
1834         help
1835           If you say Y here, the red LED will be used to give a good real
1836           time indication of CPU usage, by lighting whenever the idle task
1837           is not currently executing.
1838
1839           The LART uses the same LED for both Timer LED and CPU usage LED
1840           functions. You may choose to use both, but the Timer LED function
1841           will overrule the CPU usage LED.
1842
1843 config ALIGNMENT_TRAP
1844         bool
1845         depends on CPU_CP15_MMU
1846         default y if !ARCH_EBSA110
1847         select HAVE_PROC_CPU if PROC_FS
1848         help
1849           ARM processors cannot fetch/store information which is not
1850           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1851           address divisible by 4. On 32-bit ARM processors, these non-aligned
1852           fetch/store instructions will be emulated in software if you say
1853           here, which has a severe performance impact. This is necessary for
1854           correct operation of some network protocols. With an IP-only
1855           configuration it is safe to say N, otherwise say Y.
1856
1857 config UACCESS_WITH_MEMCPY
1858         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1859         depends on MMU && EXPERIMENTAL
1860         default y if CPU_FEROCEON
1861         help
1862           Implement faster copy_to_user and clear_user methods for CPU
1863           cores where a 8-word STM instruction give significantly higher
1864           memory write throughput than a sequence of individual 32bit stores.
1865
1866           A possible side effect is a slight increase in scheduling latency
1867           between threads sharing the same address space if they invoke
1868           such copy operations with large buffers.
1869
1870           However, if the CPU data cache is using a write-allocate mode,
1871           this option is unlikely to provide any performance gain.
1872
1873 config SECCOMP
1874         bool
1875         prompt "Enable seccomp to safely compute untrusted bytecode"
1876         ---help---
1877           This kernel feature is useful for number crunching applications
1878           that may need to compute untrusted bytecode during their
1879           execution. By using pipes or other transports made available to
1880           the process as file descriptors supporting the read/write
1881           syscalls, it's possible to isolate those applications in
1882           their own address space using seccomp. Once seccomp is
1883           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1884           and the task is only allowed to execute a few safe syscalls
1885           defined by each seccomp mode.
1886
1887 config CC_STACKPROTECTOR
1888         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1889         depends on EXPERIMENTAL
1890         help
1891           This option turns on the -fstack-protector GCC feature. This
1892           feature puts, at the beginning of functions, a canary value on
1893           the stack just before the return address, and validates
1894           the value just before actually returning.  Stack based buffer
1895           overflows (that need to overwrite this return address) now also
1896           overwrite the canary, which gets detected and the attack is then
1897           neutralized via a kernel panic.
1898           This feature requires gcc version 4.2 or above.
1899
1900 config DEPRECATED_PARAM_STRUCT
1901         bool "Provide old way to pass kernel parameters"
1902         help
1903           This was deprecated in 2001 and announced to live on for 5 years.
1904           Some old boot loaders still use this way.
1905
1906 endmenu
1907
1908 menu "Boot options"
1909
1910 config USE_OF
1911         bool "Flattened Device Tree support"
1912         select OF
1913         select OF_EARLY_FLATTREE
1914         select IRQ_DOMAIN
1915         help
1916           Include support for flattened device tree machine descriptions.
1917
1918 # Compressed boot loader in ROM.  Yes, we really want to ask about
1919 # TEXT and BSS so we preserve their values in the config files.
1920 config ZBOOT_ROM_TEXT
1921         hex "Compressed ROM boot loader base address"
1922         default "0"
1923         help
1924           The physical address at which the ROM-able zImage is to be
1925           placed in the target.  Platforms which normally make use of
1926           ROM-able zImage formats normally set this to a suitable
1927           value in their defconfig file.
1928
1929           If ZBOOT_ROM is not enabled, this has no effect.
1930
1931 config ZBOOT_ROM_BSS
1932         hex "Compressed ROM boot loader BSS address"
1933         default "0"
1934         help
1935           The base address of an area of read/write memory in the target
1936           for the ROM-able zImage which must be available while the
1937           decompressor is running. It must be large enough to hold the
1938           entire decompressed kernel plus an additional 128 KiB.
1939           Platforms which normally make use of ROM-able zImage formats
1940           normally set this to a suitable value in their defconfig file.
1941
1942           If ZBOOT_ROM is not enabled, this has no effect.
1943
1944 config ZBOOT_ROM
1945         bool "Compressed boot loader in ROM/flash"
1946         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1947         help
1948           Say Y here if you intend to execute your compressed kernel image
1949           (zImage) directly from ROM or flash.  If unsure, say N.
1950
1951 choice
1952         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1953         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1954         default ZBOOT_ROM_NONE
1955         help
1956           Include experimental SD/MMC loading code in the ROM-able zImage.
1957           With this enabled it is possible to write the ROM-able zImage
1958           kernel image to an MMC or SD card and boot the kernel straight
1959           from the reset vector. At reset the processor Mask ROM will load
1960           the first part of the ROM-able zImage which in turn loads the
1961           rest the kernel image to RAM.
1962
1963 config ZBOOT_ROM_NONE
1964         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1965         help
1966           Do not load image from SD or MMC
1967
1968 config ZBOOT_ROM_MMCIF
1969         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1970         help
1971           Load image from MMCIF hardware block.
1972
1973 config ZBOOT_ROM_SH_MOBILE_SDHI
1974         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1975         help
1976           Load image from SDHI hardware block
1977
1978 endchoice
1979
1980 config ARM_APPENDED_DTB
1981         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1982         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1983         help
1984           With this option, the boot code will look for a device tree binary
1985           (DTB) appended to zImage
1986           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1987
1988           This is meant as a backward compatibility convenience for those
1989           systems with a bootloader that can't be upgraded to accommodate
1990           the documented boot protocol using a device tree.
1991
1992           Beware that there is very little in terms of protection against
1993           this option being confused by leftover garbage in memory that might
1994           look like a DTB header after a reboot if no actual DTB is appended
1995           to zImage.  Do not leave this option active in a production kernel
1996           if you don't intend to always append a DTB.  Proper passing of the
1997           location into r2 of a bootloader provided DTB is always preferable
1998           to this option.
1999
2000 config ARM_ATAG_DTB_COMPAT
2001         bool "Supplement the appended DTB with traditional ATAG information"
2002         depends on ARM_APPENDED_DTB
2003         help
2004           Some old bootloaders can't be updated to a DTB capable one, yet
2005           they provide ATAGs with memory configuration, the ramdisk address,
2006           the kernel cmdline string, etc.  Such information is dynamically
2007           provided by the bootloader and can't always be stored in a static
2008           DTB.  To allow a device tree enabled kernel to be used with such
2009           bootloaders, this option allows zImage to extract the information
2010           from the ATAG list and store it at run time into the appended DTB.
2011
2012 choice
2013         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2014         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2015
2016 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2017         bool "Use bootloader kernel arguments if available"
2018         help
2019           Uses the command-line options passed by the boot loader instead of
2020           the device tree bootargs property. If the boot loader doesn't provide
2021           any, the device tree bootargs property will be used.
2022
2023 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2024         bool "Extend with bootloader kernel arguments"
2025         help
2026           The command-line arguments provided by the boot loader will be
2027           appended to the the device tree bootargs property.
2028
2029 endchoice
2030
2031 config CMDLINE
2032         string "Default kernel command string"
2033         default ""
2034         help
2035           On some architectures (EBSA110 and CATS), there is currently no way
2036           for the boot loader to pass arguments to the kernel. For these
2037           architectures, you should supply some command-line options at build
2038           time by entering them here. As a minimum, you should specify the
2039           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2040
2041 choice
2042         prompt "Kernel command line type" if CMDLINE != ""
2043         default CMDLINE_FROM_BOOTLOADER
2044
2045 config CMDLINE_FROM_BOOTLOADER
2046         bool "Use bootloader kernel arguments if available"
2047         help
2048           Uses the command-line options passed by the boot loader. If
2049           the boot loader doesn't provide any, the default kernel command
2050           string provided in CMDLINE will be used.
2051
2052 config CMDLINE_EXTEND
2053         bool "Extend bootloader kernel arguments"
2054         help
2055           The command-line arguments provided by the boot loader will be
2056           appended to the default kernel command string.
2057
2058 config CMDLINE_FORCE
2059         bool "Always use the default kernel command string"
2060         help
2061           Always use the default kernel command string, even if the boot
2062           loader passes other arguments to the kernel.
2063           This is useful if you cannot or don't want to change the
2064           command-line options your boot loader passes to the kernel.
2065 endchoice
2066
2067 config XIP_KERNEL
2068         bool "Kernel Execute-In-Place from ROM"
2069         depends on !ZBOOT_ROM && !ARM_LPAE
2070         help
2071           Execute-In-Place allows the kernel to run from non-volatile storage
2072           directly addressable by the CPU, such as NOR flash. This saves RAM
2073           space since the text section of the kernel is not loaded from flash
2074           to RAM.  Read-write sections, such as the data section and stack,
2075           are still copied to RAM.  The XIP kernel is not compressed since
2076           it has to run directly from flash, so it will take more space to
2077           store it.  The flash address used to link the kernel object files,
2078           and for storing it, is configuration dependent. Therefore, if you
2079           say Y here, you must know the proper physical address where to
2080           store the kernel image depending on your own flash memory usage.
2081
2082           Also note that the make target becomes "make xipImage" rather than
2083           "make zImage" or "make Image".  The final kernel binary to put in
2084           ROM memory will be arch/arm/boot/xipImage.
2085
2086           If unsure, say N.
2087
2088 config XIP_PHYS_ADDR
2089         hex "XIP Kernel Physical Location"
2090         depends on XIP_KERNEL
2091         default "0x00080000"
2092         help
2093           This is the physical address in your flash memory the kernel will
2094           be linked for and stored to.  This address is dependent on your
2095           own flash usage.
2096
2097 config KEXEC
2098         bool "Kexec system call (EXPERIMENTAL)"
2099         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2100         help
2101           kexec is a system call that implements the ability to shutdown your
2102           current kernel, and to start another kernel.  It is like a reboot
2103           but it is independent of the system firmware.   And like a reboot
2104           you can start any kernel with it, not just Linux.
2105
2106           It is an ongoing process to be certain the hardware in a machine
2107           is properly shutdown, so do not be surprised if this code does not
2108           initially work for you.  It may help to enable device hotplugging
2109           support.
2110
2111 config ATAGS_PROC
2112         bool "Export atags in procfs"
2113         depends on KEXEC
2114         default y
2115         help
2116           Should the atags used to boot the kernel be exported in an "atags"
2117           file in procfs. Useful with kexec.
2118
2119 config CRASH_DUMP
2120         bool "Build kdump crash kernel (EXPERIMENTAL)"
2121         depends on EXPERIMENTAL
2122         help
2123           Generate crash dump after being started by kexec. This should
2124           be normally only set in special crash dump kernels which are
2125           loaded in the main kernel with kexec-tools into a specially
2126           reserved region and then later executed after a crash by
2127           kdump/kexec. The crash dump kernel must be compiled to a
2128           memory address not used by the main kernel
2129
2130           For more details see Documentation/kdump/kdump.txt
2131
2132 config AUTO_ZRELADDR
2133         bool "Auto calculation of the decompressed kernel image address"
2134         depends on !ZBOOT_ROM && !ARCH_U300
2135         help
2136           ZRELADDR is the physical address where the decompressed kernel
2137           image will be placed. If AUTO_ZRELADDR is selected, the address
2138           will be determined at run-time by masking the current IP with
2139           0xf8000000. This assumes the zImage being placed in the first 128MB
2140           from start of memory.
2141
2142 endmenu
2143
2144 menu "CPU Power Management"
2145
2146 if ARCH_HAS_CPUFREQ
2147
2148 source "drivers/cpufreq/Kconfig"
2149
2150 config CPU_FREQ_IMX
2151         tristate "CPUfreq driver for i.MX CPUs"
2152         depends on ARCH_MXC && CPU_FREQ
2153         help
2154           This enables the CPUfreq driver for i.MX CPUs.
2155
2156 config CPU_FREQ_SA1100
2157         bool
2158
2159 config CPU_FREQ_SA1110
2160         bool
2161
2162 config CPU_FREQ_INTEGRATOR
2163         tristate "CPUfreq driver for ARM Integrator CPUs"
2164         depends on ARCH_INTEGRATOR && CPU_FREQ
2165         default y
2166         help
2167           This enables the CPUfreq driver for ARM Integrator CPUs.
2168
2169           For details, take a look at <file:Documentation/cpu-freq>.
2170
2171           If in doubt, say Y.
2172
2173 config CPU_FREQ_PXA
2174         bool
2175         depends on CPU_FREQ && ARCH_PXA && PXA25x
2176         default y
2177         select CPU_FREQ_TABLE
2178         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2179
2180 config CPU_FREQ_S3C
2181         bool
2182         help
2183           Internal configuration node for common cpufreq on Samsung SoC
2184
2185 config CPU_FREQ_S3C24XX
2186         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2187         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2188         select CPU_FREQ_S3C
2189         help
2190           This enables the CPUfreq driver for the Samsung S3C24XX family
2191           of CPUs.
2192
2193           For details, take a look at <file:Documentation/cpu-freq>.
2194
2195           If in doubt, say N.
2196
2197 config CPU_FREQ_S3C24XX_PLL
2198         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2199         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2200         help
2201           Compile in support for changing the PLL frequency from the
2202           S3C24XX series CPUfreq driver. The PLL takes time to settle
2203           after a frequency change, so by default it is not enabled.
2204
2205           This also means that the PLL tables for the selected CPU(s) will
2206           be built which may increase the size of the kernel image.
2207
2208 config CPU_FREQ_S3C24XX_DEBUG
2209         bool "Debug CPUfreq Samsung driver core"
2210         depends on CPU_FREQ_S3C24XX
2211         help
2212           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2213
2214 config CPU_FREQ_S3C24XX_IODEBUG
2215         bool "Debug CPUfreq Samsung driver IO timing"
2216         depends on CPU_FREQ_S3C24XX
2217         help
2218           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2219
2220 config CPU_FREQ_S3C24XX_DEBUGFS
2221         bool "Export debugfs for CPUFreq"
2222         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2223         help
2224           Export status information via debugfs.
2225
2226 endif
2227
2228 source "drivers/cpuidle/Kconfig"
2229
2230 endmenu
2231
2232 menu "Floating point emulation"
2233
2234 comment "At least one emulation must be selected"
2235
2236 config FPE_NWFPE
2237         bool "NWFPE math emulation"
2238         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2239         ---help---
2240           Say Y to include the NWFPE floating point emulator in the kernel.
2241           This is necessary to run most binaries. Linux does not currently
2242           support floating point hardware so you need to say Y here even if
2243           your machine has an FPA or floating point co-processor podule.
2244
2245           You may say N here if you are going to load the Acorn FPEmulator
2246           early in the bootup.
2247
2248 config FPE_NWFPE_XP
2249         bool "Support extended precision"
2250         depends on FPE_NWFPE
2251         help
2252           Say Y to include 80-bit support in the kernel floating-point
2253           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2254           Note that gcc does not generate 80-bit operations by default,
2255           so in most cases this option only enlarges the size of the
2256           floating point emulator without any good reason.
2257
2258           You almost surely want to say N here.
2259
2260 config FPE_FASTFPE
2261         bool "FastFPE math emulation (EXPERIMENTAL)"
2262         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2263         ---help---
2264           Say Y here to include the FAST floating point emulator in the kernel.
2265           This is an experimental much faster emulator which now also has full
2266           precision for the mantissa.  It does not support any exceptions.
2267           It is very simple, and approximately 3-6 times faster than NWFPE.
2268
2269           It should be sufficient for most programs.  It may be not suitable
2270           for scientific calculations, but you have to check this for yourself.
2271           If you do not feel you need a faster FP emulation you should better
2272           choose NWFPE.
2273
2274 config VFP
2275         bool "VFP-format floating point maths"
2276         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2277         help
2278           Say Y to include VFP support code in the kernel. This is needed
2279           if your hardware includes a VFP unit.
2280
2281           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2282           release notes and additional status information.
2283
2284           Say N if your target does not have VFP hardware.
2285
2286 config VFPv3
2287         bool
2288         depends on VFP
2289         default y if CPU_V7
2290
2291 config NEON
2292         bool "Advanced SIMD (NEON) Extension support"
2293         depends on VFPv3 && CPU_V7
2294         help
2295           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2296           Extension.
2297
2298 endmenu
2299
2300 menu "Userspace binary formats"
2301
2302 source "fs/Kconfig.binfmt"
2303
2304 config ARTHUR
2305         tristate "RISC OS personality"
2306         depends on !AEABI
2307         help
2308           Say Y here to include the kernel code necessary if you want to run
2309           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2310           experimental; if this sounds frightening, say N and sleep in peace.
2311           You can also say M here to compile this support as a module (which
2312           will be called arthur).
2313
2314 endmenu
2315
2316 menu "Power management options"
2317
2318 source "kernel/power/Kconfig"
2319
2320 config ARCH_SUSPEND_POSSIBLE
2321         depends on !ARCH_S5PC100 && !ARCH_TEGRA
2322         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2323                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2324         def_bool y
2325
2326 config ARM_CPU_SUSPEND
2327         def_bool PM_SLEEP
2328
2329 endmenu
2330
2331 source "net/Kconfig"
2332
2333 source "drivers/Kconfig"
2334
2335 source "fs/Kconfig"
2336
2337 source "arch/arm/Kconfig.debug"
2338
2339 source "security/Kconfig"
2340
2341 source "crypto/Kconfig"
2342
2343 source "lib/Kconfig"