arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAVE_CUSTOM_GPIO_H
   7         select ARCH_WANT_IPC_PARSE_VERSION
   8         select CPU_PM if (SUSPEND || CPU_IDLE)
   9         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
  10         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  11         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  12         select GENERIC_IRQ_PROBE
  13         select GENERIC_IRQ_SHOW
  14         select GENERIC_KERNEL_THREAD
  15         select GENERIC_KERNEL_EXECVE
  16         select GENERIC_PCI_IOMAP
  17         select GENERIC_SMP_IDLE_THREAD
  18         select GENERIC_STRNCPY_FROM_USER
  19         select GENERIC_STRNLEN_USER
  20         select HARDIRQS_SW_RESEND
  21         select HAVE_AOUT
  22         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  23         select HAVE_ARCH_KGDB
  24         select HAVE_ARCH_TRACEHOOK
  25         select HAVE_BPF_JIT
  26         select HAVE_C_RECORDMCOUNT
  27         select HAVE_DEBUG_KMEMLEAK
  28         select HAVE_DMA_API_DEBUG
  29         select HAVE_DMA_ATTRS
  30         select HAVE_DMA_CONTIGUOUS if MMU
  31         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  32         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  33         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  34         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  35         select HAVE_GENERIC_DMA_COHERENT
  36         select HAVE_GENERIC_HARDIRQS
  37         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  38         select HAVE_IDE if PCI || ISA || PCMCIA
  39         select HAVE_IRQ_WORK
  40         select HAVE_KERNEL_GZIP
  41         select HAVE_KERNEL_LZMA
  42         select HAVE_KERNEL_LZO
  43         select HAVE_KERNEL_XZ
  44         select HAVE_KPROBES if !XIP_KERNEL
  45         select HAVE_KRETPROBES if (HAVE_KPROBES)
  46         select HAVE_MEMBLOCK
  47         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  48         select HAVE_PERF_EVENTS
  49         select HAVE_REGS_AND_STACK_ACCESS_API
  50         select HAVE_SYSCALL_TRACEPOINTS
  51         select HAVE_UID16
  52         select KTIME_SCALAR
  53         select PERF_USE_VMALLOC
  54         select RTC_LIB
  55         select SYS_SUPPORTS_APM_EMULATION
  56         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  57         select MODULES_USE_ELF_REL
  58         help
  59           The ARM series is a line of low-power-consumption RISC chip designs
  60           licensed by ARM Ltd and targeted at embedded applications and
  61           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  62           manufactured, but legacy ARM-based PC hardware remains popular in
  63           Europe.  There is an ARM Linux project with a web page at
  64           <http://www.arm.linux.org.uk/>.
  65
  66 config ARM_HAS_SG_CHAIN
  67         bool
  68
  69 config NEED_SG_DMA_LENGTH
  70         bool
  71
  72 config ARM_DMA_USE_IOMMU
  73         bool
  74         select ARM_HAS_SG_CHAIN
  75         select NEED_SG_DMA_LENGTH
  76
  77 config HAVE_PWM
  78         bool
  79
  80 config MIGHT_HAVE_PCI
  81         bool
  82
  83 config SYS_SUPPORTS_APM_EMULATION
  84         bool
  85
  86 config GENERIC_GPIO
  87         bool
  88
  89 config HAVE_TCM
  90         bool
  91         select GENERIC_ALLOCATOR
  92
  93 config HAVE_PROC_CPU
  94         bool
  95
  96 config NO_IOPORT
  97         bool
  98
  99 config EISA
 100         bool
 101         ---help---
 102           The Extended Industry Standard Architecture (EISA) bus was
 103           developed as an open alternative to the IBM MicroChannel bus.
 104
 105           The EISA bus provided some of the features of the IBM MicroChannel
 106           bus while maintaining backward compatibility with cards made for
 107           the older ISA bus.  The EISA bus saw limited use between 1988 and
 108           1995 when it was made obsolete by the PCI bus.
 109
 110           Say Y here if you are building a kernel for an EISA-based machine.
 111
 112           Otherwise, say N.
 113
 114 config SBUS
 115         bool
 116
 117 config STACKTRACE_SUPPORT
 118         bool
 119         default y
 120
 121 config HAVE_LATENCYTOP_SUPPORT
 122         bool
 123         depends on !SMP
 124         default y
 125
 126 config LOCKDEP_SUPPORT
 127         bool
 128         default y
 129
 130 config TRACE_IRQFLAGS_SUPPORT
 131         bool
 132         default y
 133
 134 config RWSEM_GENERIC_SPINLOCK
 135         bool
 136         default y
 137
 138 config RWSEM_XCHGADD_ALGORITHM
 139         bool
 140
 141 config ARCH_HAS_ILOG2_U32
 142         bool
 143
 144 config ARCH_HAS_ILOG2_U64
 145         bool
 146
 147 config ARCH_HAS_CPUFREQ
 148         bool
 149         help
 150           Internal node to signify that the ARCH has CPUFREQ support
 151           and that the relevant menu configurations are displayed for
 152           it.
 153
 154 config GENERIC_HWEIGHT
 155         bool
 156         default y
 157
 158 config GENERIC_CALIBRATE_DELAY
 159         bool
 160         default y
 161
 162 config ARCH_MAY_HAVE_PC_FDC
 163         bool
 164
 165 config ZONE_DMA
 166         bool
 167
 168 config NEED_DMA_MAP_STATE
 169        def_bool y
 170
 171 config ARCH_HAS_DMA_SET_COHERENT_MASK
 172         bool
 173
 174 config GENERIC_ISA_DMA
 175         bool
 176
 177 config FIQ
 178         bool
 179
 180 config NEED_RET_TO_USER
 181         bool
 182
 183 config ARCH_MTD_XIP
 184         bool
 185
 186 config VECTORS_BASE
 187         hex
 188         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 189         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 190         default 0x00000000
 191         help
 192           The base address of exception vectors.
 193
 194 config ARM_PATCH_PHYS_VIRT
 195         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 196         default y
 197         depends on !XIP_KERNEL && MMU
 198         depends on !ARCH_REALVIEW || !SPARSEMEM
 199         help
 200           Patch phys-to-virt and virt-to-phys translation functions at
 201           boot and module load time according to the position of the
 202           kernel in system memory.
 203
 204           This can only be used with non-XIP MMU kernels where the base
 205           of physical memory is at a 16MB boundary.
 206
 207           Only disable this option if you know that you do not require
 208           this feature (eg, building a kernel for a single machine) and
 209           you need to shrink the kernel to the minimal size.
 210
 211 config NEED_MACH_GPIO_H
 212         bool
 213         help
 214           Select this when mach/gpio.h is required to provide special
 215           definitions for this platform. The need for mach/gpio.h should
 216           be avoided when possible.
 217
 218 config NEED_MACH_IO_H
 219         bool
 220         help
 221           Select this when mach/io.h is required to provide special
 222           definitions for this platform.  The need for mach/io.h should
 223           be avoided when possible.
 224
 225 config NEED_MACH_MEMORY_H
 226         bool
 227         help
 228           Select this when mach/memory.h is required to provide special
 229           definitions for this platform.  The need for mach/memory.h should
 230           be avoided when possible.
 231
 232 config PHYS_OFFSET
 233         hex "Physical address of main memory" if MMU
 234         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 235         default DRAM_BASE if !MMU
 236         help
 237           Please provide the physical address corresponding to the
 238           location of main memory in your system.
 239
 240 config GENERIC_BUG
 241         def_bool y
 242         depends on BUG
 243
 244 source "init/Kconfig"
 245
 246 source "kernel/Kconfig.freezer"
 247
 248 menu "System Type"
 249
 250 config MMU
 251         bool "MMU-based Paged Memory Management Support"
 252         default y
 253         help
 254           Select if you want MMU-based virtualised addressing space
 255           support by paged memory management. If unsure, say 'Y'.
 256
 257 #
 258 # The "ARM system type" choice list is ordered alphabetically by option
 259 # text.  Please add new entries in the option alphabetic order.
 260 #
 261 choice
 262         prompt "ARM system type"
 263         default ARCH_MULTIPLATFORM
 264
 265 config ARCH_MULTIPLATFORM
 266         bool "Allow multiple platforms to be selected"
 267         depends on MMU
 268         select ARM_PATCH_PHYS_VIRT
 269         select AUTO_ZRELADDR
 270         select COMMON_CLK
 271         select MULTI_IRQ_HANDLER
 272         select SPARSE_IRQ
 273         select USE_OF
 274
 275 config ARCH_INTEGRATOR
 276         bool "ARM Ltd. Integrator family"
 277         select ARCH_HAS_CPUFREQ
 278         select ARM_AMBA
 279         select COMMON_CLK
 280         select COMMON_CLK_VERSATILE
 281         select GENERIC_CLOCKEVENTS
 282         select HAVE_TCM
 283         select ICST
 284         select MULTI_IRQ_HANDLER
 285         select NEED_MACH_MEMORY_H
 286         select PLAT_VERSATILE
 287         select SPARSE_IRQ
 288         select VERSATILE_FPGA_IRQ
 289         help
 290           Support for ARM's Integrator platform.
 291
 292 config ARCH_REALVIEW
 293         bool "ARM Ltd. RealView family"
 294         select ARCH_WANT_OPTIONAL_GPIOLIB
 295         select ARM_AMBA
 296         select ARM_TIMER_SP804
 297         select COMMON_CLK
 298         select COMMON_CLK_VERSATILE
 299         select GENERIC_CLOCKEVENTS
 300         select GPIO_PL061 if GPIOLIB
 301         select ICST
 302         select NEED_MACH_MEMORY_H
 303         select PLAT_VERSATILE
 304         select PLAT_VERSATILE_CLCD
 305         help
 306           This enables support for ARM Ltd RealView boards.
 307
 308 config ARCH_VERSATILE
 309         bool "ARM Ltd. Versatile family"
 310         select ARCH_WANT_OPTIONAL_GPIOLIB
 311         select ARM_AMBA
 312         select ARM_TIMER_SP804
 313         select ARM_VIC
 314         select CLKDEV_LOOKUP
 315         select GENERIC_CLOCKEVENTS
 316         select HAVE_MACH_CLKDEV
 317         select ICST
 318         select PLAT_VERSATILE
 319         select PLAT_VERSATILE_CLCD
 320         select PLAT_VERSATILE_CLOCK
 321         select VERSATILE_FPGA_IRQ
 322         help
 323           This enables support for ARM Ltd Versatile board.
 324
 325 config ARCH_AT91
 326         bool "Atmel AT91"
 327         select ARCH_REQUIRE_GPIOLIB
 328         select CLKDEV_LOOKUP
 329         select HAVE_CLK
 330         select IRQ_DOMAIN
 331         select NEED_MACH_GPIO_H
 332         select NEED_MACH_IO_H if PCCARD
 333         help
 334           This enables support for systems based on Atmel
 335           AT91RM9200 and AT91SAM9* processors.
 336
 337 config ARCH_BCM2835
 338         bool "Broadcom BCM2835 family"
 339         select ARCH_WANT_OPTIONAL_GPIOLIB
 340         select ARM_AMBA
 341         select ARM_ERRATA_411920
 342         select ARM_TIMER_SP804
 343         select CLKDEV_LOOKUP
 344         select COMMON_CLK
 345         select CPU_V6
 346         select GENERIC_CLOCKEVENTS
 347         select MULTI_IRQ_HANDLER
 348         select SPARSE_IRQ
 349         select USE_OF
 350         help
 351           This enables support for the Broadcom BCM2835 SoC. This SoC is
 352           use in the Raspberry Pi, and Roku 2 devices.
 353
 354 config ARCH_CNS3XXX
 355         bool "Cavium Networks CNS3XXX family"
 356         select ARM_GIC
 357         select CPU_V6K
 358         select GENERIC_CLOCKEVENTS
 359         select MIGHT_HAVE_CACHE_L2X0
 360         select MIGHT_HAVE_PCI
 361         select PCI_DOMAINS if PCI
 362         help
 363           Support for Cavium Networks CNS3XXX platform.
 364
 365 config ARCH_CLPS711X
 366         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 367         select CLKDEV_LOOKUP
 368         select COMMON_CLK
 369         select CPU_ARM720T
 370         select GENERIC_CLOCKEVENTS
 371         select NEED_MACH_MEMORY_H
 372         help
 373           Support for Cirrus Logic 711x/721x/731x based boards.
 374
 375 config ARCH_GEMINI
 376         bool "Cortina Systems Gemini"
 377         select ARCH_REQUIRE_GPIOLIB
 378         select ARCH_USES_GETTIMEOFFSET
 379         select CPU_FA526
 380         help
 381           Support for the Cortina Systems Gemini family SoCs
 382
 383 config ARCH_SIRF
 384         bool "CSR SiRF"
 385         select ARCH_REQUIRE_GPIOLIB
 386         select COMMON_CLK
 387         select GENERIC_CLOCKEVENTS
 388         select GENERIC_IRQ_CHIP
 389         select MIGHT_HAVE_CACHE_L2X0
 390         select NO_IOPORT
 391         select PINCTRL
 392         select PINCTRL_SIRF
 393         select USE_OF
 394         help
 395           Support for CSR SiRFprimaII/Marco/Polo platforms
 396
 397 config ARCH_EBSA110
 398         bool "EBSA-110"
 399         select ARCH_USES_GETTIMEOFFSET
 400         select CPU_SA110
 401         select ISA
 402         select NEED_MACH_IO_H
 403         select NEED_MACH_MEMORY_H
 404         select NO_IOPORT
 405         help
 406           This is an evaluation board for the StrongARM processor available
 407           from Digital. It has limited hardware on-board, including an
 408           Ethernet interface, two PCMCIA sockets, two serial ports and a
 409           parallel port.
 410
 411 config ARCH_EP93XX
 412         bool "EP93xx-based"
 413         select ARCH_HAS_HOLES_MEMORYMODEL
 414         select ARCH_REQUIRE_GPIOLIB
 415         select ARCH_USES_GETTIMEOFFSET
 416         select ARM_AMBA
 417         select ARM_VIC
 418         select CLKDEV_LOOKUP
 419         select CPU_ARM920T
 420         select NEED_MACH_MEMORY_H
 421         help
 422           This enables support for the Cirrus EP93xx series of CPUs.
 423
 424 config ARCH_FOOTBRIDGE
 425         bool "FootBridge"
 426         select CPU_SA110
 427         select FOOTBRIDGE
 428         select GENERIC_CLOCKEVENTS
 429         select HAVE_IDE
 430         select NEED_MACH_IO_H if !MMU
 431         select NEED_MACH_MEMORY_H
 432         help
 433           Support for systems based on the DC21285 companion chip
 434           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 435
 436 config ARCH_MXS
 437         bool "Freescale MXS-based"
 438         select ARCH_REQUIRE_GPIOLIB
 439         select CLKDEV_LOOKUP
 440         select CLKSRC_MMIO
 441         select COMMON_CLK
 442         select GENERIC_CLOCKEVENTS
 443         select HAVE_CLK_PREPARE
 444         select MULTI_IRQ_HANDLER
 445         select PINCTRL
 446         select SPARSE_IRQ
 447         select USE_OF
 448         help
 449           Support for Freescale MXS-based family of processors
 450
 451 config ARCH_NETX
 452         bool "Hilscher NetX based"
 453         select ARM_VIC
 454         select CLKSRC_MMIO
 455         select CPU_ARM926T
 456         select GENERIC_CLOCKEVENTS
 457         help
 458           This enables support for systems based on the Hilscher NetX Soc
 459
 460 config ARCH_H720X
 461         bool "Hynix HMS720x-based"
 462         select ARCH_USES_GETTIMEOFFSET
 463         select CPU_ARM720T
 464         select ISA_DMA_API
 465         help
 466           This enables support for systems based on the Hynix HMS720x
 467
 468 config ARCH_IOP13XX
 469         bool "IOP13xx-based"
 470         depends on MMU
 471         select ARCH_SUPPORTS_MSI
 472         select CPU_XSC3
 473         select NEED_MACH_MEMORY_H
 474         select NEED_RET_TO_USER
 475         select PCI
 476         select PLAT_IOP
 477         select VMSPLIT_1G
 478         help
 479           Support for Intel's IOP13XX (XScale) family of processors.
 480
 481 config ARCH_IOP32X
 482         bool "IOP32x-based"
 483         depends on MMU
 484         select ARCH_REQUIRE_GPIOLIB
 485         select CPU_XSCALE
 486         select NEED_MACH_GPIO_H
 487         select NEED_RET_TO_USER
 488         select PCI
 489         select PLAT_IOP
 490         help
 491           Support for Intel's 80219 and IOP32X (XScale) family of
 492           processors.
 493
 494 config ARCH_IOP33X
 495         bool "IOP33x-based"
 496         depends on MMU
 497         select ARCH_REQUIRE_GPIOLIB
 498         select CPU_XSCALE
 499         select NEED_MACH_GPIO_H
 500         select NEED_RET_TO_USER
 501         select PCI
 502         select PLAT_IOP
 503         help
 504           Support for Intel's IOP33X (XScale) family of processors.
 505
 506 config ARCH_IXP4XX
 507         bool "IXP4xx-based"
 508         depends on MMU
 509         select ARCH_HAS_DMA_SET_COHERENT_MASK
 510         select ARCH_REQUIRE_GPIOLIB
 511         select CLKSRC_MMIO
 512         select CPU_XSCALE
 513         select DMABOUNCE if PCI
 514         select GENERIC_CLOCKEVENTS
 515         select MIGHT_HAVE_PCI
 516         select NEED_MACH_IO_H
 517         help
 518           Support for Intel's IXP4XX (XScale) family of processors.
 519
 520 config ARCH_DOVE
 521         bool "Marvell Dove"
 522         select ARCH_REQUIRE_GPIOLIB
 523         select CPU_V7
 524         select GENERIC_CLOCKEVENTS
 525         select MIGHT_HAVE_PCI
 526         select PLAT_ORION_LEGACY
 527         select USB_ARCH_HAS_EHCI
 528         help
 529           Support for the Marvell Dove SoC 88AP510
 530
 531 config ARCH_KIRKWOOD
 532         bool "Marvell Kirkwood"
 533         select ARCH_REQUIRE_GPIOLIB
 534         select CPU_FEROCEON
 535         select GENERIC_CLOCKEVENTS
 536         select PCI
 537         select PLAT_ORION_LEGACY
 538         help
 539           Support for the following Marvell Kirkwood series SoCs:
 540           88F6180, 88F6192 and 88F6281.
 541
 542 config ARCH_MV78XX0
 543         bool "Marvell MV78xx0"
 544         select ARCH_REQUIRE_GPIOLIB
 545         select CPU_FEROCEON
 546         select GENERIC_CLOCKEVENTS
 547         select PCI
 548         select PLAT_ORION_LEGACY
 549         help
 550           Support for the following Marvell MV78xx0 series SoCs:
 551           MV781x0, MV782x0.
 552
 553 config ARCH_ORION5X
 554         bool "Marvell Orion"
 555         depends on MMU
 556         select ARCH_REQUIRE_GPIOLIB
 557         select CPU_FEROCEON
 558         select GENERIC_CLOCKEVENTS
 559         select PCI
 560         select PLAT_ORION_LEGACY
 561         help
 562           Support for the following Marvell Orion 5x series SoCs:
 563           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 564           Orion-2 (5281), Orion-1-90 (6183).
 565
 566 config ARCH_MMP
 567         bool "Marvell PXA168/910/MMP2"
 568         depends on MMU
 569         select ARCH_REQUIRE_GPIOLIB
 570         select CLKDEV_LOOKUP
 571         select GENERIC_ALLOCATOR
 572         select GENERIC_CLOCKEVENTS
 573         select GPIO_PXA
 574         select IRQ_DOMAIN
 575         select NEED_MACH_GPIO_H
 576         select PLAT_PXA
 577         select SPARSE_IRQ
 578         help
 579           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 580
 581 config ARCH_KS8695
 582         bool "Micrel/Kendin KS8695"
 583         select ARCH_REQUIRE_GPIOLIB
 584         select CLKSRC_MMIO
 585         select CPU_ARM922T
 586         select GENERIC_CLOCKEVENTS
 587         select NEED_MACH_MEMORY_H
 588         help
 589           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 590           System-on-Chip devices.
 591
 592 config ARCH_W90X900
 593         bool "Nuvoton W90X900 CPU"
 594         select ARCH_REQUIRE_GPIOLIB
 595         select CLKDEV_LOOKUP
 596         select CLKSRC_MMIO
 597         select CPU_ARM926T
 598         select GENERIC_CLOCKEVENTS
 599         help
 600           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 601           At present, the w90x900 has been renamed nuc900, regarding
 602           the ARM series product line, you can login the following
 603           link address to know more.
 604
 605           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 606                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 607
 608 config ARCH_LPC32XX
 609         bool "NXP LPC32XX"
 610         select ARCH_REQUIRE_GPIOLIB
 611         select ARM_AMBA
 612         select CLKDEV_LOOKUP
 613         select CLKSRC_MMIO
 614         select CPU_ARM926T
 615         select GENERIC_CLOCKEVENTS
 616         select HAVE_IDE
 617         select HAVE_PWM
 618         select USB_ARCH_HAS_OHCI
 619         select USE_OF
 620         help
 621           Support for the NXP LPC32XX family of processors
 622
 623 config ARCH_TEGRA
 624         bool "NVIDIA Tegra"
 625         select ARCH_HAS_CPUFREQ
 626         select CLKDEV_LOOKUP
 627         select CLKSRC_MMIO
 628         select COMMON_CLK
 629         select GENERIC_CLOCKEVENTS
 630         select GENERIC_GPIO
 631         select HAVE_CLK
 632         select HAVE_SMP
 633         select MIGHT_HAVE_CACHE_L2X0
 634         select USE_OF
 635         help
 636           This enables support for NVIDIA Tegra based systems (Tegra APX,
 637           Tegra 6xx and Tegra 2 series).
 638
 639 config ARCH_PXA
 640         bool "PXA2xx/PXA3xx-based"
 641         depends on MMU
 642         select ARCH_HAS_CPUFREQ
 643         select ARCH_MTD_XIP
 644         select ARCH_REQUIRE_GPIOLIB
 645         select ARM_CPU_SUSPEND if PM
 646         select AUTO_ZRELADDR
 647         select CLKDEV_LOOKUP
 648         select CLKSRC_MMIO
 649         select GENERIC_CLOCKEVENTS
 650         select GPIO_PXA
 651         select HAVE_IDE
 652         select MULTI_IRQ_HANDLER
 653         select NEED_MACH_GPIO_H
 654         select PLAT_PXA
 655         select SPARSE_IRQ
 656         help
 657           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 658
 659 config ARCH_MSM
 660         bool "Qualcomm MSM"
 661         select ARCH_REQUIRE_GPIOLIB
 662         select CLKDEV_LOOKUP
 663         select GENERIC_CLOCKEVENTS
 664         select HAVE_CLK
 665         help
 666           Support for Qualcomm MSM/QSD based systems.  This runs on the
 667           apps processor of the MSM/QSD and depends on a shared memory
 668           interface to the modem processor which runs the baseband
 669           stack and controls some vital subsystems
 670           (clock and power control, etc).
 671
 672 config ARCH_SHMOBILE
 673         bool "Renesas SH-Mobile / R-Mobile"
 674         select CLKDEV_LOOKUP
 675         select GENERIC_CLOCKEVENTS
 676         select HAVE_CLK
 677         select HAVE_MACH_CLKDEV
 678         select HAVE_SMP
 679         select MIGHT_HAVE_CACHE_L2X0
 680         select MULTI_IRQ_HANDLER
 681         select NEED_MACH_MEMORY_H
 682         select NO_IOPORT
 683         select PM_GENERIC_DOMAINS if PM
 684         select SPARSE_IRQ
 685         help
 686           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 687
 688 config ARCH_RPC
 689         bool "RiscPC"
 690         select ARCH_ACORN
 691         select ARCH_MAY_HAVE_PC_FDC
 692         select ARCH_SPARSEMEM_ENABLE
 693         select ARCH_USES_GETTIMEOFFSET
 694         select FIQ
 695         select HAVE_IDE
 696         select HAVE_PATA_PLATFORM
 697         select ISA_DMA_API
 698         select NEED_MACH_IO_H
 699         select NEED_MACH_MEMORY_H
 700         select NO_IOPORT
 701         help
 702           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 703           CD-ROM interface, serial and parallel port, and the floppy drive.
 704
 705 config ARCH_SA1100
 706         bool "SA1100-based"
 707         select ARCH_HAS_CPUFREQ
 708         select ARCH_MTD_XIP
 709         select ARCH_REQUIRE_GPIOLIB
 710         select ARCH_SPARSEMEM_ENABLE
 711         select CLKDEV_LOOKUP
 712         select CLKSRC_MMIO
 713         select CPU_FREQ
 714         select CPU_SA1100
 715         select GENERIC_CLOCKEVENTS
 716         select HAVE_IDE
 717         select ISA
 718         select NEED_MACH_GPIO_H
 719         select NEED_MACH_MEMORY_H
 720         select SPARSE_IRQ
 721         help
 722           Support for StrongARM 11x0 based boards.
 723
 724 config ARCH_S3C24XX
 725         bool "Samsung S3C24XX SoCs"
 726         select ARCH_HAS_CPUFREQ
 727         select ARCH_USES_GETTIMEOFFSET
 728         select CLKDEV_LOOKUP
 729         select GENERIC_GPIO
 730         select HAVE_CLK
 731         select HAVE_S3C2410_I2C if I2C
 732         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 733         select HAVE_S3C_RTC if RTC_CLASS
 734         select NEED_MACH_GPIO_H
 735         select NEED_MACH_IO_H
 736         help
 737           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 738           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 739           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 740           Samsung SMDK2410 development board (and derivatives).
 741
 742 config ARCH_S3C64XX
 743         bool "Samsung S3C64XX"
 744         select ARCH_HAS_CPUFREQ
 745         select ARCH_REQUIRE_GPIOLIB
 746         select ARCH_USES_GETTIMEOFFSET
 747         select ARM_VIC
 748         select CLKDEV_LOOKUP
 749         select CPU_V6
 750         select HAVE_CLK
 751         select HAVE_S3C2410_I2C if I2C
 752         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 753         select HAVE_TCM
 754         select NEED_MACH_GPIO_H
 755         select NO_IOPORT
 756         select PLAT_SAMSUNG
 757         select S3C_DEV_NAND
 758         select S3C_GPIO_TRACK
 759         select SAMSUNG_CLKSRC
 760         select SAMSUNG_GPIOLIB_4BIT
 761         select SAMSUNG_IRQ_VIC_TIMER
 762         select USB_ARCH_HAS_OHCI
 763         help
 764           Samsung S3C64XX series based systems
 765
 766 config ARCH_S5P64X0
 767         bool "Samsung S5P6440 S5P6450"
 768         select CLKDEV_LOOKUP
 769         select CLKSRC_MMIO
 770         select CPU_V6
 771         select GENERIC_CLOCKEVENTS
 772         select GENERIC_GPIO
 773         select HAVE_CLK
 774         select HAVE_S3C2410_I2C if I2C
 775         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 776         select HAVE_S3C_RTC if RTC_CLASS
 777         select NEED_MACH_GPIO_H
 778         help
 779           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 780           SMDK6450.
 781
 782 config ARCH_S5PC100
 783         bool "Samsung S5PC100"
 784         select ARCH_USES_GETTIMEOFFSET
 785         select CLKDEV_LOOKUP
 786         select CPU_V7
 787         select GENERIC_GPIO
 788         select HAVE_CLK
 789         select HAVE_S3C2410_I2C if I2C
 790         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 791         select HAVE_S3C_RTC if RTC_CLASS
 792         select NEED_MACH_GPIO_H
 793         help
 794           Samsung S5PC100 series based systems
 795
 796 config ARCH_S5PV210
 797         bool "Samsung S5PV210/S5PC110"
 798         select ARCH_HAS_CPUFREQ
 799         select ARCH_HAS_HOLES_MEMORYMODEL
 800         select ARCH_SPARSEMEM_ENABLE
 801         select CLKDEV_LOOKUP
 802         select CLKSRC_MMIO
 803         select CPU_V7
 804         select GENERIC_CLOCKEVENTS
 805         select GENERIC_GPIO
 806         select HAVE_CLK
 807         select HAVE_S3C2410_I2C if I2C
 808         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 809         select HAVE_S3C_RTC if RTC_CLASS
 810         select NEED_MACH_GPIO_H
 811         select NEED_MACH_MEMORY_H
 812         help
 813           Samsung S5PV210/S5PC110 series based systems
 814
 815 config ARCH_EXYNOS
 816         bool "Samsung EXYNOS"
 817         select ARCH_HAS_CPUFREQ
 818         select ARCH_HAS_HOLES_MEMORYMODEL
 819         select ARCH_SPARSEMEM_ENABLE
 820         select CLKDEV_LOOKUP
 821         select CPU_V7
 822         select GENERIC_CLOCKEVENTS
 823         select GENERIC_GPIO
 824         select HAVE_CLK
 825         select HAVE_S3C2410_I2C if I2C
 826         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 827         select HAVE_S3C_RTC if RTC_CLASS
 828         select NEED_MACH_GPIO_H
 829         select NEED_MACH_MEMORY_H
 830         help
 831           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 832
 833 config ARCH_SHARK
 834         bool "Shark"
 835         select ARCH_USES_GETTIMEOFFSET
 836         select CPU_SA110
 837         select ISA
 838         select ISA_DMA
 839         select NEED_MACH_MEMORY_H
 840         select PCI
 841         select ZONE_DMA
 842         help
 843           Support for the StrongARM based Digital DNARD machine, also known
 844           as "Shark" (<http://www.shark-linux.de/shark.html>).
 845
 846 config ARCH_U300
 847         bool "ST-Ericsson U300 Series"
 848         depends on MMU
 849         select ARCH_REQUIRE_GPIOLIB
 850         select ARM_AMBA
 851         select ARM_PATCH_PHYS_VIRT
 852         select ARM_VIC
 853         select CLKDEV_LOOKUP
 854         select CLKSRC_MMIO
 855         select COMMON_CLK
 856         select CPU_ARM926T
 857         select GENERIC_CLOCKEVENTS
 858         select GENERIC_GPIO
 859         select HAVE_TCM
 860         select SPARSE_IRQ
 861         help
 862           Support for ST-Ericsson U300 series mobile platforms.
 863
 864 config ARCH_U8500
 865         bool "ST-Ericsson U8500 Series"
 866         depends on MMU
 867         select ARCH_HAS_CPUFREQ
 868         select ARCH_REQUIRE_GPIOLIB
 869         select ARM_AMBA
 870         select CLKDEV_LOOKUP
 871         select CPU_V7
 872         select GENERIC_CLOCKEVENTS
 873         select HAVE_SMP
 874         select MIGHT_HAVE_CACHE_L2X0
 875         help
 876           Support for ST-Ericsson's Ux500 architecture
 877
 878 config ARCH_NOMADIK
 879         bool "STMicroelectronics Nomadik"
 880         select ARCH_REQUIRE_GPIOLIB
 881         select ARM_AMBA
 882         select ARM_VIC
 883         select COMMON_CLK
 884         select CPU_ARM926T
 885         select GENERIC_CLOCKEVENTS
 886         select MIGHT_HAVE_CACHE_L2X0
 887         select PINCTRL
 888         select PINCTRL_STN8815
 889         help
 890           Support for the Nomadik platform by ST-Ericsson
 891
 892 config PLAT_SPEAR
 893         bool "ST SPEAr"
 894         select ARCH_REQUIRE_GPIOLIB
 895         select ARM_AMBA
 896         select CLKDEV_LOOKUP
 897         select CLKSRC_MMIO
 898         select COMMON_CLK
 899         select GENERIC_CLOCKEVENTS
 900         select HAVE_CLK
 901         help
 902           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 903
 904 config ARCH_DAVINCI
 905         bool "TI DaVinci"
 906         select ARCH_HAS_HOLES_MEMORYMODEL
 907         select ARCH_REQUIRE_GPIOLIB
 908         select CLKDEV_LOOKUP
 909         select GENERIC_ALLOCATOR
 910         select GENERIC_CLOCKEVENTS
 911         select GENERIC_IRQ_CHIP
 912         select HAVE_IDE
 913         select NEED_MACH_GPIO_H
 914         select ZONE_DMA
 915         help
 916           Support for TI's DaVinci platform.
 917
 918 config ARCH_OMAP
 919         bool "TI OMAP"
 920         depends on MMU
 921         select ARCH_HAS_CPUFREQ
 922         select ARCH_HAS_HOLES_MEMORYMODEL
 923         select ARCH_REQUIRE_GPIOLIB
 924         select CLKSRC_MMIO
 925         select GENERIC_CLOCKEVENTS
 926         select HAVE_CLK
 927         select NEED_MACH_GPIO_H
 928         help
 929           Support for TI's OMAP platform (OMAP1/2/3/4).
 930
 931 config ARCH_VT8500
 932         bool "VIA/WonderMedia 85xx"
 933         select ARCH_HAS_CPUFREQ
 934         select ARCH_REQUIRE_GPIOLIB
 935         select CLKDEV_LOOKUP
 936         select COMMON_CLK
 937         select CPU_ARM926T
 938         select GENERIC_CLOCKEVENTS
 939         select GENERIC_GPIO
 940         select HAVE_CLK
 941         select USE_OF
 942         help
 943           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 944
 945 config ARCH_ZYNQ
 946         bool "Xilinx Zynq ARM Cortex A9 Platform"
 947         select ARM_AMBA
 948         select ARM_GIC
 949         select CLKDEV_LOOKUP
 950         select CPU_V7
 951         select GENERIC_CLOCKEVENTS
 952         select ICST
 953         select MIGHT_HAVE_CACHE_L2X0
 954         select USE_OF
 955         help
 956           Support for Xilinx Zynq ARM Cortex A9 Platform
 957 endchoice
 958
 959 menu "Multiple platform selection"
 960         depends on ARCH_MULTIPLATFORM
 961
 962 comment "CPU Core family selection"
 963
 964 config ARCH_MULTI_V4
 965         bool "ARMv4 based platforms (FA526, StrongARM)"
 966         depends on !ARCH_MULTI_V6_V7
 967         select ARCH_MULTI_V4_V5
 968
 969 config ARCH_MULTI_V4T
 970         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 971         depends on !ARCH_MULTI_V6_V7
 972         select ARCH_MULTI_V4_V5
 973
 974 config ARCH_MULTI_V5
 975         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 976         depends on !ARCH_MULTI_V6_V7
 977         select ARCH_MULTI_V4_V5
 978
 979 config ARCH_MULTI_V4_V5
 980         bool
 981
 982 config ARCH_MULTI_V6
 983         bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
 984         select ARCH_MULTI_V6_V7
 985         select CPU_V6
 986
 987 config ARCH_MULTI_V7
 988         bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
 989         default y
 990         select ARCH_MULTI_V6_V7
 991         select ARCH_VEXPRESS
 992         select CPU_V7
 993
 994 config ARCH_MULTI_V6_V7
 995         bool
 996
 997 config ARCH_MULTI_CPU_AUTO
 998         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 999         select ARCH_MULTI_V5
1000
1001 endmenu
1002
1003 #
1004 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1005 # Kconfigs may be included either alphabetically (according to the
1006 # plat- suffix) or along side the corresponding mach-* source.
1007 #
1008 source "arch/arm/mach-mvebu/Kconfig"
1009
1010 source "arch/arm/mach-at91/Kconfig"
1011
1012 source "arch/arm/mach-bcm/Kconfig"
1013
1014 source "arch/arm/mach-clps711x/Kconfig"
1015
1016 source "arch/arm/mach-cns3xxx/Kconfig"
1017
1018 source "arch/arm/mach-davinci/Kconfig"
1019
1020 source "arch/arm/mach-dove/Kconfig"
1021
1022 source "arch/arm/mach-ep93xx/Kconfig"
1023
1024 source "arch/arm/mach-footbridge/Kconfig"
1025
1026 source "arch/arm/mach-gemini/Kconfig"
1027
1028 source "arch/arm/mach-h720x/Kconfig"
1029
1030 source "arch/arm/mach-highbank/Kconfig"
1031
1032 source "arch/arm/mach-integrator/Kconfig"
1033
1034 source "arch/arm/mach-iop32x/Kconfig"
1035
1036 source "arch/arm/mach-iop33x/Kconfig"
1037
1038 source "arch/arm/mach-iop13xx/Kconfig"
1039
1040 source "arch/arm/mach-ixp4xx/Kconfig"
1041
1042 source "arch/arm/mach-kirkwood/Kconfig"
1043
1044 source "arch/arm/mach-ks8695/Kconfig"
1045
1046 source "arch/arm/mach-msm/Kconfig"
1047
1048 source "arch/arm/mach-mv78xx0/Kconfig"
1049
1050 source "arch/arm/mach-imx/Kconfig"
1051
1052 source "arch/arm/mach-mxs/Kconfig"
1053
1054 source "arch/arm/mach-netx/Kconfig"
1055
1056 source "arch/arm/mach-nomadik/Kconfig"
1057 source "arch/arm/plat-nomadik/Kconfig"
1058
1059 source "arch/arm/plat-omap/Kconfig"
1060
1061 source "arch/arm/mach-omap1/Kconfig"
1062
1063 source "arch/arm/mach-omap2/Kconfig"
1064
1065 source "arch/arm/mach-orion5x/Kconfig"
1066
1067 source "arch/arm/mach-picoxcell/Kconfig"
1068
1069 source "arch/arm/mach-pxa/Kconfig"
1070 source "arch/arm/plat-pxa/Kconfig"
1071
1072 source "arch/arm/mach-mmp/Kconfig"
1073
1074 source "arch/arm/mach-realview/Kconfig"
1075
1076 source "arch/arm/mach-sa1100/Kconfig"
1077
1078 source "arch/arm/plat-samsung/Kconfig"
1079 source "arch/arm/plat-s3c24xx/Kconfig"
1080
1081 source "arch/arm/mach-socfpga/Kconfig"
1082
1083 source "arch/arm/plat-spear/Kconfig"
1084
1085 source "arch/arm/mach-s3c24xx/Kconfig"
1086 if ARCH_S3C24XX
1087 source "arch/arm/mach-s3c2412/Kconfig"
1088 source "arch/arm/mach-s3c2440/Kconfig"
1089 endif
1090
1091 if ARCH_S3C64XX
1092 source "arch/arm/mach-s3c64xx/Kconfig"
1093 endif
1094
1095 source "arch/arm/mach-s5p64x0/Kconfig"
1096
1097 source "arch/arm/mach-s5pc100/Kconfig"
1098
1099 source "arch/arm/mach-s5pv210/Kconfig"
1100
1101 source "arch/arm/mach-exynos/Kconfig"
1102
1103 source "arch/arm/mach-shmobile/Kconfig"
1104
1105 source "arch/arm/mach-prima2/Kconfig"
1106
1107 source "arch/arm/mach-tegra/Kconfig"
1108
1109 source "arch/arm/mach-u300/Kconfig"
1110
1111 source "arch/arm/mach-ux500/Kconfig"
1112
1113 source "arch/arm/mach-versatile/Kconfig"
1114
1115 source "arch/arm/mach-vexpress/Kconfig"
1116 source "arch/arm/plat-versatile/Kconfig"
1117
1118 source "arch/arm/mach-w90x900/Kconfig"
1119
1120 # Definitions to make life easier
1121 config ARCH_ACORN
1122         bool
1123
1124 config PLAT_IOP
1125         bool
1126         select GENERIC_CLOCKEVENTS
1127
1128 config PLAT_ORION
1129         bool
1130         select CLKSRC_MMIO
1131         select COMMON_CLK
1132         select GENERIC_IRQ_CHIP
1133         select IRQ_DOMAIN
1134
1135 config PLAT_ORION_LEGACY
1136         bool
1137         select PLAT_ORION
1138
1139 config PLAT_PXA
1140         bool
1141
1142 config PLAT_VERSATILE
1143         bool
1144
1145 config ARM_TIMER_SP804
1146         bool
1147         select CLKSRC_MMIO
1148         select HAVE_SCHED_CLOCK
1149
1150 source arch/arm/mm/Kconfig
1151
1152 config ARM_NR_BANKS
1153         int
1154         default 16 if ARCH_EP93XX
1155         default 8
1156
1157 config IWMMXT
1158         bool "Enable iWMMXt support"
1159         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1160         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1161         help
1162           Enable support for iWMMXt context switching at run time if
1163           running on a CPU that supports it.
1164
1165 config XSCALE_PMU
1166         bool
1167         depends on CPU_XSCALE
1168         default y
1169
1170 config MULTI_IRQ_HANDLER
1171         bool
1172         help
1173           Allow each machine to specify it's own IRQ handler at run time.
1174
1175 if !MMU
1176 source "arch/arm/Kconfig-nommu"
1177 endif
1178
1179 config ARM_ERRATA_326103
1180         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1181         depends on CPU_V6
1182         help
1183           Executing a SWP instruction to read-only memory does not set bit 11
1184           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1185           treat the access as a read, preventing a COW from occurring and
1186           causing the faulting task to livelock.
1187
1188 config ARM_ERRATA_411920
1189         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1190         depends on CPU_V6 || CPU_V6K
1191         help
1192           Invalidation of the Instruction Cache operation can
1193           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1194           It does not affect the MPCore. This option enables the ARM Ltd.
1195           recommended workaround.
1196
1197 config ARM_ERRATA_430973
1198         bool "ARM errata: Stale prediction on replaced interworking branch"
1199         depends on CPU_V7
1200         help
1201           This option enables the workaround for the 430973 Cortex-A8
1202           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1203           interworking branch is replaced with another code sequence at the
1204           same virtual address, whether due to self-modifying code or virtual
1205           to physical address re-mapping, Cortex-A8 does not recover from the
1206           stale interworking branch prediction. This results in Cortex-A8
1207           executing the new code sequence in the incorrect ARM or Thumb state.
1208           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1209           and also flushes the branch target cache at every context switch.
1210           Note that setting specific bits in the ACTLR register may not be
1211           available in non-secure mode.
1212
1213 config ARM_ERRATA_458693
1214         bool "ARM errata: Processor deadlock when a false hazard is created"
1215         depends on CPU_V7
1216         help
1217           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1218           erratum. For very specific sequences of memory operations, it is
1219           possible for a hazard condition intended for a cache line to instead
1220           be incorrectly associated with a different cache line. This false
1221           hazard might then cause a processor deadlock. The workaround enables
1222           the L1 caching of the NEON accesses and disables the PLD instruction
1223           in the ACTLR register. Note that setting specific bits in the ACTLR
1224           register may not be available in non-secure mode.
1225
1226 config ARM_ERRATA_460075
1227         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1228         depends on CPU_V7
1229         help
1230           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1231           erratum. Any asynchronous access to the L2 cache may encounter a
1232           situation in which recent store transactions to the L2 cache are lost
1233           and overwritten with stale memory contents from external memory. The
1234           workaround disables the write-allocate mode for the L2 cache via the
1235           ACTLR register. Note that setting specific bits in the ACTLR register
1236           may not be available in non-secure mode.
1237
1238 config ARM_ERRATA_742230
1239         bool "ARM errata: DMB operation may be faulty"
1240         depends on CPU_V7 && SMP
1241         help
1242           This option enables the workaround for the 742230 Cortex-A9
1243           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1244           between two write operations may not ensure the correct visibility
1245           ordering of the two writes. This workaround sets a specific bit in
1246           the diagnostic register of the Cortex-A9 which causes the DMB
1247           instruction to behave as a DSB, ensuring the correct behaviour of
1248           the two writes.
1249
1250 config ARM_ERRATA_742231
1251         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1252         depends on CPU_V7 && SMP
1253         help
1254           This option enables the workaround for the 742231 Cortex-A9
1255           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1256           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1257           accessing some data located in the same cache line, may get corrupted
1258           data due to bad handling of the address hazard when the line gets
1259           replaced from one of the CPUs at the same time as another CPU is
1260           accessing it. This workaround sets specific bits in the diagnostic
1261           register of the Cortex-A9 which reduces the linefill issuing
1262           capabilities of the processor.
1263
1264 config PL310_ERRATA_588369
1265         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1266         depends on CACHE_L2X0
1267         help
1268            The PL310 L2 cache controller implements three types of Clean &
1269            Invalidate maintenance operations: by Physical Address
1270            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1271            They are architecturally defined to behave as the execution of a
1272            clean operation followed immediately by an invalidate operation,
1273            both performing to the same memory location. This functionality
1274            is not correctly implemented in PL310 as clean lines are not
1275            invalidated as a result of these operations.
1276
1277 config ARM_ERRATA_720789
1278         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1279         depends on CPU_V7
1280         help
1281           This option enables the workaround for the 720789 Cortex-A9 (prior to
1282           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1283           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1284           As a consequence of this erratum, some TLB entries which should be
1285           invalidated are not, resulting in an incoherency in the system page
1286           tables. The workaround changes the TLB flushing routines to invalidate
1287           entries regardless of the ASID.
1288
1289 config PL310_ERRATA_727915
1290         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1291         depends on CACHE_L2X0
1292         help
1293           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1294           operation (offset 0x7FC). This operation runs in background so that
1295           PL310 can handle normal accesses while it is in progress. Under very
1296           rare circumstances, due to this erratum, write data can be lost when
1297           PL310 treats a cacheable write transaction during a Clean &
1298           Invalidate by Way operation.
1299
1300 config ARM_ERRATA_743622
1301         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1302         depends on CPU_V7
1303         help
1304           This option enables the workaround for the 743622 Cortex-A9
1305           (r2p*) erratum. Under very rare conditions, a faulty
1306           optimisation in the Cortex-A9 Store Buffer may lead to data
1307           corruption. This workaround sets a specific bit in the diagnostic
1308           register of the Cortex-A9 which disables the Store Buffer
1309           optimisation, preventing the defect from occurring. This has no
1310           visible impact on the overall performance or power consumption of the
1311           processor.
1312
1313 config ARM_ERRATA_751472
1314         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1315         depends on CPU_V7
1316         help
1317           This option enables the workaround for the 751472 Cortex-A9 (prior
1318           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1319           completion of a following broadcasted operation if the second
1320           operation is received by a CPU before the ICIALLUIS has completed,
1321           potentially leading to corrupted entries in the cache or TLB.
1322
1323 config PL310_ERRATA_753970
1324         bool "PL310 errata: cache sync operation may be faulty"
1325         depends on CACHE_PL310
1326         help
1327           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1328
1329           Under some condition the effect of cache sync operation on
1330           the store buffer still remains when the operation completes.
1331           This means that the store buffer is always asked to drain and
1332           this prevents it from merging any further writes. The workaround
1333           is to replace the normal offset of cache sync operation (0x730)
1334           by another offset targeting an unmapped PL310 register 0x740.
1335           This has the same effect as the cache sync operation: store buffer
1336           drain and waiting for all buffers empty.
1337
1338 config ARM_ERRATA_754322
1339         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1340         depends on CPU_V7
1341         help
1342           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1343           r3p*) erratum. A speculative memory access may cause a page table walk
1344           which starts prior to an ASID switch but completes afterwards. This
1345           can populate the micro-TLB with a stale entry which may be hit with
1346           the new ASID. This workaround places two dsb instructions in the mm
1347           switching code so that no page table walks can cross the ASID switch.
1348
1349 config ARM_ERRATA_754327
1350         bool "ARM errata: no automatic Store Buffer drain"
1351         depends on CPU_V7 && SMP
1352         help
1353           This option enables the workaround for the 754327 Cortex-A9 (prior to
1354           r2p0) erratum. The Store Buffer does not have any automatic draining
1355           mechanism and therefore a livelock may occur if an external agent
1356           continuously polls a memory location waiting to observe an update.
1357           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1358           written polling loops from denying visibility of updates to memory.
1359
1360 config ARM_ERRATA_364296
1361         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1362         depends on CPU_V6 && !SMP
1363         help
1364           This options enables the workaround for the 364296 ARM1136
1365           r0p2 erratum (possible cache data corruption with
1366           hit-under-miss enabled). It sets the undocumented bit 31 in
1367           the auxiliary control register and the FI bit in the control
1368           register, thus disabling hit-under-miss without putting the
1369           processor into full low interrupt latency mode. ARM11MPCore
1370           is not affected.
1371
1372 config ARM_ERRATA_764369
1373         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1374         depends on CPU_V7 && SMP
1375         help
1376           This option enables the workaround for erratum 764369
1377           affecting Cortex-A9 MPCore with two or more processors (all
1378           current revisions). Under certain timing circumstances, a data
1379           cache line maintenance operation by MVA targeting an Inner
1380           Shareable memory region may fail to proceed up to either the
1381           Point of Coherency or to the Point of Unification of the
1382           system. This workaround adds a DSB instruction before the
1383           relevant cache maintenance functions and sets a specific bit
1384           in the diagnostic control register of the SCU.
1385
1386 config PL310_ERRATA_769419
1387         bool "PL310 errata: no automatic Store Buffer drain"
1388         depends on CACHE_L2X0
1389         help
1390           On revisions of the PL310 prior to r3p2, the Store Buffer does
1391           not automatically drain. This can cause normal, non-cacheable
1392           writes to be retained when the memory system is idle, leading
1393           to suboptimal I/O performance for drivers using coherent DMA.
1394           This option adds a write barrier to the cpu_idle loop so that,
1395           on systems with an outer cache, the store buffer is drained
1396           explicitly.
1397
1398 config ARM_ERRATA_775420
1399        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1400        depends on CPU_V7
1401        help
1402          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1403          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1404          operation aborts with MMU exception, it might cause the processor
1405          to deadlock. This workaround puts DSB before executing ISB if
1406          an abort may occur on cache maintenance.
1407
1408 endmenu
1409
1410 source "arch/arm/common/Kconfig"
1411
1412 menu "Bus support"
1413
1414 config ARM_AMBA
1415         bool
1416
1417 config ISA
1418         bool
1419         help
1420           Find out whether you have ISA slots on your motherboard.  ISA is the
1421           name of a bus system, i.e. the way the CPU talks to the other stuff
1422           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1423           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1424           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1425
1426 # Select ISA DMA controller support
1427 config ISA_DMA
1428         bool
1429         select ISA_DMA_API
1430
1431 # Select ISA DMA interface
1432 config ISA_DMA_API
1433         bool
1434
1435 config PCI
1436         bool "PCI support" if MIGHT_HAVE_PCI
1437         help
1438           Find out whether you have a PCI motherboard. PCI is the name of a
1439           bus system, i.e. the way the CPU talks to the other stuff inside
1440           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1441           VESA. If you have PCI, say Y, otherwise N.
1442
1443 config PCI_DOMAINS
1444         bool
1445         depends on PCI
1446
1447 config PCI_NANOENGINE
1448         bool "BSE nanoEngine PCI support"
1449         depends on SA1100_NANOENGINE
1450         help
1451           Enable PCI on the BSE nanoEngine board.
1452
1453 config PCI_SYSCALL
1454         def_bool PCI
1455
1456 # Select the host bridge type
1457 config PCI_HOST_VIA82C505
1458         bool
1459         depends on PCI && ARCH_SHARK
1460         default y
1461
1462 config PCI_HOST_ITE8152
1463         bool
1464         depends on PCI && MACH_ARMCORE
1465         default y
1466         select DMABOUNCE
1467
1468 source "drivers/pci/Kconfig"
1469
1470 source "drivers/pcmcia/Kconfig"
1471
1472 endmenu
1473
1474 menu "Kernel Features"
1475
1476 config HAVE_SMP
1477         bool
1478         help
1479           This option should be selected by machines which have an SMP-
1480           capable CPU.
1481
1482           The only effect of this option is to make the SMP-related
1483           options available to the user for configuration.
1484
1485 config SMP
1486         bool "Symmetric Multi-Processing"
1487         depends on CPU_V6K || CPU_V7
1488         depends on GENERIC_CLOCKEVENTS
1489         depends on HAVE_SMP
1490         depends on MMU
1491         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1492         select USE_GENERIC_SMP_HELPERS
1493         help
1494           This enables support for systems with more than one CPU. If you have
1495           a system with only one CPU, like most personal computers, say N. If
1496           you have a system with more than one CPU, say Y.
1497
1498           If you say N here, the kernel will run on single and multiprocessor
1499           machines, but will use only one CPU of a multiprocessor machine. If
1500           you say Y here, the kernel will run on many, but not all, single
1501           processor machines. On a single processor machine, the kernel will
1502           run faster if you say N here.
1503
1504           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1505           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1506           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1507
1508           If you don't know what to do here, say N.
1509
1510 config SMP_ON_UP
1511         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1512         depends on EXPERIMENTAL
1513         depends on SMP && !XIP_KERNEL
1514         default y
1515         help
1516           SMP kernels contain instructions which fail on non-SMP processors.
1517           Enabling this option allows the kernel to modify itself to make
1518           these instructions safe.  Disabling it allows about 1K of space
1519           savings.
1520
1521           If you don't know what to do here, say Y.
1522
1523 config ARM_CPU_TOPOLOGY
1524         bool "Support cpu topology definition"
1525         depends on SMP && CPU_V7
1526         default y
1527         help
1528           Support ARM cpu topology definition. The MPIDR register defines
1529           affinity between processors which is then used to describe the cpu
1530           topology of an ARM System.
1531
1532 config SCHED_MC
1533         bool "Multi-core scheduler support"
1534         depends on ARM_CPU_TOPOLOGY
1535         help
1536           Multi-core scheduler support improves the CPU scheduler's decision
1537           making when dealing with multi-core CPU chips at a cost of slightly
1538           increased overhead in some places. If unsure say N here.
1539
1540 config SCHED_SMT
1541         bool "SMT scheduler support"
1542         depends on ARM_CPU_TOPOLOGY
1543         help
1544           Improves the CPU scheduler's decision making when dealing with
1545           MultiThreading at a cost of slightly increased overhead in some
1546           places. If unsure say N here.
1547
1548 config HAVE_ARM_SCU
1549         bool
1550         help
1551           This option enables support for the ARM system coherency unit
1552
1553 config ARM_ARCH_TIMER
1554         bool "Architected timer support"
1555         depends on CPU_V7
1556         help
1557           This option enables support for the ARM architected timer
1558
1559 config HAVE_ARM_TWD
1560         bool
1561         depends on SMP
1562         help
1563           This options enables support for the ARM timer and watchdog unit
1564
1565 choice
1566         prompt "Memory split"
1567         default VMSPLIT_3G
1568         help
1569           Select the desired split between kernel and user memory.
1570
1571           If you are not absolutely sure what you are doing, leave this
1572           option alone!
1573
1574         config VMSPLIT_3G
1575                 bool "3G/1G user/kernel split"
1576         config VMSPLIT_2G
1577                 bool "2G/2G user/kernel split"
1578         config VMSPLIT_1G
1579                 bool "1G/3G user/kernel split"
1580 endchoice
1581
1582 config PAGE_OFFSET
1583         hex
1584         default 0x40000000 if VMSPLIT_1G
1585         default 0x80000000 if VMSPLIT_2G
1586         default 0xC0000000
1587
1588 config NR_CPUS
1589         int "Maximum number of CPUs (2-32)"
1590         range 2 32
1591         depends on SMP
1592         default "4"
1593
1594 config HOTPLUG_CPU
1595         bool "Support for hot-pluggable CPUs"
1596         depends on SMP && HOTPLUG
1597         help
1598           Say Y here to experiment with turning CPUs off and on.  CPUs
1599           can be controlled through /sys/devices/system/cpu.
1600
1601 config LOCAL_TIMERS
1602         bool "Use local timer interrupts"
1603         depends on SMP
1604         default y
1605         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1606         help
1607           Enable support for local timers on SMP platforms, rather then the
1608           legacy IPI broadcast method.  Local timers allows the system
1609           accounting to be spread across the timer interval, preventing a
1610           "thundering herd" at every timer tick.
1611
1612 config ARCH_NR_GPIO
1613         int
1614         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1615         default 355 if ARCH_U8500
1616         default 264 if MACH_H4700
1617         default 512 if SOC_OMAP5
1618         default 288 if ARCH_VT8500
1619         default 0
1620         help
1621           Maximum number of GPIOs in the system.
1622
1623           If unsure, leave the default value.
1624
1625 source kernel/Kconfig.preempt
1626
1627 config HZ
1628         int
1629         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1630                 ARCH_S5PV210 || ARCH_EXYNOS4
1631         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1632         default AT91_TIMER_HZ if ARCH_AT91
1633         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1634         default 100
1635
1636 config THUMB2_KERNEL
1637         bool "Compile the kernel in Thumb-2 mode"
1638         depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1639         select AEABI
1640         select ARM_ASM_UNIFIED
1641         select ARM_UNWIND
1642         help
1643           By enabling this option, the kernel will be compiled in
1644           Thumb-2 mode. A compiler/assembler that understand the unified
1645           ARM-Thumb syntax is needed.
1646
1647           If unsure, say N.
1648
1649 config THUMB2_AVOID_R_ARM_THM_JUMP11
1650         bool "Work around buggy Thumb-2 short branch relocations in gas"
1651         depends on THUMB2_KERNEL && MODULES
1652         default y
1653         help
1654           Various binutils versions can resolve Thumb-2 branches to
1655           locally-defined, preemptible global symbols as short-range "b.n"
1656           branch instructions.
1657
1658           This is a problem, because there's no guarantee the final
1659           destination of the symbol, or any candidate locations for a
1660           trampoline, are within range of the branch.  For this reason, the
1661           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1662           relocation in modules at all, and it makes little sense to add
1663           support.
1664
1665           The symptom is that the kernel fails with an "unsupported
1666           relocation" error when loading some modules.
1667
1668           Until fixed tools are available, passing
1669           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1670           code which hits this problem, at the cost of a bit of extra runtime
1671           stack usage in some cases.
1672
1673           The problem is described in more detail at:
1674               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1675
1676           Only Thumb-2 kernels are affected.
1677
1678           Unless you are sure your tools don't have this problem, say Y.
1679
1680 config ARM_ASM_UNIFIED
1681         bool
1682
1683 config AEABI
1684         bool "Use the ARM EABI to compile the kernel"
1685         help
1686           This option allows for the kernel to be compiled using the latest
1687           ARM ABI (aka EABI).  This is only useful if you are using a user
1688           space environment that is also compiled with EABI.
1689
1690           Since there are major incompatibilities between the legacy ABI and
1691           EABI, especially with regard to structure member alignment, this
1692           option also changes the kernel syscall calling convention to
1693           disambiguate both ABIs and allow for backward compatibility support
1694           (selected with CONFIG_OABI_COMPAT).
1695
1696           To use this you need GCC version 4.0.0 or later.
1697
1698 config OABI_COMPAT
1699         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1700         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1701         default y
1702         help
1703           This option preserves the old syscall interface along with the
1704           new (ARM EABI) one. It also provides a compatibility layer to
1705           intercept syscalls that have structure arguments which layout
1706           in memory differs between the legacy ABI and the new ARM EABI
1707           (only for non "thumb" binaries). This option adds a tiny
1708           overhead to all syscalls and produces a slightly larger kernel.
1709           If you know you'll be using only pure EABI user space then you
1710           can say N here. If this option is not selected and you attempt
1711           to execute a legacy ABI binary then the result will be
1712           UNPREDICTABLE (in fact it can be predicted that it won't work
1713           at all). If in doubt say Y.
1714
1715 config ARCH_HAS_HOLES_MEMORYMODEL
1716         bool
1717
1718 config ARCH_SPARSEMEM_ENABLE
1719         bool
1720
1721 config ARCH_SPARSEMEM_DEFAULT
1722         def_bool ARCH_SPARSEMEM_ENABLE
1723
1724 config ARCH_SELECT_MEMORY_MODEL
1725         def_bool ARCH_SPARSEMEM_ENABLE
1726
1727 config HAVE_ARCH_PFN_VALID
1728         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1729
1730 config HIGHMEM
1731         bool "High Memory Support"
1732         depends on MMU
1733         help
1734           The address space of ARM processors is only 4 Gigabytes large
1735           and it has to accommodate user address space, kernel address
1736           space as well as some memory mapped IO. That means that, if you
1737           have a large amount of physical memory and/or IO, not all of the
1738           memory can be "permanently mapped" by the kernel. The physical
1739           memory that is not permanently mapped is called "high memory".
1740
1741           Depending on the selected kernel/user memory split, minimum
1742           vmalloc space and actual amount of RAM, you may not need this
1743           option which should result in a slightly faster kernel.
1744
1745           If unsure, say n.
1746
1747 config HIGHPTE
1748         bool "Allocate 2nd-level pagetables from highmem"
1749         depends on HIGHMEM
1750
1751 config HW_PERF_EVENTS
1752         bool "Enable hardware performance counter support for perf events"
1753         depends on PERF_EVENTS
1754         default y
1755         help
1756           Enable hardware performance counter support for perf events. If
1757           disabled, perf events will use software events only.
1758
1759 source "mm/Kconfig"
1760
1761 config FORCE_MAX_ZONEORDER
1762         int "Maximum zone order" if ARCH_SHMOBILE
1763         range 11 64 if ARCH_SHMOBILE
1764         default "12" if SOC_AM33XX
1765         default "9" if SA1111
1766         default "11"
1767         help
1768           The kernel memory allocator divides physically contiguous memory
1769           blocks into "zones", where each zone is a power of two number of
1770           pages.  This option selects the largest power of two that the kernel
1771           keeps in the memory allocator.  If you need to allocate very large
1772           blocks of physically contiguous memory, then you may need to
1773           increase this value.
1774
1775           This config option is actually maximum order plus one. For example,
1776           a value of 11 means that the largest free memory block is 2^10 pages.
1777
1778 config ALIGNMENT_TRAP
1779         bool
1780         depends on CPU_CP15_MMU
1781         default y if !ARCH_EBSA110
1782         select HAVE_PROC_CPU if PROC_FS
1783         help
1784           ARM processors cannot fetch/store information which is not
1785           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1786           address divisible by 4. On 32-bit ARM processors, these non-aligned
1787           fetch/store instructions will be emulated in software if you say
1788           here, which has a severe performance impact. This is necessary for
1789           correct operation of some network protocols. With an IP-only
1790           configuration it is safe to say N, otherwise say Y.
1791
1792 config UACCESS_WITH_MEMCPY
1793         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1794         depends on MMU
1795         default y if CPU_FEROCEON
1796         help
1797           Implement faster copy_to_user and clear_user methods for CPU
1798           cores where a 8-word STM instruction give significantly higher
1799           memory write throughput than a sequence of individual 32bit stores.
1800
1801           A possible side effect is a slight increase in scheduling latency
1802           between threads sharing the same address space if they invoke
1803           such copy operations with large buffers.
1804
1805           However, if the CPU data cache is using a write-allocate mode,
1806           this option is unlikely to provide any performance gain.
1807
1808 config SECCOMP
1809         bool
1810         prompt "Enable seccomp to safely compute untrusted bytecode"
1811         ---help---
1812           This kernel feature is useful for number crunching applications
1813           that may need to compute untrusted bytecode during their
1814           execution. By using pipes or other transports made available to
1815           the process as file descriptors supporting the read/write
1816           syscalls, it's possible to isolate those applications in
1817           their own address space using seccomp. Once seccomp is
1818           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1819           and the task is only allowed to execute a few safe syscalls
1820           defined by each seccomp mode.
1821
1822 config CC_STACKPROTECTOR
1823         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1824         depends on EXPERIMENTAL
1825         help
1826           This option turns on the -fstack-protector GCC feature. This
1827           feature puts, at the beginning of functions, a canary value on
1828           the stack just before the return address, and validates
1829           the value just before actually returning.  Stack based buffer
1830           overflows (that need to overwrite this return address) now also
1831           overwrite the canary, which gets detected and the attack is then
1832           neutralized via a kernel panic.
1833           This feature requires gcc version 4.2 or above.
1834
1835 config XEN_DOM0
1836         def_bool y
1837         depends on XEN
1838
1839 config XEN
1840         bool "Xen guest support on ARM (EXPERIMENTAL)"
1841         depends on EXPERIMENTAL && ARM && OF
1842         depends on CPU_V7 && !CPU_V6
1843         help
1844           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1845
1846 endmenu
1847
1848 menu "Boot options"
1849
1850 config USE_OF
1851         bool "Flattened Device Tree support"
1852         select IRQ_DOMAIN
1853         select OF
1854         select OF_EARLY_FLATTREE
1855         help
1856           Include support for flattened device tree machine descriptions.
1857
1858 config ATAGS
1859         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1860         default y
1861         help
1862           This is the traditional way of passing data to the kernel at boot
1863           time. If you are solely relying on the flattened device tree (or
1864           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1865           to remove ATAGS support from your kernel binary.  If unsure,
1866           leave this to y.
1867
1868 config DEPRECATED_PARAM_STRUCT
1869         bool "Provide old way to pass kernel parameters"
1870         depends on ATAGS
1871         help
1872           This was deprecated in 2001 and announced to live on for 5 years.
1873           Some old boot loaders still use this way.
1874
1875 # Compressed boot loader in ROM.  Yes, we really want to ask about
1876 # TEXT and BSS so we preserve their values in the config files.
1877 config ZBOOT_ROM_TEXT
1878         hex "Compressed ROM boot loader base address"
1879         default "0"
1880         help
1881           The physical address at which the ROM-able zImage is to be
1882           placed in the target.  Platforms which normally make use of
1883           ROM-able zImage formats normally set this to a suitable
1884           value in their defconfig file.
1885
1886           If ZBOOT_ROM is not enabled, this has no effect.
1887
1888 config ZBOOT_ROM_BSS
1889         hex "Compressed ROM boot loader BSS address"
1890         default "0"
1891         help
1892           The base address of an area of read/write memory in the target
1893           for the ROM-able zImage which must be available while the
1894           decompressor is running. It must be large enough to hold the
1895           entire decompressed kernel plus an additional 128 KiB.
1896           Platforms which normally make use of ROM-able zImage formats
1897           normally set this to a suitable value in their defconfig file.
1898
1899           If ZBOOT_ROM is not enabled, this has no effect.
1900
1901 config ZBOOT_ROM
1902         bool "Compressed boot loader in ROM/flash"
1903         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1904         help
1905           Say Y here if you intend to execute your compressed kernel image
1906           (zImage) directly from ROM or flash.  If unsure, say N.
1907
1908 choice
1909         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1910         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1911         default ZBOOT_ROM_NONE
1912         help
1913           Include experimental SD/MMC loading code in the ROM-able zImage.
1914           With this enabled it is possible to write the ROM-able zImage
1915           kernel image to an MMC or SD card and boot the kernel straight
1916           from the reset vector. At reset the processor Mask ROM will load
1917           the first part of the ROM-able zImage which in turn loads the
1918           rest the kernel image to RAM.
1919
1920 config ZBOOT_ROM_NONE
1921         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1922         help
1923           Do not load image from SD or MMC
1924
1925 config ZBOOT_ROM_MMCIF
1926         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1927         help
1928           Load image from MMCIF hardware block.
1929
1930 config ZBOOT_ROM_SH_MOBILE_SDHI
1931         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1932         help
1933           Load image from SDHI hardware block
1934
1935 endchoice
1936
1937 config ARM_APPENDED_DTB
1938         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1939         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1940         help
1941           With this option, the boot code will look for a device tree binary
1942           (DTB) appended to zImage
1943           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1944
1945           This is meant as a backward compatibility convenience for those
1946           systems with a bootloader that can't be upgraded to accommodate
1947           the documented boot protocol using a device tree.
1948
1949           Beware that there is very little in terms of protection against
1950           this option being confused by leftover garbage in memory that might
1951           look like a DTB header after a reboot if no actual DTB is appended
1952           to zImage.  Do not leave this option active in a production kernel
1953           if you don't intend to always append a DTB.  Proper passing of the
1954           location into r2 of a bootloader provided DTB is always preferable
1955           to this option.
1956
1957 config ARM_ATAG_DTB_COMPAT
1958         bool "Supplement the appended DTB with traditional ATAG information"
1959         depends on ARM_APPENDED_DTB
1960         help
1961           Some old bootloaders can't be updated to a DTB capable one, yet
1962           they provide ATAGs with memory configuration, the ramdisk address,
1963           the kernel cmdline string, etc.  Such information is dynamically
1964           provided by the bootloader and can't always be stored in a static
1965           DTB.  To allow a device tree enabled kernel to be used with such
1966           bootloaders, this option allows zImage to extract the information
1967           from the ATAG list and store it at run time into the appended DTB.
1968
1969 choice
1970         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1971         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1972
1973 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1974         bool "Use bootloader kernel arguments if available"
1975         help
1976           Uses the command-line options passed by the boot loader instead of
1977           the device tree bootargs property. If the boot loader doesn't provide
1978           any, the device tree bootargs property will be used.
1979
1980 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1981         bool "Extend with bootloader kernel arguments"
1982         help
1983           The command-line arguments provided by the boot loader will be
1984           appended to the the device tree bootargs property.
1985
1986 endchoice
1987
1988 config CMDLINE
1989         string "Default kernel command string"
1990         default ""
1991         help
1992           On some architectures (EBSA110 and CATS), there is currently no way
1993           for the boot loader to pass arguments to the kernel. For these
1994           architectures, you should supply some command-line options at build
1995           time by entering them here. As a minimum, you should specify the
1996           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1997
1998 choice
1999         prompt "Kernel command line type" if CMDLINE != ""
2000         default CMDLINE_FROM_BOOTLOADER
2001         depends on ATAGS
2002
2003 config CMDLINE_FROM_BOOTLOADER
2004         bool "Use bootloader kernel arguments if available"
2005         help
2006           Uses the command-line options passed by the boot loader. If
2007           the boot loader doesn't provide any, the default kernel command
2008           string provided in CMDLINE will be used.
2009
2010 config CMDLINE_EXTEND
2011         bool "Extend bootloader kernel arguments"
2012         help
2013           The command-line arguments provided by the boot loader will be
2014           appended to the default kernel command string.
2015
2016 config CMDLINE_FORCE
2017         bool "Always use the default kernel command string"
2018         help
2019           Always use the default kernel command string, even if the boot
2020           loader passes other arguments to the kernel.
2021           This is useful if you cannot or don't want to change the
2022           command-line options your boot loader passes to the kernel.
2023 endchoice
2024
2025 config XIP_KERNEL
2026         bool "Kernel Execute-In-Place from ROM"
2027         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2028         help
2029           Execute-In-Place allows the kernel to run from non-volatile storage
2030           directly addressable by the CPU, such as NOR flash. This saves RAM
2031           space since the text section of the kernel is not loaded from flash
2032           to RAM.  Read-write sections, such as the data section and stack,
2033           are still copied to RAM.  The XIP kernel is not compressed since
2034           it has to run directly from flash, so it will take more space to
2035           store it.  The flash address used to link the kernel object files,
2036           and for storing it, is configuration dependent. Therefore, if you
2037           say Y here, you must know the proper physical address where to
2038           store the kernel image depending on your own flash memory usage.
2039
2040           Also note that the make target becomes "make xipImage" rather than
2041           "make zImage" or "make Image".  The final kernel binary to put in
2042           ROM memory will be arch/arm/boot/xipImage.
2043
2044           If unsure, say N.
2045
2046 config XIP_PHYS_ADDR
2047         hex "XIP Kernel Physical Location"
2048         depends on XIP_KERNEL
2049         default "0x00080000"
2050         help
2051           This is the physical address in your flash memory the kernel will
2052           be linked for and stored to.  This address is dependent on your
2053           own flash usage.
2054
2055 config KEXEC
2056         bool "Kexec system call (EXPERIMENTAL)"
2057         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2058         help
2059           kexec is a system call that implements the ability to shutdown your
2060           current kernel, and to start another kernel.  It is like a reboot
2061           but it is independent of the system firmware.   And like a reboot
2062           you can start any kernel with it, not just Linux.
2063
2064           It is an ongoing process to be certain the hardware in a machine
2065           is properly shutdown, so do not be surprised if this code does not
2066           initially work for you.  It may help to enable device hotplugging
2067           support.
2068
2069 config ATAGS_PROC
2070         bool "Export atags in procfs"
2071         depends on ATAGS && KEXEC
2072         default y
2073         help
2074           Should the atags used to boot the kernel be exported in an "atags"
2075           file in procfs. Useful with kexec.
2076
2077 config CRASH_DUMP
2078         bool "Build kdump crash kernel (EXPERIMENTAL)"
2079         depends on EXPERIMENTAL
2080         help
2081           Generate crash dump after being started by kexec. This should
2082           be normally only set in special crash dump kernels which are
2083           loaded in the main kernel with kexec-tools into a specially
2084           reserved region and then later executed after a crash by
2085           kdump/kexec. The crash dump kernel must be compiled to a
2086           memory address not used by the main kernel
2087
2088           For more details see Documentation/kdump/kdump.txt
2089
2090 config AUTO_ZRELADDR
2091         bool "Auto calculation of the decompressed kernel image address"
2092         depends on !ZBOOT_ROM && !ARCH_U300
2093         help
2094           ZRELADDR is the physical address where the decompressed kernel
2095           image will be placed. If AUTO_ZRELADDR is selected, the address
2096           will be determined at run-time by masking the current IP with
2097           0xf8000000. This assumes the zImage being placed in the first 128MB
2098           from start of memory.
2099
2100 endmenu
2101
2102 menu "CPU Power Management"
2103
2104 if ARCH_HAS_CPUFREQ
2105
2106 source "drivers/cpufreq/Kconfig"
2107
2108 config CPU_FREQ_IMX
2109         tristate "CPUfreq driver for i.MX CPUs"
2110         depends on ARCH_MXC && CPU_FREQ
2111         select CPU_FREQ_TABLE
2112         help
2113           This enables the CPUfreq driver for i.MX CPUs.
2114
2115 config CPU_FREQ_SA1100
2116         bool
2117
2118 config CPU_FREQ_SA1110
2119         bool
2120
2121 config CPU_FREQ_INTEGRATOR
2122         tristate "CPUfreq driver for ARM Integrator CPUs"
2123         depends on ARCH_INTEGRATOR && CPU_FREQ
2124         default y
2125         help
2126           This enables the CPUfreq driver for ARM Integrator CPUs.
2127
2128           For details, take a look at <file:Documentation/cpu-freq>.
2129
2130           If in doubt, say Y.
2131
2132 config CPU_FREQ_PXA
2133         bool
2134         depends on CPU_FREQ && ARCH_PXA && PXA25x
2135         default y
2136         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2137         select CPU_FREQ_TABLE
2138
2139 config CPU_FREQ_S3C
2140         bool
2141         help
2142           Internal configuration node for common cpufreq on Samsung SoC
2143
2144 config CPU_FREQ_S3C24XX
2145         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2146         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2147         select CPU_FREQ_S3C
2148         help
2149           This enables the CPUfreq driver for the Samsung S3C24XX family
2150           of CPUs.
2151
2152           For details, take a look at <file:Documentation/cpu-freq>.
2153
2154           If in doubt, say N.
2155
2156 config CPU_FREQ_S3C24XX_PLL
2157         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2158         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2159         help
2160           Compile in support for changing the PLL frequency from the
2161           S3C24XX series CPUfreq driver. The PLL takes time to settle
2162           after a frequency change, so by default it is not enabled.
2163
2164           This also means that the PLL tables for the selected CPU(s) will
2165           be built which may increase the size of the kernel image.
2166
2167 config CPU_FREQ_S3C24XX_DEBUG
2168         bool "Debug CPUfreq Samsung driver core"
2169         depends on CPU_FREQ_S3C24XX
2170         help
2171           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2172
2173 config CPU_FREQ_S3C24XX_IODEBUG
2174         bool "Debug CPUfreq Samsung driver IO timing"
2175         depends on CPU_FREQ_S3C24XX
2176         help
2177           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2178
2179 config CPU_FREQ_S3C24XX_DEBUGFS
2180         bool "Export debugfs for CPUFreq"
2181         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2182         help
2183           Export status information via debugfs.
2184
2185 endif
2186
2187 source "drivers/cpuidle/Kconfig"
2188
2189 endmenu
2190
2191 menu "Floating point emulation"
2192
2193 comment "At least one emulation must be selected"
2194
2195 config FPE_NWFPE
2196         bool "NWFPE math emulation"
2197         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2198         ---help---
2199           Say Y to include the NWFPE floating point emulator in the kernel.
2200           This is necessary to run most binaries. Linux does not currently
2201           support floating point hardware so you need to say Y here even if
2202           your machine has an FPA or floating point co-processor podule.
2203
2204           You may say N here if you are going to load the Acorn FPEmulator
2205           early in the bootup.
2206
2207 config FPE_NWFPE_XP
2208         bool "Support extended precision"
2209         depends on FPE_NWFPE
2210         help
2211           Say Y to include 80-bit support in the kernel floating-point
2212           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2213           Note that gcc does not generate 80-bit operations by default,
2214           so in most cases this option only enlarges the size of the
2215           floating point emulator without any good reason.
2216
2217           You almost surely want to say N here.
2218
2219 config FPE_FASTFPE
2220         bool "FastFPE math emulation (EXPERIMENTAL)"
2221         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2222         ---help---
2223           Say Y here to include the FAST floating point emulator in the kernel.
2224           This is an experimental much faster emulator which now also has full
2225           precision for the mantissa.  It does not support any exceptions.
2226           It is very simple, and approximately 3-6 times faster than NWFPE.
2227
2228           It should be sufficient for most programs.  It may be not suitable
2229           for scientific calculations, but you have to check this for yourself.
2230           If you do not feel you need a faster FP emulation you should better
2231           choose NWFPE.
2232
2233 config VFP
2234         bool "VFP-format floating point maths"
2235         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2236         help
2237           Say Y to include VFP support code in the kernel. This is needed
2238           if your hardware includes a VFP unit.
2239
2240           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2241           release notes and additional status information.
2242
2243           Say N if your target does not have VFP hardware.
2244
2245 config VFPv3
2246         bool
2247         depends on VFP
2248         default y if CPU_V7
2249
2250 config NEON
2251         bool "Advanced SIMD (NEON) Extension support"
2252         depends on VFPv3 && CPU_V7
2253         help
2254           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2255           Extension.
2256
2257 endmenu
2258
2259 menu "Userspace binary formats"
2260
2261 source "fs/Kconfig.binfmt"
2262
2263 config ARTHUR
2264         tristate "RISC OS personality"
2265         depends on !AEABI
2266         help
2267           Say Y here to include the kernel code necessary if you want to run
2268           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2269           experimental; if this sounds frightening, say N and sleep in peace.
2270           You can also say M here to compile this support as a module (which
2271           will be called arthur).
2272
2273 endmenu
2274
2275 menu "Power management options"
2276
2277 source "kernel/power/Kconfig"
2278
2279 config ARCH_SUSPEND_POSSIBLE
2280         depends on !ARCH_S5PC100
2281         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2282                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2283         def_bool y
2284
2285 config ARM_CPU_SUSPEND
2286         def_bool PM_SLEEP
2287
2288 endmenu
2289
2290 source "net/Kconfig"
2291
2292 source "drivers/Kconfig"
2293
2294 source "fs/Kconfig"
2295
2296 source "arch/arm/Kconfig.debug"
2297
2298 source "security/Kconfig"
2299
2300 source "crypto/Kconfig"
2301
2302 source "lib/Kconfig"