arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAVE_CUSTOM_GPIO_H
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_WANT_IPC_PARSE_VERSION
   9         select BUILDTIME_EXTABLE_SORT if MMU
  10         select CPU_PM if (SUSPEND || CPU_IDLE)
  11         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
  12         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  13         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  14         select GENERIC_IRQ_PROBE
  15         select GENERIC_IRQ_SHOW
  16         select GENERIC_PCI_IOMAP
  17         select GENERIC_SMP_IDLE_THREAD
  18         select GENERIC_IDLE_POLL_SETUP
  19         select GENERIC_STRNCPY_FROM_USER
  20         select GENERIC_STRNLEN_USER
  21         select HARDIRQS_SW_RESEND
  22         select HAVE_AOUT
  23         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  24         select HAVE_ARCH_KGDB
  25         select HAVE_ARCH_SECCOMP_FILTER
  26         select HAVE_ARCH_TRACEHOOK
  27         select HAVE_BPF_JIT
  28         select HAVE_C_RECORDMCOUNT
  29         select HAVE_DEBUG_KMEMLEAK
  30         select HAVE_DMA_API_DEBUG
  31         select HAVE_DMA_ATTRS
  32         select HAVE_DMA_CONTIGUOUS if MMU
  33         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  34         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  35         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  36         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  37         select HAVE_GENERIC_DMA_COHERENT
  38         select HAVE_GENERIC_HARDIRQS
  39         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  40         select HAVE_IDE if PCI || ISA || PCMCIA
  41         select HAVE_KERNEL_GZIP
  42         select HAVE_KERNEL_LZMA
  43         select HAVE_KERNEL_LZO
  44         select HAVE_KERNEL_XZ
  45         select HAVE_KPROBES if !XIP_KERNEL
  46         select HAVE_KRETPROBES if (HAVE_KPROBES)
  47         select HAVE_MEMBLOCK
  48         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  49         select HAVE_PERF_EVENTS
  50         select HAVE_REGS_AND_STACK_ACCESS_API
  51         select HAVE_SYSCALL_TRACEPOINTS
  52         select HAVE_UID16
  53         select KTIME_SCALAR
  54         select PERF_USE_VMALLOC
  55         select RTC_LIB
  56         select SYS_SUPPORTS_APM_EMULATION
  57         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  58         select MODULES_USE_ELF_REL
  59         select CLONE_BACKWARDS
  60         select OLD_SIGSUSPEND3
  61         select OLD_SIGACTION
  62         select HAVE_CONTEXT_TRACKING
  63         help
  64           The ARM series is a line of low-power-consumption RISC chip designs
  65           licensed by ARM Ltd and targeted at embedded applications and
  66           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  67           manufactured, but legacy ARM-based PC hardware remains popular in
  68           Europe.  There is an ARM Linux project with a web page at
  69           <http://www.arm.linux.org.uk/>.
  70
  71 config ARM_HAS_SG_CHAIN
  72         bool
  73
  74 config NEED_SG_DMA_LENGTH
  75         bool
  76
  77 config ARM_DMA_USE_IOMMU
  78         bool
  79         select ARM_HAS_SG_CHAIN
  80         select NEED_SG_DMA_LENGTH
  81
  82 if ARM_DMA_USE_IOMMU
  83
  84 config ARM_DMA_IOMMU_ALIGNMENT
  85         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
  86         range 4 9
  87         default 8
  88         help
  89           DMA mapping framework by default aligns all buffers to the smallest
  90           PAGE_SIZE order which is greater than or equal to the requested buffer
  91           size. This works well for buffers up to a few hundreds kilobytes, but
  92           for larger buffers it just a waste of address space. Drivers which has
  93           relatively small addressing window (like 64Mib) might run out of
  94           virtual space with just a few allocations.
  95
  96           With this parameter you can specify the maximum PAGE_SIZE order for
  97           DMA IOMMU buffers. Larger buffers will be aligned only to this
  98           specified order. The order is expressed as a power of two multiplied
  99           by the PAGE_SIZE.
 100
 101 endif
 102
 103 config HAVE_PWM
 104         bool
 105
 106 config MIGHT_HAVE_PCI
 107         bool
 108
 109 config SYS_SUPPORTS_APM_EMULATION
 110         bool
 111
 112 config GENERIC_GPIO
 113         bool
 114
 115 config HAVE_TCM
 116         bool
 117         select GENERIC_ALLOCATOR
 118
 119 config HAVE_PROC_CPU
 120         bool
 121
 122 config NO_IOPORT
 123         bool
 124
 125 config EISA
 126         bool
 127         ---help---
 128           The Extended Industry Standard Architecture (EISA) bus was
 129           developed as an open alternative to the IBM MicroChannel bus.
 130
 131           The EISA bus provided some of the features of the IBM MicroChannel
 132           bus while maintaining backward compatibility with cards made for
 133           the older ISA bus.  The EISA bus saw limited use between 1988 and
 134           1995 when it was made obsolete by the PCI bus.
 135
 136           Say Y here if you are building a kernel for an EISA-based machine.
 137
 138           Otherwise, say N.
 139
 140 config SBUS
 141         bool
 142
 143 config STACKTRACE_SUPPORT
 144         bool
 145         default y
 146
 147 config HAVE_LATENCYTOP_SUPPORT
 148         bool
 149         depends on !SMP
 150         default y
 151
 152 config LOCKDEP_SUPPORT
 153         bool
 154         default y
 155
 156 config TRACE_IRQFLAGS_SUPPORT
 157         bool
 158         default y
 159
 160 config RWSEM_GENERIC_SPINLOCK
 161         bool
 162         default y
 163
 164 config RWSEM_XCHGADD_ALGORITHM
 165         bool
 166
 167 config ARCH_HAS_ILOG2_U32
 168         bool
 169
 170 config ARCH_HAS_ILOG2_U64
 171         bool
 172
 173 config ARCH_HAS_CPUFREQ
 174         bool
 175         help
 176           Internal node to signify that the ARCH has CPUFREQ support
 177           and that the relevant menu configurations are displayed for
 178           it.
 179
 180 config GENERIC_HWEIGHT
 181         bool
 182         default y
 183
 184 config GENERIC_CALIBRATE_DELAY
 185         bool
 186         default y
 187
 188 config ARCH_MAY_HAVE_PC_FDC
 189         bool
 190
 191 config ZONE_DMA
 192         bool
 193
 194 config NEED_DMA_MAP_STATE
 195        def_bool y
 196
 197 config ARCH_HAS_DMA_SET_COHERENT_MASK
 198         bool
 199
 200 config GENERIC_ISA_DMA
 201         bool
 202
 203 config FIQ
 204         bool
 205
 206 config NEED_RET_TO_USER
 207         bool
 208
 209 config ARCH_MTD_XIP
 210         bool
 211
 212 config VECTORS_BASE
 213         hex
 214         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 215         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 216         default 0x00000000
 217         help
 218           The base address of exception vectors.
 219
 220 config ARM_PATCH_PHYS_VIRT
 221         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 222         default y
 223         depends on !XIP_KERNEL && MMU
 224         depends on !ARCH_REALVIEW || !SPARSEMEM
 225         help
 226           Patch phys-to-virt and virt-to-phys translation functions at
 227           boot and module load time according to the position of the
 228           kernel in system memory.
 229
 230           This can only be used with non-XIP MMU kernels where the base
 231           of physical memory is at a 16MB boundary.
 232
 233           Only disable this option if you know that you do not require
 234           this feature (eg, building a kernel for a single machine) and
 235           you need to shrink the kernel to the minimal size.
 236
 237 config NEED_MACH_GPIO_H
 238         bool
 239         help
 240           Select this when mach/gpio.h is required to provide special
 241           definitions for this platform. The need for mach/gpio.h should
 242           be avoided when possible.
 243
 244 config NEED_MACH_IO_H
 245         bool
 246         help
 247           Select this when mach/io.h is required to provide special
 248           definitions for this platform.  The need for mach/io.h should
 249           be avoided when possible.
 250
 251 config NEED_MACH_MEMORY_H
 252         bool
 253         help
 254           Select this when mach/memory.h is required to provide special
 255           definitions for this platform.  The need for mach/memory.h should
 256           be avoided when possible.
 257
 258 config PHYS_OFFSET
 259         hex "Physical address of main memory" if MMU
 260         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 261         default DRAM_BASE if !MMU
 262         help
 263           Please provide the physical address corresponding to the
 264           location of main memory in your system.
 265
 266 config GENERIC_BUG
 267         def_bool y
 268         depends on BUG
 269
 270 source "init/Kconfig"
 271
 272 source "kernel/Kconfig.freezer"
 273
 274 menu "System Type"
 275
 276 config MMU
 277         bool "MMU-based Paged Memory Management Support"
 278         default y
 279         help
 280           Select if you want MMU-based virtualised addressing space
 281           support by paged memory management. If unsure, say 'Y'.
 282
 283 #
 284 # The "ARM system type" choice list is ordered alphabetically by option
 285 # text.  Please add new entries in the option alphabetic order.
 286 #
 287 choice
 288         prompt "ARM system type"
 289         default ARCH_VERSATILE if !MMU
 290         default ARCH_MULTIPLATFORM if MMU
 291
 292 config ARCH_MULTIPLATFORM
 293         bool "Allow multiple platforms to be selected"
 294         depends on MMU
 295         select ARM_PATCH_PHYS_VIRT
 296         select AUTO_ZRELADDR
 297         select COMMON_CLK
 298         select MULTI_IRQ_HANDLER
 299         select SPARSE_IRQ
 300         select USE_OF
 301
 302 config ARCH_INTEGRATOR
 303         bool "ARM Ltd. Integrator family"
 304         select ARCH_HAS_CPUFREQ
 305         select ARM_AMBA
 306         select COMMON_CLK
 307         select COMMON_CLK_VERSATILE
 308         select GENERIC_CLOCKEVENTS
 309         select HAVE_TCM
 310         select ICST
 311         select MULTI_IRQ_HANDLER
 312         select NEED_MACH_MEMORY_H
 313         select PLAT_VERSATILE
 314         select SPARSE_IRQ
 315         select VERSATILE_FPGA_IRQ
 316         help
 317           Support for ARM's Integrator platform.
 318
 319 config ARCH_REALVIEW
 320         bool "ARM Ltd. RealView family"
 321         select ARCH_WANT_OPTIONAL_GPIOLIB
 322         select ARM_AMBA
 323         select ARM_TIMER_SP804
 324         select COMMON_CLK
 325         select COMMON_CLK_VERSATILE
 326         select GENERIC_CLOCKEVENTS
 327         select GPIO_PL061 if GPIOLIB
 328         select ICST
 329         select NEED_MACH_MEMORY_H
 330         select PLAT_VERSATILE
 331         select PLAT_VERSATILE_CLCD
 332         help
 333           This enables support for ARM Ltd RealView boards.
 334
 335 config ARCH_VERSATILE
 336         bool "ARM Ltd. Versatile family"
 337         select ARCH_WANT_OPTIONAL_GPIOLIB
 338         select ARM_AMBA
 339         select ARM_TIMER_SP804
 340         select ARM_VIC
 341         select CLKDEV_LOOKUP
 342         select GENERIC_CLOCKEVENTS
 343         select HAVE_MACH_CLKDEV
 344         select ICST
 345         select PLAT_VERSATILE
 346         select PLAT_VERSATILE_CLCD
 347         select PLAT_VERSATILE_CLOCK
 348         select VERSATILE_FPGA_IRQ
 349         help
 350           This enables support for ARM Ltd Versatile board.
 351
 352 config ARCH_AT91
 353         bool "Atmel AT91"
 354         select ARCH_REQUIRE_GPIOLIB
 355         select CLKDEV_LOOKUP
 356         select HAVE_CLK
 357         select IRQ_DOMAIN
 358         select NEED_MACH_GPIO_H
 359         select NEED_MACH_IO_H if PCCARD
 360         select PINCTRL
 361         select PINCTRL_AT91 if USE_OF
 362         help
 363           This enables support for systems based on Atmel
 364           AT91RM9200 and AT91SAM9* processors.
 365
 366 config ARCH_CLPS711X
 367         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 368         select ARCH_REQUIRE_GPIOLIB
 369         select AUTO_ZRELADDR
 370         select CLKDEV_LOOKUP
 371         select COMMON_CLK
 372         select CPU_ARM720T
 373         select GENERIC_CLOCKEVENTS
 374         select MULTI_IRQ_HANDLER
 375         select NEED_MACH_MEMORY_H
 376         select SPARSE_IRQ
 377         help
 378           Support for Cirrus Logic 711x/721x/731x based boards.
 379
 380 config ARCH_GEMINI
 381         bool "Cortina Systems Gemini"
 382         select ARCH_REQUIRE_GPIOLIB
 383         select ARCH_USES_GETTIMEOFFSET
 384         select NEED_MACH_GPIO_H
 385         select CPU_FA526
 386         help
 387           Support for the Cortina Systems Gemini family SoCs
 388
 389 config ARCH_EBSA110
 390         bool "EBSA-110"
 391         select ARCH_USES_GETTIMEOFFSET
 392         select CPU_SA110
 393         select ISA
 394         select NEED_MACH_IO_H
 395         select NEED_MACH_MEMORY_H
 396         select NO_IOPORT
 397         help
 398           This is an evaluation board for the StrongARM processor available
 399           from Digital. It has limited hardware on-board, including an
 400           Ethernet interface, two PCMCIA sockets, two serial ports and a
 401           parallel port.
 402
 403 config ARCH_EP93XX
 404         bool "EP93xx-based"
 405         select ARCH_HAS_HOLES_MEMORYMODEL
 406         select ARCH_REQUIRE_GPIOLIB
 407         select ARCH_USES_GETTIMEOFFSET
 408         select ARM_AMBA
 409         select ARM_VIC
 410         select CLKDEV_LOOKUP
 411         select CPU_ARM920T
 412         select NEED_MACH_MEMORY_H
 413         help
 414           This enables support for the Cirrus EP93xx series of CPUs.
 415
 416 config ARCH_FOOTBRIDGE
 417         bool "FootBridge"
 418         select CPU_SA110
 419         select FOOTBRIDGE
 420         select GENERIC_CLOCKEVENTS
 421         select HAVE_IDE
 422         select NEED_MACH_IO_H if !MMU
 423         select NEED_MACH_MEMORY_H
 424         help
 425           Support for systems based on the DC21285 companion chip
 426           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 427
 428 config ARCH_NETX
 429         bool "Hilscher NetX based"
 430         select ARM_VIC
 431         select CLKSRC_MMIO
 432         select CPU_ARM926T
 433         select GENERIC_CLOCKEVENTS
 434         help
 435           This enables support for systems based on the Hilscher NetX Soc
 436
 437 config ARCH_IOP13XX
 438         bool "IOP13xx-based"
 439         depends on MMU
 440         select ARCH_SUPPORTS_MSI
 441         select CPU_XSC3
 442         select NEED_MACH_MEMORY_H
 443         select NEED_RET_TO_USER
 444         select PCI
 445         select PLAT_IOP
 446         select VMSPLIT_1G
 447         help
 448           Support for Intel's IOP13XX (XScale) family of processors.
 449
 450 config ARCH_IOP32X
 451         bool "IOP32x-based"
 452         depends on MMU
 453         select ARCH_REQUIRE_GPIOLIB
 454         select CPU_XSCALE
 455         select NEED_MACH_GPIO_H
 456         select NEED_RET_TO_USER
 457         select PCI
 458         select PLAT_IOP
 459         help
 460           Support for Intel's 80219 and IOP32X (XScale) family of
 461           processors.
 462
 463 config ARCH_IOP33X
 464         bool "IOP33x-based"
 465         depends on MMU
 466         select ARCH_REQUIRE_GPIOLIB
 467         select CPU_XSCALE
 468         select NEED_MACH_GPIO_H
 469         select NEED_RET_TO_USER
 470         select PCI
 471         select PLAT_IOP
 472         help
 473           Support for Intel's IOP33X (XScale) family of processors.
 474
 475 config ARCH_IXP4XX
 476         bool "IXP4xx-based"
 477         depends on MMU
 478         select ARCH_HAS_DMA_SET_COHERENT_MASK
 479         select ARCH_REQUIRE_GPIOLIB
 480         select CLKSRC_MMIO
 481         select CPU_XSCALE
 482         select DMABOUNCE if PCI
 483         select GENERIC_CLOCKEVENTS
 484         select MIGHT_HAVE_PCI
 485         select NEED_MACH_IO_H
 486         select USB_EHCI_BIG_ENDIAN_MMIO
 487         select USB_EHCI_BIG_ENDIAN_DESC
 488         help
 489           Support for Intel's IXP4XX (XScale) family of processors.
 490
 491 config ARCH_DOVE
 492         bool "Marvell Dove"
 493         select ARCH_REQUIRE_GPIOLIB
 494         select CPU_V7
 495         select GENERIC_CLOCKEVENTS
 496         select MIGHT_HAVE_PCI
 497         select PINCTRL
 498         select PINCTRL_DOVE
 499         select PLAT_ORION_LEGACY
 500         select USB_ARCH_HAS_EHCI
 501         help
 502           Support for the Marvell Dove SoC 88AP510
 503
 504 config ARCH_KIRKWOOD
 505         bool "Marvell Kirkwood"
 506         select ARCH_REQUIRE_GPIOLIB
 507         select CPU_FEROCEON
 508         select GENERIC_CLOCKEVENTS
 509         select PCI
 510         select PCI_QUIRKS
 511         select PINCTRL
 512         select PINCTRL_KIRKWOOD
 513         select PLAT_ORION_LEGACY
 514         help
 515           Support for the following Marvell Kirkwood series SoCs:
 516           88F6180, 88F6192 and 88F6281.
 517
 518 config ARCH_MV78XX0
 519         bool "Marvell MV78xx0"
 520         select ARCH_REQUIRE_GPIOLIB
 521         select CPU_FEROCEON
 522         select GENERIC_CLOCKEVENTS
 523         select PCI
 524         select PLAT_ORION_LEGACY
 525         help
 526           Support for the following Marvell MV78xx0 series SoCs:
 527           MV781x0, MV782x0.
 528
 529 config ARCH_ORION5X
 530         bool "Marvell Orion"
 531         depends on MMU
 532         select ARCH_REQUIRE_GPIOLIB
 533         select CPU_FEROCEON
 534         select GENERIC_CLOCKEVENTS
 535         select PCI
 536         select PLAT_ORION_LEGACY
 537         help
 538           Support for the following Marvell Orion 5x series SoCs:
 539           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 540           Orion-2 (5281), Orion-1-90 (6183).
 541
 542 config ARCH_MMP
 543         bool "Marvell PXA168/910/MMP2"
 544         depends on MMU
 545         select ARCH_REQUIRE_GPIOLIB
 546         select CLKDEV_LOOKUP
 547         select GENERIC_ALLOCATOR
 548         select GENERIC_CLOCKEVENTS
 549         select GPIO_PXA
 550         select IRQ_DOMAIN
 551         select NEED_MACH_GPIO_H
 552         select PINCTRL
 553         select PLAT_PXA
 554         select SPARSE_IRQ
 555         help
 556           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 557
 558 config ARCH_KS8695
 559         bool "Micrel/Kendin KS8695"
 560         select ARCH_REQUIRE_GPIOLIB
 561         select CLKSRC_MMIO
 562         select CPU_ARM922T
 563         select GENERIC_CLOCKEVENTS
 564         select NEED_MACH_MEMORY_H
 565         help
 566           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 567           System-on-Chip devices.
 568
 569 config ARCH_W90X900
 570         bool "Nuvoton W90X900 CPU"
 571         select ARCH_REQUIRE_GPIOLIB
 572         select CLKDEV_LOOKUP
 573         select CLKSRC_MMIO
 574         select CPU_ARM926T
 575         select GENERIC_CLOCKEVENTS
 576         help
 577           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 578           At present, the w90x900 has been renamed nuc900, regarding
 579           the ARM series product line, you can login the following
 580           link address to know more.
 581
 582           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 583                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 584
 585 config ARCH_LPC32XX
 586         bool "NXP LPC32XX"
 587         select ARCH_REQUIRE_GPIOLIB
 588         select ARM_AMBA
 589         select CLKDEV_LOOKUP
 590         select CLKSRC_MMIO
 591         select CPU_ARM926T
 592         select GENERIC_CLOCKEVENTS
 593         select HAVE_IDE
 594         select HAVE_PWM
 595         select USB_ARCH_HAS_OHCI
 596         select USE_OF
 597         help
 598           Support for the NXP LPC32XX family of processors
 599
 600 config ARCH_PXA
 601         bool "PXA2xx/PXA3xx-based"
 602         depends on MMU
 603         select ARCH_HAS_CPUFREQ
 604         select ARCH_MTD_XIP
 605         select ARCH_REQUIRE_GPIOLIB
 606         select ARM_CPU_SUSPEND if PM
 607         select AUTO_ZRELADDR
 608         select CLKDEV_LOOKUP
 609         select CLKSRC_MMIO
 610         select GENERIC_CLOCKEVENTS
 611         select GPIO_PXA
 612         select HAVE_IDE
 613         select MULTI_IRQ_HANDLER
 614         select NEED_MACH_GPIO_H
 615         select PLAT_PXA
 616         select SPARSE_IRQ
 617         help
 618           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 619
 620 config ARCH_MSM
 621         bool "Qualcomm MSM"
 622         select ARCH_REQUIRE_GPIOLIB
 623         select CLKDEV_LOOKUP
 624         select GENERIC_CLOCKEVENTS
 625         select HAVE_CLK
 626         help
 627           Support for Qualcomm MSM/QSD based systems.  This runs on the
 628           apps processor of the MSM/QSD and depends on a shared memory
 629           interface to the modem processor which runs the baseband
 630           stack and controls some vital subsystems
 631           (clock and power control, etc).
 632
 633 config ARCH_SHMOBILE
 634         bool "Renesas SH-Mobile / R-Mobile"
 635         select CLKDEV_LOOKUP
 636         select GENERIC_CLOCKEVENTS
 637         select HAVE_ARM_SCU if SMP
 638         select HAVE_ARM_TWD if LOCAL_TIMERS
 639         select HAVE_CLK
 640         select HAVE_MACH_CLKDEV
 641         select HAVE_SMP
 642         select MIGHT_HAVE_CACHE_L2X0
 643         select MULTI_IRQ_HANDLER
 644         select NEED_MACH_MEMORY_H
 645         select NO_IOPORT
 646         select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
 647         select PM_GENERIC_DOMAINS if PM
 648         select SPARSE_IRQ
 649         help
 650           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 651
 652 config ARCH_RPC
 653         bool "RiscPC"
 654         select ARCH_ACORN
 655         select ARCH_MAY_HAVE_PC_FDC
 656         select ARCH_SPARSEMEM_ENABLE
 657         select ARCH_USES_GETTIMEOFFSET
 658         select FIQ
 659         select HAVE_IDE
 660         select HAVE_PATA_PLATFORM
 661         select ISA_DMA_API
 662         select NEED_MACH_IO_H
 663         select NEED_MACH_MEMORY_H
 664         select NO_IOPORT
 665         select VIRT_TO_BUS
 666         help
 667           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 668           CD-ROM interface, serial and parallel port, and the floppy drive.
 669
 670 config ARCH_SA1100
 671         bool "SA1100-based"
 672         select ARCH_HAS_CPUFREQ
 673         select ARCH_MTD_XIP
 674         select ARCH_REQUIRE_GPIOLIB
 675         select ARCH_SPARSEMEM_ENABLE
 676         select CLKDEV_LOOKUP
 677         select CLKSRC_MMIO
 678         select CPU_FREQ
 679         select CPU_SA1100
 680         select GENERIC_CLOCKEVENTS
 681         select HAVE_IDE
 682         select ISA
 683         select NEED_MACH_GPIO_H
 684         select NEED_MACH_MEMORY_H
 685         select SPARSE_IRQ
 686         help
 687           Support for StrongARM 11x0 based boards.
 688
 689 config ARCH_S3C24XX
 690         bool "Samsung S3C24XX SoCs"
 691         select ARCH_HAS_CPUFREQ
 692         select ARCH_REQUIRE_GPIOLIB
 693         select CLKDEV_LOOKUP
 694         select CLKSRC_MMIO
 695         select GENERIC_CLOCKEVENTS
 696         select HAVE_CLK
 697         select HAVE_S3C2410_I2C if I2C
 698         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 699         select HAVE_S3C_RTC if RTC_CLASS
 700         select MULTI_IRQ_HANDLER
 701         select NEED_MACH_GPIO_H
 702         select NEED_MACH_IO_H
 703         help
 704           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 705           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 706           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 707           Samsung SMDK2410 development board (and derivatives).
 708
 709 config ARCH_S3C64XX
 710         bool "Samsung S3C64XX"
 711         select ARCH_HAS_CPUFREQ
 712         select ARCH_REQUIRE_GPIOLIB
 713         select ARM_VIC
 714         select CLKDEV_LOOKUP
 715         select CLKSRC_MMIO
 716         select CPU_V6
 717         select GENERIC_CLOCKEVENTS
 718         select HAVE_CLK
 719         select HAVE_S3C2410_I2C if I2C
 720         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 721         select HAVE_TCM
 722         select NEED_MACH_GPIO_H
 723         select NO_IOPORT
 724         select PLAT_SAMSUNG
 725         select S3C_DEV_NAND
 726         select S3C_GPIO_TRACK
 727         select SAMSUNG_CLKSRC
 728         select SAMSUNG_GPIOLIB_4BIT
 729         select SAMSUNG_IRQ_VIC_TIMER
 730         select USB_ARCH_HAS_OHCI
 731         help
 732           Samsung S3C64XX series based systems
 733
 734 config ARCH_S5P64X0
 735         bool "Samsung S5P6440 S5P6450"
 736         select CLKDEV_LOOKUP
 737         select CLKSRC_MMIO
 738         select CPU_V6
 739         select GENERIC_CLOCKEVENTS
 740         select HAVE_CLK
 741         select HAVE_S3C2410_I2C if I2C
 742         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 743         select HAVE_S3C_RTC if RTC_CLASS
 744         select NEED_MACH_GPIO_H
 745         help
 746           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 747           SMDK6450.
 748
 749 config ARCH_S5PC100
 750         bool "Samsung S5PC100"
 751         select ARCH_REQUIRE_GPIOLIB
 752         select CLKDEV_LOOKUP
 753         select CLKSRC_MMIO
 754         select CPU_V7
 755         select GENERIC_CLOCKEVENTS
 756         select HAVE_CLK
 757         select HAVE_S3C2410_I2C if I2C
 758         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 759         select HAVE_S3C_RTC if RTC_CLASS
 760         select NEED_MACH_GPIO_H
 761         help
 762           Samsung S5PC100 series based systems
 763
 764 config ARCH_S5PV210
 765         bool "Samsung S5PV210/S5PC110"
 766         select ARCH_HAS_CPUFREQ
 767         select ARCH_HAS_HOLES_MEMORYMODEL
 768         select ARCH_SPARSEMEM_ENABLE
 769         select CLKDEV_LOOKUP
 770         select CLKSRC_MMIO
 771         select CPU_V7
 772         select GENERIC_CLOCKEVENTS
 773         select HAVE_CLK
 774         select HAVE_S3C2410_I2C if I2C
 775         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 776         select HAVE_S3C_RTC if RTC_CLASS
 777         select NEED_MACH_GPIO_H
 778         select NEED_MACH_MEMORY_H
 779         help
 780           Samsung S5PV210/S5PC110 series based systems
 781
 782 config ARCH_EXYNOS
 783         bool "Samsung EXYNOS"
 784         select ARCH_HAS_CPUFREQ
 785         select ARCH_HAS_HOLES_MEMORYMODEL
 786         select ARCH_SPARSEMEM_ENABLE
 787         select CLKDEV_LOOKUP
 788         select COMMON_CLK
 789         select CPU_V7
 790         select GENERIC_CLOCKEVENTS
 791         select HAVE_CLK
 792         select HAVE_S3C2410_I2C if I2C
 793         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 794         select HAVE_S3C_RTC if RTC_CLASS
 795         select NEED_MACH_GPIO_H
 796         select NEED_MACH_MEMORY_H
 797         help
 798           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 799
 800 config ARCH_SHARK
 801         bool "Shark"
 802         select ARCH_USES_GETTIMEOFFSET
 803         select CPU_SA110
 804         select ISA
 805         select ISA_DMA
 806         select NEED_MACH_MEMORY_H
 807         select PCI
 808         select VIRT_TO_BUS
 809         select ZONE_DMA
 810         help
 811           Support for the StrongARM based Digital DNARD machine, also known
 812           as "Shark" (<http://www.shark-linux.de/shark.html>).
 813
 814 config ARCH_U300
 815         bool "ST-Ericsson U300 Series"
 816         depends on MMU
 817         select ARCH_REQUIRE_GPIOLIB
 818         select ARM_AMBA
 819         select ARM_PATCH_PHYS_VIRT
 820         select ARM_VIC
 821         select CLKDEV_LOOKUP
 822         select CLKSRC_MMIO
 823         select COMMON_CLK
 824         select CPU_ARM926T
 825         select GENERIC_CLOCKEVENTS
 826         select HAVE_TCM
 827         select SPARSE_IRQ
 828         help
 829           Support for ST-Ericsson U300 series mobile platforms.
 830
 831 config ARCH_DAVINCI
 832         bool "TI DaVinci"
 833         select ARCH_HAS_HOLES_MEMORYMODEL
 834         select ARCH_REQUIRE_GPIOLIB
 835         select CLKDEV_LOOKUP
 836         select GENERIC_ALLOCATOR
 837         select GENERIC_CLOCKEVENTS
 838         select GENERIC_IRQ_CHIP
 839         select HAVE_IDE
 840         select NEED_MACH_GPIO_H
 841         select USE_OF
 842         select ZONE_DMA
 843         help
 844           Support for TI's DaVinci platform.
 845
 846 config ARCH_OMAP1
 847         bool "TI OMAP1"
 848         depends on MMU
 849         select ARCH_HAS_CPUFREQ
 850         select ARCH_HAS_HOLES_MEMORYMODEL
 851         select ARCH_OMAP
 852         select ARCH_REQUIRE_GPIOLIB
 853         select CLKDEV_LOOKUP
 854         select CLKSRC_MMIO
 855         select GENERIC_CLOCKEVENTS
 856         select GENERIC_IRQ_CHIP
 857         select HAVE_CLK
 858         select HAVE_IDE
 859         select IRQ_DOMAIN
 860         select NEED_MACH_IO_H if PCCARD
 861         select NEED_MACH_MEMORY_H
 862         help
 863           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 864
 865 endchoice
 866
 867 menu "Multiple platform selection"
 868         depends on ARCH_MULTIPLATFORM
 869
 870 comment "CPU Core family selection"
 871
 872 config ARCH_MULTI_V4
 873         bool "ARMv4 based platforms (FA526, StrongARM)"
 874         depends on !ARCH_MULTI_V6_V7
 875         select ARCH_MULTI_V4_V5
 876
 877 config ARCH_MULTI_V4T
 878         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 879         depends on !ARCH_MULTI_V6_V7
 880         select ARCH_MULTI_V4_V5
 881
 882 config ARCH_MULTI_V5
 883         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 884         depends on !ARCH_MULTI_V6_V7
 885         select ARCH_MULTI_V4_V5
 886
 887 config ARCH_MULTI_V4_V5
 888         bool
 889
 890 config ARCH_MULTI_V6
 891         bool "ARMv6 based platforms (ARM11)"
 892         select ARCH_MULTI_V6_V7
 893         select CPU_V6
 894
 895 config ARCH_MULTI_V7
 896         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 897         default y
 898         select ARCH_MULTI_V6_V7
 899         select ARCH_VEXPRESS
 900         select CPU_V7
 901
 902 config ARCH_MULTI_V6_V7
 903         bool
 904
 905 config ARCH_MULTI_CPU_AUTO
 906         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 907         select ARCH_MULTI_V5
 908
 909 endmenu
 910
 911 #
 912 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 913 # Kconfigs may be included either alphabetically (according to the
 914 # plat- suffix) or along side the corresponding mach-* source.
 915 #
 916 source "arch/arm/mach-mvebu/Kconfig"
 917
 918 source "arch/arm/mach-at91/Kconfig"
 919
 920 source "arch/arm/mach-bcm/Kconfig"
 921
 922 source "arch/arm/mach-bcm2835/Kconfig"
 923
 924 source "arch/arm/mach-clps711x/Kconfig"
 925
 926 source "arch/arm/mach-cns3xxx/Kconfig"
 927
 928 source "arch/arm/mach-davinci/Kconfig"
 929
 930 source "arch/arm/mach-dove/Kconfig"
 931
 932 source "arch/arm/mach-ep93xx/Kconfig"
 933
 934 source "arch/arm/mach-footbridge/Kconfig"
 935
 936 source "arch/arm/mach-gemini/Kconfig"
 937
 938 source "arch/arm/mach-highbank/Kconfig"
 939
 940 source "arch/arm/mach-integrator/Kconfig"
 941
 942 source "arch/arm/mach-iop32x/Kconfig"
 943
 944 source "arch/arm/mach-iop33x/Kconfig"
 945
 946 source "arch/arm/mach-iop13xx/Kconfig"
 947
 948 source "arch/arm/mach-ixp4xx/Kconfig"
 949
 950 source "arch/arm/mach-kirkwood/Kconfig"
 951
 952 source "arch/arm/mach-ks8695/Kconfig"
 953
 954 source "arch/arm/mach-msm/Kconfig"
 955
 956 source "arch/arm/mach-mv78xx0/Kconfig"
 957
 958 source "arch/arm/mach-imx/Kconfig"
 959
 960 source "arch/arm/mach-mxs/Kconfig"
 961
 962 source "arch/arm/mach-netx/Kconfig"
 963
 964 source "arch/arm/mach-nomadik/Kconfig"
 965
 966 source "arch/arm/plat-omap/Kconfig"
 967
 968 source "arch/arm/mach-omap1/Kconfig"
 969
 970 source "arch/arm/mach-omap2/Kconfig"
 971
 972 source "arch/arm/mach-orion5x/Kconfig"
 973
 974 source "arch/arm/mach-picoxcell/Kconfig"
 975
 976 source "arch/arm/mach-pxa/Kconfig"
 977 source "arch/arm/plat-pxa/Kconfig"
 978
 979 source "arch/arm/mach-mmp/Kconfig"
 980
 981 source "arch/arm/mach-realview/Kconfig"
 982
 983 source "arch/arm/mach-sa1100/Kconfig"
 984
 985 source "arch/arm/plat-samsung/Kconfig"
 986
 987 source "arch/arm/mach-socfpga/Kconfig"
 988
 989 source "arch/arm/mach-spear/Kconfig"
 990
 991 source "arch/arm/mach-s3c24xx/Kconfig"
 992
 993 if ARCH_S3C64XX
 994 source "arch/arm/mach-s3c64xx/Kconfig"
 995 endif
 996
 997 source "arch/arm/mach-s5p64x0/Kconfig"
 998
 999 source "arch/arm/mach-s5pc100/Kconfig"
1000
1001 source "arch/arm/mach-s5pv210/Kconfig"
1002
1003 source "arch/arm/mach-exynos/Kconfig"
1004
1005 source "arch/arm/mach-shmobile/Kconfig"
1006
1007 source "arch/arm/mach-sunxi/Kconfig"
1008
1009 source "arch/arm/mach-prima2/Kconfig"
1010
1011 source "arch/arm/mach-tegra/Kconfig"
1012
1013 source "arch/arm/mach-u300/Kconfig"
1014
1015 source "arch/arm/mach-ux500/Kconfig"
1016
1017 source "arch/arm/mach-versatile/Kconfig"
1018
1019 source "arch/arm/mach-vexpress/Kconfig"
1020 source "arch/arm/plat-versatile/Kconfig"
1021
1022 source "arch/arm/mach-virt/Kconfig"
1023
1024 source "arch/arm/mach-vt8500/Kconfig"
1025
1026 source "arch/arm/mach-w90x900/Kconfig"
1027
1028 source "arch/arm/mach-zynq/Kconfig"
1029
1030 # Definitions to make life easier
1031 config ARCH_ACORN
1032         bool
1033
1034 config PLAT_IOP
1035         bool
1036         select GENERIC_CLOCKEVENTS
1037
1038 config PLAT_ORION
1039         bool
1040         select CLKSRC_MMIO
1041         select COMMON_CLK
1042         select GENERIC_IRQ_CHIP
1043         select IRQ_DOMAIN
1044
1045 config PLAT_ORION_LEGACY
1046         bool
1047         select PLAT_ORION
1048
1049 config PLAT_PXA
1050         bool
1051
1052 config PLAT_VERSATILE
1053         bool
1054
1055 config ARM_TIMER_SP804
1056         bool
1057         select CLKSRC_MMIO
1058
1059 source arch/arm/mm/Kconfig
1060
1061 config ARM_NR_BANKS
1062         int
1063         default 16 if ARCH_EP93XX
1064         default 8
1065
1066 config IWMMXT
1067         bool "Enable iWMMXt support" if !CPU_PJ4
1068         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1069         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1070         help
1071           Enable support for iWMMXt context switching at run time if
1072           running on a CPU that supports it.
1073
1074 config XSCALE_PMU
1075         bool
1076         depends on CPU_XSCALE
1077         default y
1078
1079 config MULTI_IRQ_HANDLER
1080         bool
1081         help
1082           Allow each machine to specify it's own IRQ handler at run time.
1083
1084 if !MMU
1085 source "arch/arm/Kconfig-nommu"
1086 endif
1087
1088 config ARM_ERRATA_326103
1089         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1090         depends on CPU_V6
1091         help
1092           Executing a SWP instruction to read-only memory does not set bit 11
1093           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1094           treat the access as a read, preventing a COW from occurring and
1095           causing the faulting task to livelock.
1096
1097 config ARM_ERRATA_411920
1098         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1099         depends on CPU_V6 || CPU_V6K
1100         help
1101           Invalidation of the Instruction Cache operation can
1102           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1103           It does not affect the MPCore. This option enables the ARM Ltd.
1104           recommended workaround.
1105
1106 config ARM_ERRATA_430973
1107         bool "ARM errata: Stale prediction on replaced interworking branch"
1108         depends on CPU_V7
1109         help
1110           This option enables the workaround for the 430973 Cortex-A8
1111           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1112           interworking branch is replaced with another code sequence at the
1113           same virtual address, whether due to self-modifying code or virtual
1114           to physical address re-mapping, Cortex-A8 does not recover from the
1115           stale interworking branch prediction. This results in Cortex-A8
1116           executing the new code sequence in the incorrect ARM or Thumb state.
1117           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1118           and also flushes the branch target cache at every context switch.
1119           Note that setting specific bits in the ACTLR register may not be
1120           available in non-secure mode.
1121
1122 config ARM_ERRATA_458693
1123         bool "ARM errata: Processor deadlock when a false hazard is created"
1124         depends on CPU_V7
1125         depends on !ARCH_MULTIPLATFORM
1126         help
1127           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1128           erratum. For very specific sequences of memory operations, it is
1129           possible for a hazard condition intended for a cache line to instead
1130           be incorrectly associated with a different cache line. This false
1131           hazard might then cause a processor deadlock. The workaround enables
1132           the L1 caching of the NEON accesses and disables the PLD instruction
1133           in the ACTLR register. Note that setting specific bits in the ACTLR
1134           register may not be available in non-secure mode.
1135
1136 config ARM_ERRATA_460075
1137         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1138         depends on CPU_V7
1139         depends on !ARCH_MULTIPLATFORM
1140         help
1141           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1142           erratum. Any asynchronous access to the L2 cache may encounter a
1143           situation in which recent store transactions to the L2 cache are lost
1144           and overwritten with stale memory contents from external memory. The
1145           workaround disables the write-allocate mode for the L2 cache via the
1146           ACTLR register. Note that setting specific bits in the ACTLR register
1147           may not be available in non-secure mode.
1148
1149 config ARM_ERRATA_742230
1150         bool "ARM errata: DMB operation may be faulty"
1151         depends on CPU_V7 && SMP
1152         depends on !ARCH_MULTIPLATFORM
1153         help
1154           This option enables the workaround for the 742230 Cortex-A9
1155           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1156           between two write operations may not ensure the correct visibility
1157           ordering of the two writes. This workaround sets a specific bit in
1158           the diagnostic register of the Cortex-A9 which causes the DMB
1159           instruction to behave as a DSB, ensuring the correct behaviour of
1160           the two writes.
1161
1162 config ARM_ERRATA_742231
1163         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1164         depends on CPU_V7 && SMP
1165         depends on !ARCH_MULTIPLATFORM
1166         help
1167           This option enables the workaround for the 742231 Cortex-A9
1168           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1169           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1170           accessing some data located in the same cache line, may get corrupted
1171           data due to bad handling of the address hazard when the line gets
1172           replaced from one of the CPUs at the same time as another CPU is
1173           accessing it. This workaround sets specific bits in the diagnostic
1174           register of the Cortex-A9 which reduces the linefill issuing
1175           capabilities of the processor.
1176
1177 config PL310_ERRATA_588369
1178         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1179         depends on CACHE_L2X0
1180         help
1181            The PL310 L2 cache controller implements three types of Clean &
1182            Invalidate maintenance operations: by Physical Address
1183            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1184            They are architecturally defined to behave as the execution of a
1185            clean operation followed immediately by an invalidate operation,
1186            both performing to the same memory location. This functionality
1187            is not correctly implemented in PL310 as clean lines are not
1188            invalidated as a result of these operations.
1189
1190 config ARM_ERRATA_720789
1191         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1192         depends on CPU_V7
1193         help
1194           This option enables the workaround for the 720789 Cortex-A9 (prior to
1195           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1196           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1197           As a consequence of this erratum, some TLB entries which should be
1198           invalidated are not, resulting in an incoherency in the system page
1199           tables. The workaround changes the TLB flushing routines to invalidate
1200           entries regardless of the ASID.
1201
1202 config PL310_ERRATA_727915
1203         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1204         depends on CACHE_L2X0
1205         help
1206           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1207           operation (offset 0x7FC). This operation runs in background so that
1208           PL310 can handle normal accesses while it is in progress. Under very
1209           rare circumstances, due to this erratum, write data can be lost when
1210           PL310 treats a cacheable write transaction during a Clean &
1211           Invalidate by Way operation.
1212
1213 config ARM_ERRATA_743622
1214         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1215         depends on CPU_V7
1216         depends on !ARCH_MULTIPLATFORM
1217         help
1218           This option enables the workaround for the 743622 Cortex-A9
1219           (r2p*) erratum. Under very rare conditions, a faulty
1220           optimisation in the Cortex-A9 Store Buffer may lead to data
1221           corruption. This workaround sets a specific bit in the diagnostic
1222           register of the Cortex-A9 which disables the Store Buffer
1223           optimisation, preventing the defect from occurring. This has no
1224           visible impact on the overall performance or power consumption of the
1225           processor.
1226
1227 config ARM_ERRATA_751472
1228         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1229         depends on CPU_V7
1230         depends on !ARCH_MULTIPLATFORM
1231         help
1232           This option enables the workaround for the 751472 Cortex-A9 (prior
1233           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1234           completion of a following broadcasted operation if the second
1235           operation is received by a CPU before the ICIALLUIS has completed,
1236           potentially leading to corrupted entries in the cache or TLB.
1237
1238 config PL310_ERRATA_753970
1239         bool "PL310 errata: cache sync operation may be faulty"
1240         depends on CACHE_PL310
1241         help
1242           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1243
1244           Under some condition the effect of cache sync operation on
1245           the store buffer still remains when the operation completes.
1246           This means that the store buffer is always asked to drain and
1247           this prevents it from merging any further writes. The workaround
1248           is to replace the normal offset of cache sync operation (0x730)
1249           by another offset targeting an unmapped PL310 register 0x740.
1250           This has the same effect as the cache sync operation: store buffer
1251           drain and waiting for all buffers empty.
1252
1253 config ARM_ERRATA_754322
1254         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1255         depends on CPU_V7
1256         help
1257           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1258           r3p*) erratum. A speculative memory access may cause a page table walk
1259           which starts prior to an ASID switch but completes afterwards. This
1260           can populate the micro-TLB with a stale entry which may be hit with
1261           the new ASID. This workaround places two dsb instructions in the mm
1262           switching code so that no page table walks can cross the ASID switch.
1263
1264 config ARM_ERRATA_754327
1265         bool "ARM errata: no automatic Store Buffer drain"
1266         depends on CPU_V7 && SMP
1267         help
1268           This option enables the workaround for the 754327 Cortex-A9 (prior to
1269           r2p0) erratum. The Store Buffer does not have any automatic draining
1270           mechanism and therefore a livelock may occur if an external agent
1271           continuously polls a memory location waiting to observe an update.
1272           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1273           written polling loops from denying visibility of updates to memory.
1274
1275 config ARM_ERRATA_364296
1276         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1277         depends on CPU_V6 && !SMP
1278         help
1279           This options enables the workaround for the 364296 ARM1136
1280           r0p2 erratum (possible cache data corruption with
1281           hit-under-miss enabled). It sets the undocumented bit 31 in
1282           the auxiliary control register and the FI bit in the control
1283           register, thus disabling hit-under-miss without putting the
1284           processor into full low interrupt latency mode. ARM11MPCore
1285           is not affected.
1286
1287 config ARM_ERRATA_764369
1288         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1289         depends on CPU_V7 && SMP
1290         help
1291           This option enables the workaround for erratum 764369
1292           affecting Cortex-A9 MPCore with two or more processors (all
1293           current revisions). Under certain timing circumstances, a data
1294           cache line maintenance operation by MVA targeting an Inner
1295           Shareable memory region may fail to proceed up to either the
1296           Point of Coherency or to the Point of Unification of the
1297           system. This workaround adds a DSB instruction before the
1298           relevant cache maintenance functions and sets a specific bit
1299           in the diagnostic control register of the SCU.
1300
1301 config PL310_ERRATA_769419
1302         bool "PL310 errata: no automatic Store Buffer drain"
1303         depends on CACHE_L2X0
1304         help
1305           On revisions of the PL310 prior to r3p2, the Store Buffer does
1306           not automatically drain. This can cause normal, non-cacheable
1307           writes to be retained when the memory system is idle, leading
1308           to suboptimal I/O performance for drivers using coherent DMA.
1309           This option adds a write barrier to the cpu_idle loop so that,
1310           on systems with an outer cache, the store buffer is drained
1311           explicitly.
1312
1313 config ARM_ERRATA_775420
1314        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1315        depends on CPU_V7
1316        help
1317          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1318          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1319          operation aborts with MMU exception, it might cause the processor
1320          to deadlock. This workaround puts DSB before executing ISB if
1321          an abort may occur on cache maintenance.
1322
1323 config ARM_ERRATA_798181
1324         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1325         depends on CPU_V7 && SMP
1326         help
1327           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1328           adequately shooting down all use of the old entries. This
1329           option enables the Linux kernel workaround for this erratum
1330           which sends an IPI to the CPUs that are running the same ASID
1331           as the one being invalidated.
1332
1333 endmenu
1334
1335 source "arch/arm/common/Kconfig"
1336
1337 menu "Bus support"
1338
1339 config ARM_AMBA
1340         bool
1341
1342 config ISA
1343         bool
1344         help
1345           Find out whether you have ISA slots on your motherboard.  ISA is the
1346           name of a bus system, i.e. the way the CPU talks to the other stuff
1347           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1348           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1349           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1350
1351 # Select ISA DMA controller support
1352 config ISA_DMA
1353         bool
1354         select ISA_DMA_API
1355
1356 # Select ISA DMA interface
1357 config ISA_DMA_API
1358         bool
1359
1360 config PCI
1361         bool "PCI support" if MIGHT_HAVE_PCI
1362         help
1363           Find out whether you have a PCI motherboard. PCI is the name of a
1364           bus system, i.e. the way the CPU talks to the other stuff inside
1365           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1366           VESA. If you have PCI, say Y, otherwise N.
1367
1368 config PCI_DOMAINS
1369         bool
1370         depends on PCI
1371
1372 config PCI_NANOENGINE
1373         bool "BSE nanoEngine PCI support"
1374         depends on SA1100_NANOENGINE
1375         help
1376           Enable PCI on the BSE nanoEngine board.
1377
1378 config PCI_SYSCALL
1379         def_bool PCI
1380
1381 # Select the host bridge type
1382 config PCI_HOST_VIA82C505
1383         bool
1384         depends on PCI && ARCH_SHARK
1385         default y
1386
1387 config PCI_HOST_ITE8152
1388         bool
1389         depends on PCI && MACH_ARMCORE
1390         default y
1391         select DMABOUNCE
1392
1393 source "drivers/pci/Kconfig"
1394
1395 source "drivers/pcmcia/Kconfig"
1396
1397 endmenu
1398
1399 menu "Kernel Features"
1400
1401 config HAVE_SMP
1402         bool
1403         help
1404           This option should be selected by machines which have an SMP-
1405           capable CPU.
1406
1407           The only effect of this option is to make the SMP-related
1408           options available to the user for configuration.
1409
1410 config SMP
1411         bool "Symmetric Multi-Processing"
1412         depends on CPU_V6K || CPU_V7
1413         depends on GENERIC_CLOCKEVENTS
1414         depends on HAVE_SMP
1415         depends on MMU
1416         select USE_GENERIC_SMP_HELPERS
1417         help
1418           This enables support for systems with more than one CPU. If you have
1419           a system with only one CPU, like most personal computers, say N. If
1420           you have a system with more than one CPU, say Y.
1421
1422           If you say N here, the kernel will run on single and multiprocessor
1423           machines, but will use only one CPU of a multiprocessor machine. If
1424           you say Y here, the kernel will run on many, but not all, single
1425           processor machines. On a single processor machine, the kernel will
1426           run faster if you say N here.
1427
1428           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1429           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1430           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1431
1432           If you don't know what to do here, say N.
1433
1434 config SMP_ON_UP
1435         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1436         depends on SMP && !XIP_KERNEL
1437         default y
1438         help
1439           SMP kernels contain instructions which fail on non-SMP processors.
1440           Enabling this option allows the kernel to modify itself to make
1441           these instructions safe.  Disabling it allows about 1K of space
1442           savings.
1443
1444           If you don't know what to do here, say Y.
1445
1446 config ARM_CPU_TOPOLOGY
1447         bool "Support cpu topology definition"
1448         depends on SMP && CPU_V7
1449         default y
1450         help
1451           Support ARM cpu topology definition. The MPIDR register defines
1452           affinity between processors which is then used to describe the cpu
1453           topology of an ARM System.
1454
1455 config SCHED_MC
1456         bool "Multi-core scheduler support"
1457         depends on ARM_CPU_TOPOLOGY
1458         help
1459           Multi-core scheduler support improves the CPU scheduler's decision
1460           making when dealing with multi-core CPU chips at a cost of slightly
1461           increased overhead in some places. If unsure say N here.
1462
1463 config SCHED_SMT
1464         bool "SMT scheduler support"
1465         depends on ARM_CPU_TOPOLOGY
1466         help
1467           Improves the CPU scheduler's decision making when dealing with
1468           MultiThreading at a cost of slightly increased overhead in some
1469           places. If unsure say N here.
1470
1471 config HAVE_ARM_SCU
1472         bool
1473         help
1474           This option enables support for the ARM system coherency unit
1475
1476 config HAVE_ARM_ARCH_TIMER
1477         bool "Architected timer support"
1478         depends on CPU_V7
1479         select ARM_ARCH_TIMER
1480         help
1481           This option enables support for the ARM architected timer
1482
1483 config HAVE_ARM_TWD
1484         bool
1485         depends on SMP
1486         select CLKSRC_OF if OF
1487         help
1488           This options enables support for the ARM timer and watchdog unit
1489
1490 config MCPM
1491         bool "Multi-Cluster Power Management"
1492         depends on CPU_V7 && SMP
1493         help
1494           This option provides the common power management infrastructure
1495           for (multi-)cluster based systems, such as big.LITTLE based
1496           systems.
1497
1498 choice
1499         prompt "Memory split"
1500         default VMSPLIT_3G
1501         help
1502           Select the desired split between kernel and user memory.
1503
1504           If you are not absolutely sure what you are doing, leave this
1505           option alone!
1506
1507         config VMSPLIT_3G
1508                 bool "3G/1G user/kernel split"
1509         config VMSPLIT_2G
1510                 bool "2G/2G user/kernel split"
1511         config VMSPLIT_1G
1512                 bool "1G/3G user/kernel split"
1513 endchoice
1514
1515 config PAGE_OFFSET
1516         hex
1517         default 0x40000000 if VMSPLIT_1G
1518         default 0x80000000 if VMSPLIT_2G
1519         default 0xC0000000
1520
1521 config NR_CPUS
1522         int "Maximum number of CPUs (2-32)"
1523         range 2 32
1524         depends on SMP
1525         default "4"
1526
1527 config HOTPLUG_CPU
1528         bool "Support for hot-pluggable CPUs"
1529         depends on SMP && HOTPLUG
1530         help
1531           Say Y here to experiment with turning CPUs off and on.  CPUs
1532           can be controlled through /sys/devices/system/cpu.
1533
1534 config ARM_PSCI
1535         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1536         depends on CPU_V7
1537         help
1538           Say Y here if you want Linux to communicate with system firmware
1539           implementing the PSCI specification for CPU-centric power
1540           management operations described in ARM document number ARM DEN
1541           0022A ("Power State Coordination Interface System Software on
1542           ARM processors").
1543
1544 config LOCAL_TIMERS
1545         bool "Use local timer interrupts"
1546         depends on SMP
1547         default y
1548         help
1549           Enable support for local timers on SMP platforms, rather then the
1550           legacy IPI broadcast method.  Local timers allows the system
1551           accounting to be spread across the timer interval, preventing a
1552           "thundering herd" at every timer tick.
1553
1554 # The GPIO number here must be sorted by descending number. In case of
1555 # a multiplatform kernel, we just want the highest value required by the
1556 # selected platforms.
1557 config ARCH_NR_GPIO
1558         int
1559         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1560         default 512 if SOC_OMAP5
1561         default 392 if ARCH_U8500
1562         default 352 if ARCH_VT8500
1563         default 288 if ARCH_SUNXI
1564         default 264 if MACH_H4700
1565         default 0
1566         help
1567           Maximum number of GPIOs in the system.
1568
1569           If unsure, leave the default value.
1570
1571 source kernel/Kconfig.preempt
1572
1573 config HZ
1574         int
1575         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1576                 ARCH_S5PV210 || ARCH_EXYNOS4
1577         default AT91_TIMER_HZ if ARCH_AT91
1578         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1579         default 100
1580
1581 config SCHED_HRTICK
1582         def_bool HIGH_RES_TIMERS
1583
1584 config THUMB2_KERNEL
1585         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1586         depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1587         default y if CPU_THUMBONLY
1588         select AEABI
1589         select ARM_ASM_UNIFIED
1590         select ARM_UNWIND
1591         help
1592           By enabling this option, the kernel will be compiled in
1593           Thumb-2 mode. A compiler/assembler that understand the unified
1594           ARM-Thumb syntax is needed.
1595
1596           If unsure, say N.
1597
1598 config THUMB2_AVOID_R_ARM_THM_JUMP11
1599         bool "Work around buggy Thumb-2 short branch relocations in gas"
1600         depends on THUMB2_KERNEL && MODULES
1601         default y
1602         help
1603           Various binutils versions can resolve Thumb-2 branches to
1604           locally-defined, preemptible global symbols as short-range "b.n"
1605           branch instructions.
1606
1607           This is a problem, because there's no guarantee the final
1608           destination of the symbol, or any candidate locations for a
1609           trampoline, are within range of the branch.  For this reason, the
1610           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1611           relocation in modules at all, and it makes little sense to add
1612           support.
1613
1614           The symptom is that the kernel fails with an "unsupported
1615           relocation" error when loading some modules.
1616
1617           Until fixed tools are available, passing
1618           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1619           code which hits this problem, at the cost of a bit of extra runtime
1620           stack usage in some cases.
1621
1622           The problem is described in more detail at:
1623               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1624
1625           Only Thumb-2 kernels are affected.
1626
1627           Unless you are sure your tools don't have this problem, say Y.
1628
1629 config ARM_ASM_UNIFIED
1630         bool
1631
1632 config AEABI
1633         bool "Use the ARM EABI to compile the kernel"
1634         help
1635           This option allows for the kernel to be compiled using the latest
1636           ARM ABI (aka EABI).  This is only useful if you are using a user
1637           space environment that is also compiled with EABI.
1638
1639           Since there are major incompatibilities between the legacy ABI and
1640           EABI, especially with regard to structure member alignment, this
1641           option also changes the kernel syscall calling convention to
1642           disambiguate both ABIs and allow for backward compatibility support
1643           (selected with CONFIG_OABI_COMPAT).
1644
1645           To use this you need GCC version 4.0.0 or later.
1646
1647 config OABI_COMPAT
1648         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1649         depends on AEABI && !THUMB2_KERNEL
1650         default y
1651         help
1652           This option preserves the old syscall interface along with the
1653           new (ARM EABI) one. It also provides a compatibility layer to
1654           intercept syscalls that have structure arguments which layout
1655           in memory differs between the legacy ABI and the new ARM EABI
1656           (only for non "thumb" binaries). This option adds a tiny
1657           overhead to all syscalls and produces a slightly larger kernel.
1658           If you know you'll be using only pure EABI user space then you
1659           can say N here. If this option is not selected and you attempt
1660           to execute a legacy ABI binary then the result will be
1661           UNPREDICTABLE (in fact it can be predicted that it won't work
1662           at all). If in doubt say Y.
1663
1664 config ARCH_HAS_HOLES_MEMORYMODEL
1665         bool
1666
1667 config ARCH_SPARSEMEM_ENABLE
1668         bool
1669
1670 config ARCH_SPARSEMEM_DEFAULT
1671         def_bool ARCH_SPARSEMEM_ENABLE
1672
1673 config ARCH_SELECT_MEMORY_MODEL
1674         def_bool ARCH_SPARSEMEM_ENABLE
1675
1676 config HAVE_ARCH_PFN_VALID
1677         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1678
1679 config HIGHMEM
1680         bool "High Memory Support"
1681         depends on MMU
1682         help
1683           The address space of ARM processors is only 4 Gigabytes large
1684           and it has to accommodate user address space, kernel address
1685           space as well as some memory mapped IO. That means that, if you
1686           have a large amount of physical memory and/or IO, not all of the
1687           memory can be "permanently mapped" by the kernel. The physical
1688           memory that is not permanently mapped is called "high memory".
1689
1690           Depending on the selected kernel/user memory split, minimum
1691           vmalloc space and actual amount of RAM, you may not need this
1692           option which should result in a slightly faster kernel.
1693
1694           If unsure, say n.
1695
1696 config HIGHPTE
1697         bool "Allocate 2nd-level pagetables from highmem"
1698         depends on HIGHMEM
1699
1700 config HW_PERF_EVENTS
1701         bool "Enable hardware performance counter support for perf events"
1702         depends on PERF_EVENTS
1703         default y
1704         help
1705           Enable hardware performance counter support for perf events. If
1706           disabled, perf events will use software events only.
1707
1708 source "mm/Kconfig"
1709
1710 config FORCE_MAX_ZONEORDER
1711         int "Maximum zone order" if ARCH_SHMOBILE
1712         range 11 64 if ARCH_SHMOBILE
1713         default "12" if SOC_AM33XX
1714         default "9" if SA1111
1715         default "11"
1716         help
1717           The kernel memory allocator divides physically contiguous memory
1718           blocks into "zones", where each zone is a power of two number of
1719           pages.  This option selects the largest power of two that the kernel
1720           keeps in the memory allocator.  If you need to allocate very large
1721           blocks of physically contiguous memory, then you may need to
1722           increase this value.
1723
1724           This config option is actually maximum order plus one. For example,
1725           a value of 11 means that the largest free memory block is 2^10 pages.
1726
1727 config ALIGNMENT_TRAP
1728         bool
1729         depends on CPU_CP15_MMU
1730         default y if !ARCH_EBSA110
1731         select HAVE_PROC_CPU if PROC_FS
1732         help
1733           ARM processors cannot fetch/store information which is not
1734           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1735           address divisible by 4. On 32-bit ARM processors, these non-aligned
1736           fetch/store instructions will be emulated in software if you say
1737           here, which has a severe performance impact. This is necessary for
1738           correct operation of some network protocols. With an IP-only
1739           configuration it is safe to say N, otherwise say Y.
1740
1741 config UACCESS_WITH_MEMCPY
1742         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1743         depends on MMU
1744         default y if CPU_FEROCEON
1745         help
1746           Implement faster copy_to_user and clear_user methods for CPU
1747           cores where a 8-word STM instruction give significantly higher
1748           memory write throughput than a sequence of individual 32bit stores.
1749
1750           A possible side effect is a slight increase in scheduling latency
1751           between threads sharing the same address space if they invoke
1752           such copy operations with large buffers.
1753
1754           However, if the CPU data cache is using a write-allocate mode,
1755           this option is unlikely to provide any performance gain.
1756
1757 config SECCOMP
1758         bool
1759         prompt "Enable seccomp to safely compute untrusted bytecode"
1760         ---help---
1761           This kernel feature is useful for number crunching applications
1762           that may need to compute untrusted bytecode during their
1763           execution. By using pipes or other transports made available to
1764           the process as file descriptors supporting the read/write
1765           syscalls, it's possible to isolate those applications in
1766           their own address space using seccomp. Once seccomp is
1767           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1768           and the task is only allowed to execute a few safe syscalls
1769           defined by each seccomp mode.
1770
1771 config CC_STACKPROTECTOR
1772         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1773         help
1774           This option turns on the -fstack-protector GCC feature. This
1775           feature puts, at the beginning of functions, a canary value on
1776           the stack just before the return address, and validates
1777           the value just before actually returning.  Stack based buffer
1778           overflows (that need to overwrite this return address) now also
1779           overwrite the canary, which gets detected and the attack is then
1780           neutralized via a kernel panic.
1781           This feature requires gcc version 4.2 or above.
1782
1783 config XEN_DOM0
1784         def_bool y
1785         depends on XEN
1786
1787 config XEN
1788         bool "Xen guest support on ARM (EXPERIMENTAL)"
1789         depends on ARM && AEABI && OF
1790         depends on CPU_V7 && !CPU_V6
1791         depends on !GENERIC_ATOMIC64
1792         help
1793           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1794
1795 endmenu
1796
1797 menu "Boot options"
1798
1799 config USE_OF
1800         bool "Flattened Device Tree support"
1801         select IRQ_DOMAIN
1802         select OF
1803         select OF_EARLY_FLATTREE
1804         help
1805           Include support for flattened device tree machine descriptions.
1806
1807 config ATAGS
1808         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1809         default y
1810         help
1811           This is the traditional way of passing data to the kernel at boot
1812           time. If you are solely relying on the flattened device tree (or
1813           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1814           to remove ATAGS support from your kernel binary.  If unsure,
1815           leave this to y.
1816
1817 config DEPRECATED_PARAM_STRUCT
1818         bool "Provide old way to pass kernel parameters"
1819         depends on ATAGS
1820         help
1821           This was deprecated in 2001 and announced to live on for 5 years.
1822           Some old boot loaders still use this way.
1823
1824 # Compressed boot loader in ROM.  Yes, we really want to ask about
1825 # TEXT and BSS so we preserve their values in the config files.
1826 config ZBOOT_ROM_TEXT
1827         hex "Compressed ROM boot loader base address"
1828         default "0"
1829         help
1830           The physical address at which the ROM-able zImage is to be
1831           placed in the target.  Platforms which normally make use of
1832           ROM-able zImage formats normally set this to a suitable
1833           value in their defconfig file.
1834
1835           If ZBOOT_ROM is not enabled, this has no effect.
1836
1837 config ZBOOT_ROM_BSS
1838         hex "Compressed ROM boot loader BSS address"
1839         default "0"
1840         help
1841           The base address of an area of read/write memory in the target
1842           for the ROM-able zImage which must be available while the
1843           decompressor is running. It must be large enough to hold the
1844           entire decompressed kernel plus an additional 128 KiB.
1845           Platforms which normally make use of ROM-able zImage formats
1846           normally set this to a suitable value in their defconfig file.
1847
1848           If ZBOOT_ROM is not enabled, this has no effect.
1849
1850 config ZBOOT_ROM
1851         bool "Compressed boot loader in ROM/flash"
1852         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1853         help
1854           Say Y here if you intend to execute your compressed kernel image
1855           (zImage) directly from ROM or flash.  If unsure, say N.
1856
1857 choice
1858         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1859         depends on ZBOOT_ROM && ARCH_SH7372
1860         default ZBOOT_ROM_NONE
1861         help
1862           Include experimental SD/MMC loading code in the ROM-able zImage.
1863           With this enabled it is possible to write the ROM-able zImage
1864           kernel image to an MMC or SD card and boot the kernel straight
1865           from the reset vector. At reset the processor Mask ROM will load
1866           the first part of the ROM-able zImage which in turn loads the
1867           rest the kernel image to RAM.
1868
1869 config ZBOOT_ROM_NONE
1870         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1871         help
1872           Do not load image from SD or MMC
1873
1874 config ZBOOT_ROM_MMCIF
1875         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1876         help
1877           Load image from MMCIF hardware block.
1878
1879 config ZBOOT_ROM_SH_MOBILE_SDHI
1880         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1881         help
1882           Load image from SDHI hardware block
1883
1884 endchoice
1885
1886 config ARM_APPENDED_DTB
1887         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1888         depends on OF && !ZBOOT_ROM
1889         help
1890           With this option, the boot code will look for a device tree binary
1891           (DTB) appended to zImage
1892           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1893
1894           This is meant as a backward compatibility convenience for those
1895           systems with a bootloader that can't be upgraded to accommodate
1896           the documented boot protocol using a device tree.
1897
1898           Beware that there is very little in terms of protection against
1899           this option being confused by leftover garbage in memory that might
1900           look like a DTB header after a reboot if no actual DTB is appended
1901           to zImage.  Do not leave this option active in a production kernel
1902           if you don't intend to always append a DTB.  Proper passing of the
1903           location into r2 of a bootloader provided DTB is always preferable
1904           to this option.
1905
1906 config ARM_ATAG_DTB_COMPAT
1907         bool "Supplement the appended DTB with traditional ATAG information"
1908         depends on ARM_APPENDED_DTB
1909         help
1910           Some old bootloaders can't be updated to a DTB capable one, yet
1911           they provide ATAGs with memory configuration, the ramdisk address,
1912           the kernel cmdline string, etc.  Such information is dynamically
1913           provided by the bootloader and can't always be stored in a static
1914           DTB.  To allow a device tree enabled kernel to be used with such
1915           bootloaders, this option allows zImage to extract the information
1916           from the ATAG list and store it at run time into the appended DTB.
1917
1918 choice
1919         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1920         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1921
1922 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1923         bool "Use bootloader kernel arguments if available"
1924         help
1925           Uses the command-line options passed by the boot loader instead of
1926           the device tree bootargs property. If the boot loader doesn't provide
1927           any, the device tree bootargs property will be used.
1928
1929 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1930         bool "Extend with bootloader kernel arguments"
1931         help
1932           The command-line arguments provided by the boot loader will be
1933           appended to the the device tree bootargs property.
1934
1935 endchoice
1936
1937 config CMDLINE
1938         string "Default kernel command string"
1939         default ""
1940         help
1941           On some architectures (EBSA110 and CATS), there is currently no way
1942           for the boot loader to pass arguments to the kernel. For these
1943           architectures, you should supply some command-line options at build
1944           time by entering them here. As a minimum, you should specify the
1945           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1946
1947 choice
1948         prompt "Kernel command line type" if CMDLINE != ""
1949         default CMDLINE_FROM_BOOTLOADER
1950         depends on ATAGS
1951
1952 config CMDLINE_FROM_BOOTLOADER
1953         bool "Use bootloader kernel arguments if available"
1954         help
1955           Uses the command-line options passed by the boot loader. If
1956           the boot loader doesn't provide any, the default kernel command
1957           string provided in CMDLINE will be used.
1958
1959 config CMDLINE_EXTEND
1960         bool "Extend bootloader kernel arguments"
1961         help
1962           The command-line arguments provided by the boot loader will be
1963           appended to the default kernel command string.
1964
1965 config CMDLINE_FORCE
1966         bool "Always use the default kernel command string"
1967         help
1968           Always use the default kernel command string, even if the boot
1969           loader passes other arguments to the kernel.
1970           This is useful if you cannot or don't want to change the
1971           command-line options your boot loader passes to the kernel.
1972 endchoice
1973
1974 config XIP_KERNEL
1975         bool "Kernel Execute-In-Place from ROM"
1976         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
1977         help
1978           Execute-In-Place allows the kernel to run from non-volatile storage
1979           directly addressable by the CPU, such as NOR flash. This saves RAM
1980           space since the text section of the kernel is not loaded from flash
1981           to RAM.  Read-write sections, such as the data section and stack,
1982           are still copied to RAM.  The XIP kernel is not compressed since
1983           it has to run directly from flash, so it will take more space to
1984           store it.  The flash address used to link the kernel object files,
1985           and for storing it, is configuration dependent. Therefore, if you
1986           say Y here, you must know the proper physical address where to
1987           store the kernel image depending on your own flash memory usage.
1988
1989           Also note that the make target becomes "make xipImage" rather than
1990           "make zImage" or "make Image".  The final kernel binary to put in
1991           ROM memory will be arch/arm/boot/xipImage.
1992
1993           If unsure, say N.
1994
1995 config XIP_PHYS_ADDR
1996         hex "XIP Kernel Physical Location"
1997         depends on XIP_KERNEL
1998         default "0x00080000"
1999         help
2000           This is the physical address in your flash memory the kernel will
2001           be linked for and stored to.  This address is dependent on your
2002           own flash usage.
2003
2004 config KEXEC
2005         bool "Kexec system call (EXPERIMENTAL)"
2006         depends on (!SMP || HOTPLUG_CPU)
2007         help
2008           kexec is a system call that implements the ability to shutdown your
2009           current kernel, and to start another kernel.  It is like a reboot
2010           but it is independent of the system firmware.   And like a reboot
2011           you can start any kernel with it, not just Linux.
2012
2013           It is an ongoing process to be certain the hardware in a machine
2014           is properly shutdown, so do not be surprised if this code does not
2015           initially work for you.  It may help to enable device hotplugging
2016           support.
2017
2018 config ATAGS_PROC
2019         bool "Export atags in procfs"
2020         depends on ATAGS && KEXEC
2021         default y
2022         help
2023           Should the atags used to boot the kernel be exported in an "atags"
2024           file in procfs. Useful with kexec.
2025
2026 config CRASH_DUMP
2027         bool "Build kdump crash kernel (EXPERIMENTAL)"
2028         help
2029           Generate crash dump after being started by kexec. This should
2030           be normally only set in special crash dump kernels which are
2031           loaded in the main kernel with kexec-tools into a specially
2032           reserved region and then later executed after a crash by
2033           kdump/kexec. The crash dump kernel must be compiled to a
2034           memory address not used by the main kernel
2035
2036           For more details see Documentation/kdump/kdump.txt
2037
2038 config AUTO_ZRELADDR
2039         bool "Auto calculation of the decompressed kernel image address"
2040         depends on !ZBOOT_ROM && !ARCH_U300
2041         help
2042           ZRELADDR is the physical address where the decompressed kernel
2043           image will be placed. If AUTO_ZRELADDR is selected, the address
2044           will be determined at run-time by masking the current IP with
2045           0xf8000000. This assumes the zImage being placed in the first 128MB
2046           from start of memory.
2047
2048 endmenu
2049
2050 menu "CPU Power Management"
2051
2052 if ARCH_HAS_CPUFREQ
2053 source "drivers/cpufreq/Kconfig"
2054
2055 config CPU_FREQ_S3C
2056         bool
2057         help
2058           Internal configuration node for common cpufreq on Samsung SoC
2059
2060 config CPU_FREQ_S3C24XX
2061         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2062         depends on ARCH_S3C24XX && CPU_FREQ
2063         select CPU_FREQ_S3C
2064         help
2065           This enables the CPUfreq driver for the Samsung S3C24XX family
2066           of CPUs.
2067
2068           For details, take a look at <file:Documentation/cpu-freq>.
2069
2070           If in doubt, say N.
2071
2072 config CPU_FREQ_S3C24XX_PLL
2073         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2074         depends on CPU_FREQ_S3C24XX
2075         help
2076           Compile in support for changing the PLL frequency from the
2077           S3C24XX series CPUfreq driver. The PLL takes time to settle
2078           after a frequency change, so by default it is not enabled.
2079
2080           This also means that the PLL tables for the selected CPU(s) will
2081           be built which may increase the size of the kernel image.
2082
2083 config CPU_FREQ_S3C24XX_DEBUG
2084         bool "Debug CPUfreq Samsung driver core"
2085         depends on CPU_FREQ_S3C24XX
2086         help
2087           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2088
2089 config CPU_FREQ_S3C24XX_IODEBUG
2090         bool "Debug CPUfreq Samsung driver IO timing"
2091         depends on CPU_FREQ_S3C24XX
2092         help
2093           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2094
2095 config CPU_FREQ_S3C24XX_DEBUGFS
2096         bool "Export debugfs for CPUFreq"
2097         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2098         help
2099           Export status information via debugfs.
2100
2101 endif
2102
2103 source "drivers/cpuidle/Kconfig"
2104
2105 endmenu
2106
2107 menu "Floating point emulation"
2108
2109 comment "At least one emulation must be selected"
2110
2111 config FPE_NWFPE
2112         bool "NWFPE math emulation"
2113         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2114         ---help---
2115           Say Y to include the NWFPE floating point emulator in the kernel.
2116           This is necessary to run most binaries. Linux does not currently
2117           support floating point hardware so you need to say Y here even if
2118           your machine has an FPA or floating point co-processor podule.
2119
2120           You may say N here if you are going to load the Acorn FPEmulator
2121           early in the bootup.
2122
2123 config FPE_NWFPE_XP
2124         bool "Support extended precision"
2125         depends on FPE_NWFPE
2126         help
2127           Say Y to include 80-bit support in the kernel floating-point
2128           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2129           Note that gcc does not generate 80-bit operations by default,
2130           so in most cases this option only enlarges the size of the
2131           floating point emulator without any good reason.
2132
2133           You almost surely want to say N here.
2134
2135 config FPE_FASTFPE
2136         bool "FastFPE math emulation (EXPERIMENTAL)"
2137         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2138         ---help---
2139           Say Y here to include the FAST floating point emulator in the kernel.
2140           This is an experimental much faster emulator which now also has full
2141           precision for the mantissa.  It does not support any exceptions.
2142           It is very simple, and approximately 3-6 times faster than NWFPE.
2143
2144           It should be sufficient for most programs.  It may be not suitable
2145           for scientific calculations, but you have to check this for yourself.
2146           If you do not feel you need a faster FP emulation you should better
2147           choose NWFPE.
2148
2149 config VFP
2150         bool "VFP-format floating point maths"
2151         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2152         help
2153           Say Y to include VFP support code in the kernel. This is needed
2154           if your hardware includes a VFP unit.
2155
2156           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2157           release notes and additional status information.
2158
2159           Say N if your target does not have VFP hardware.
2160
2161 config VFPv3
2162         bool
2163         depends on VFP
2164         default y if CPU_V7
2165
2166 config NEON
2167         bool "Advanced SIMD (NEON) Extension support"
2168         depends on VFPv3 && CPU_V7
2169         help
2170           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2171           Extension.
2172
2173 endmenu
2174
2175 menu "Userspace binary formats"
2176
2177 source "fs/Kconfig.binfmt"
2178
2179 config ARTHUR
2180         tristate "RISC OS personality"
2181         depends on !AEABI
2182         help
2183           Say Y here to include the kernel code necessary if you want to run
2184           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2185           experimental; if this sounds frightening, say N and sleep in peace.
2186           You can also say M here to compile this support as a module (which
2187           will be called arthur).
2188
2189 endmenu
2190
2191 menu "Power management options"
2192
2193 source "kernel/power/Kconfig"
2194
2195 config ARCH_SUSPEND_POSSIBLE
2196         depends on !ARCH_S5PC100
2197         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2198                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2199         def_bool y
2200
2201 config ARM_CPU_SUSPEND
2202         def_bool PM_SLEEP
2203
2204 endmenu
2205
2206 source "net/Kconfig"
2207
2208 source "drivers/Kconfig"
2209
2210 source "fs/Kconfig"
2211
2212 source "arch/arm/Kconfig.debug"
2213
2214 source "security/Kconfig"
2215
2216 source "crypto/Kconfig"
2217
2218 source "lib/Kconfig"
2219
2220 source "arch/arm/kvm/Kconfig"