| 1 | #undef DEBUG |
| 2 | |
| 3 | /* |
| 4 | * ARM performance counter support. |
| 5 | * |
| 6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles |
| 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
| 8 | * |
| 9 | * This code is based on the sparc64 perf event code, which is in turn based |
| 10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace |
| 11 | * code. |
| 12 | */ |
| 13 | #define pr_fmt(fmt) "hw perfevents: " fmt |
| 14 | |
| 15 | #include <linux/cpumask.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/pm_runtime.h> |
| 19 | #include <linux/uaccess.h> |
| 20 | |
| 21 | #include <asm/irq_regs.h> |
| 22 | #include <asm/pmu.h> |
| 23 | #include <asm/stacktrace.h> |
| 24 | |
| 25 | static int |
| 26 | armpmu_map_cache_event(const unsigned (*cache_map) |
| 27 | [PERF_COUNT_HW_CACHE_MAX] |
| 28 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 29 | [PERF_COUNT_HW_CACHE_RESULT_MAX], |
| 30 | u64 config) |
| 31 | { |
| 32 | unsigned int cache_type, cache_op, cache_result, ret; |
| 33 | |
| 34 | cache_type = (config >> 0) & 0xff; |
| 35 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 36 | return -EINVAL; |
| 37 | |
| 38 | cache_op = (config >> 8) & 0xff; |
| 39 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 40 | return -EINVAL; |
| 41 | |
| 42 | cache_result = (config >> 16) & 0xff; |
| 43 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 44 | return -EINVAL; |
| 45 | |
| 46 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
| 47 | |
| 48 | if (ret == CACHE_OP_UNSUPPORTED) |
| 49 | return -ENOENT; |
| 50 | |
| 51 | return ret; |
| 52 | } |
| 53 | |
| 54 | static int |
| 55 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
| 56 | { |
| 57 | int mapping; |
| 58 | |
| 59 | if (config >= PERF_COUNT_HW_MAX) |
| 60 | return -ENOENT; |
| 61 | |
| 62 | mapping = (*event_map)[config]; |
| 63 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; |
| 64 | } |
| 65 | |
| 66 | static int |
| 67 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
| 68 | { |
| 69 | return (int)(config & raw_event_mask); |
| 70 | } |
| 71 | |
| 72 | int |
| 73 | armpmu_map_event(struct perf_event *event, |
| 74 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], |
| 75 | const unsigned (*cache_map) |
| 76 | [PERF_COUNT_HW_CACHE_MAX] |
| 77 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 78 | [PERF_COUNT_HW_CACHE_RESULT_MAX], |
| 79 | u32 raw_event_mask) |
| 80 | { |
| 81 | u64 config = event->attr.config; |
| 82 | |
| 83 | switch (event->attr.type) { |
| 84 | case PERF_TYPE_HARDWARE: |
| 85 | return armpmu_map_hw_event(event_map, config); |
| 86 | case PERF_TYPE_HW_CACHE: |
| 87 | return armpmu_map_cache_event(cache_map, config); |
| 88 | case PERF_TYPE_RAW: |
| 89 | return armpmu_map_raw_event(raw_event_mask, config); |
| 90 | default: |
| 91 | if (event->attr.type >= PERF_TYPE_MAX) |
| 92 | return armpmu_map_raw_event(raw_event_mask, config); |
| 93 | } |
| 94 | |
| 95 | return -ENOENT; |
| 96 | } |
| 97 | |
| 98 | int armpmu_event_set_period(struct perf_event *event) |
| 99 | { |
| 100 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 101 | struct hw_perf_event *hwc = &event->hw; |
| 102 | s64 left = local64_read(&hwc->period_left); |
| 103 | s64 period = hwc->sample_period; |
| 104 | int ret = 0; |
| 105 | |
| 106 | /* The period may have been changed by PERF_EVENT_IOC_PERIOD */ |
| 107 | if (unlikely(period != hwc->last_period)) |
| 108 | left = period - (hwc->last_period - left); |
| 109 | |
| 110 | if (unlikely(left <= -period)) { |
| 111 | left = period; |
| 112 | local64_set(&hwc->period_left, left); |
| 113 | hwc->last_period = period; |
| 114 | ret = 1; |
| 115 | } |
| 116 | |
| 117 | if (unlikely(left <= 0)) { |
| 118 | left += period; |
| 119 | local64_set(&hwc->period_left, left); |
| 120 | hwc->last_period = period; |
| 121 | ret = 1; |
| 122 | } |
| 123 | |
| 124 | if (left > (s64)armpmu->max_period) |
| 125 | left = armpmu->max_period; |
| 126 | |
| 127 | local64_set(&hwc->prev_count, (u64)-left); |
| 128 | |
| 129 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
| 130 | |
| 131 | perf_event_update_userpage(event); |
| 132 | |
| 133 | return ret; |
| 134 | } |
| 135 | |
| 136 | u64 armpmu_event_update(struct perf_event *event) |
| 137 | { |
| 138 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 139 | struct hw_perf_event *hwc = &event->hw; |
| 140 | u64 delta, prev_raw_count, new_raw_count; |
| 141 | |
| 142 | again: |
| 143 | prev_raw_count = local64_read(&hwc->prev_count); |
| 144 | new_raw_count = armpmu->read_counter(event); |
| 145 | |
| 146 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 147 | new_raw_count) != prev_raw_count) |
| 148 | goto again; |
| 149 | |
| 150 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
| 151 | |
| 152 | local64_add(delta, &event->count); |
| 153 | local64_sub(delta, &hwc->period_left); |
| 154 | |
| 155 | return new_raw_count; |
| 156 | } |
| 157 | |
| 158 | static void |
| 159 | armpmu_read(struct perf_event *event) |
| 160 | { |
| 161 | armpmu_event_update(event); |
| 162 | } |
| 163 | |
| 164 | static void |
| 165 | armpmu_stop(struct perf_event *event, int flags) |
| 166 | { |
| 167 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 168 | struct hw_perf_event *hwc = &event->hw; |
| 169 | |
| 170 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->valid_cpus)) |
| 171 | return; |
| 172 | /* |
| 173 | * ARM pmu always has to update the counter, so ignore |
| 174 | * PERF_EF_UPDATE, see comments in armpmu_start(). |
| 175 | */ |
| 176 | if (!(hwc->state & PERF_HES_STOPPED)) { |
| 177 | armpmu->disable(event); |
| 178 | armpmu_event_update(event); |
| 179 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 180 | } |
| 181 | } |
| 182 | |
| 183 | static void armpmu_start(struct perf_event *event, int flags) |
| 184 | { |
| 185 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 186 | struct hw_perf_event *hwc = &event->hw; |
| 187 | |
| 188 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->valid_cpus)) |
| 189 | return; |
| 190 | /* |
| 191 | * ARM pmu always has to reprogram the period, so ignore |
| 192 | * PERF_EF_RELOAD, see the comment below. |
| 193 | */ |
| 194 | if (flags & PERF_EF_RELOAD) |
| 195 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); |
| 196 | |
| 197 | hwc->state = 0; |
| 198 | /* |
| 199 | * Set the period again. Some counters can't be stopped, so when we |
| 200 | * were stopped we simply disabled the IRQ source and the counter |
| 201 | * may have been left counting. If we don't do this step then we may |
| 202 | * get an interrupt too soon or *way* too late if the overflow has |
| 203 | * happened since disabling. |
| 204 | */ |
| 205 | armpmu_event_set_period(event); |
| 206 | armpmu->enable(event); |
| 207 | } |
| 208 | |
| 209 | static void |
| 210 | armpmu_del(struct perf_event *event, int flags) |
| 211 | { |
| 212 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 213 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
| 214 | struct hw_perf_event *hwc = &event->hw; |
| 215 | int idx = hwc->idx; |
| 216 | |
| 217 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->valid_cpus)) |
| 218 | return; |
| 219 | |
| 220 | armpmu_stop(event, PERF_EF_UPDATE); |
| 221 | hw_events->events[idx] = NULL; |
| 222 | clear_bit(idx, hw_events->used_mask); |
| 223 | |
| 224 | perf_event_update_userpage(event); |
| 225 | } |
| 226 | |
| 227 | static int |
| 228 | armpmu_add(struct perf_event *event, int flags) |
| 229 | { |
| 230 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 231 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
| 232 | struct hw_perf_event *hwc = &event->hw; |
| 233 | int idx; |
| 234 | int err = 0; |
| 235 | |
| 236 | /* An event following a process won't be stopped earlier */ |
| 237 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->valid_cpus)) |
| 238 | return 0; |
| 239 | |
| 240 | perf_pmu_disable(event->pmu); |
| 241 | |
| 242 | /* If we don't have a space for the counter then finish early. */ |
| 243 | idx = armpmu->get_event_idx(hw_events, event); |
| 244 | if (idx < 0) { |
| 245 | err = idx; |
| 246 | goto out; |
| 247 | } |
| 248 | |
| 249 | /* |
| 250 | * If there is an event in the counter we are going to use then make |
| 251 | * sure it is disabled. |
| 252 | */ |
| 253 | event->hw.idx = idx; |
| 254 | armpmu->disable(event); |
| 255 | hw_events->events[idx] = event; |
| 256 | |
| 257 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 258 | if (flags & PERF_EF_START) |
| 259 | armpmu_start(event, PERF_EF_RELOAD); |
| 260 | |
| 261 | /* Propagate our changes to the userspace mapping. */ |
| 262 | perf_event_update_userpage(event); |
| 263 | |
| 264 | out: |
| 265 | perf_pmu_enable(event->pmu); |
| 266 | return err; |
| 267 | } |
| 268 | |
| 269 | static int |
| 270 | validate_event(struct pmu_hw_events *hw_events, |
| 271 | struct perf_event *event) |
| 272 | { |
| 273 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 274 | struct pmu *leader_pmu = event->group_leader->pmu; |
| 275 | |
| 276 | if (is_software_event(event)) |
| 277 | return 1; |
| 278 | |
| 279 | if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF) |
| 280 | return 1; |
| 281 | |
| 282 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) |
| 283 | return 1; |
| 284 | |
| 285 | return armpmu->get_event_idx(hw_events, event) >= 0; |
| 286 | } |
| 287 | |
| 288 | static int |
| 289 | validate_group(struct perf_event *event) |
| 290 | { |
| 291 | struct perf_event *sibling, *leader = event->group_leader; |
| 292 | struct pmu_hw_events fake_pmu; |
| 293 | DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS); |
| 294 | |
| 295 | /* |
| 296 | * Initialise the fake PMU. We only need to populate the |
| 297 | * used_mask for the purposes of validation. |
| 298 | */ |
| 299 | memset(fake_used_mask, 0, sizeof(fake_used_mask)); |
| 300 | fake_pmu.used_mask = fake_used_mask; |
| 301 | |
| 302 | if (!validate_event(&fake_pmu, leader)) |
| 303 | return -EINVAL; |
| 304 | |
| 305 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { |
| 306 | if (!validate_event(&fake_pmu, sibling)) |
| 307 | return -EINVAL; |
| 308 | } |
| 309 | |
| 310 | if (!validate_event(&fake_pmu, event)) |
| 311 | return -EINVAL; |
| 312 | |
| 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
| 317 | { |
| 318 | struct arm_pmu *armpmu = (struct arm_pmu *) dev; |
| 319 | struct platform_device *plat_device = armpmu->plat_device; |
| 320 | struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); |
| 321 | int ret; |
| 322 | u64 start_clock, finish_clock; |
| 323 | |
| 324 | start_clock = sched_clock(); |
| 325 | if (plat && plat->handle_irq) |
| 326 | ret = plat->handle_irq(irq, dev, armpmu->handle_irq); |
| 327 | else |
| 328 | ret = armpmu->handle_irq(irq, dev); |
| 329 | finish_clock = sched_clock(); |
| 330 | |
| 331 | perf_sample_event_took(finish_clock - start_clock); |
| 332 | return ret; |
| 333 | } |
| 334 | |
| 335 | static void |
| 336 | armpmu_release_hardware(struct arm_pmu *armpmu) |
| 337 | { |
| 338 | armpmu->free_irq(armpmu); |
| 339 | pm_runtime_put_sync(&armpmu->plat_device->dev); |
| 340 | } |
| 341 | |
| 342 | static int |
| 343 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
| 344 | { |
| 345 | int err; |
| 346 | struct platform_device *pmu_device = armpmu->plat_device; |
| 347 | |
| 348 | if (!pmu_device) |
| 349 | return -ENODEV; |
| 350 | |
| 351 | pm_runtime_get_sync(&pmu_device->dev); |
| 352 | err = armpmu->request_irq(armpmu, armpmu_dispatch_irq); |
| 353 | if (err) { |
| 354 | armpmu_release_hardware(armpmu); |
| 355 | return err; |
| 356 | } |
| 357 | |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | static void |
| 362 | hw_perf_event_destroy(struct perf_event *event) |
| 363 | { |
| 364 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 365 | atomic_t *active_events = &armpmu->active_events; |
| 366 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; |
| 367 | |
| 368 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { |
| 369 | armpmu_release_hardware(armpmu); |
| 370 | mutex_unlock(pmu_reserve_mutex); |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | static int |
| 375 | event_requires_mode_exclusion(struct perf_event_attr *attr) |
| 376 | { |
| 377 | return attr->exclude_idle || attr->exclude_user || |
| 378 | attr->exclude_kernel || attr->exclude_hv; |
| 379 | } |
| 380 | |
| 381 | static int |
| 382 | __hw_perf_event_init(struct perf_event *event) |
| 383 | { |
| 384 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 385 | struct hw_perf_event *hwc = &event->hw; |
| 386 | int mapping; |
| 387 | |
| 388 | mapping = armpmu->map_event(event); |
| 389 | |
| 390 | if (mapping < 0) { |
| 391 | pr_debug("event %x:%llx not supported\n", event->attr.type, |
| 392 | event->attr.config); |
| 393 | return mapping; |
| 394 | } |
| 395 | |
| 396 | /* |
| 397 | * We don't assign an index until we actually place the event onto |
| 398 | * hardware. Use -1 to signify that we haven't decided where to put it |
| 399 | * yet. For SMP systems, each core has it's own PMU so we can't do any |
| 400 | * clever allocation or constraints checking at this point. |
| 401 | */ |
| 402 | hwc->idx = -1; |
| 403 | hwc->config_base = 0; |
| 404 | hwc->config = 0; |
| 405 | hwc->event_base = 0; |
| 406 | |
| 407 | /* |
| 408 | * Check whether we need to exclude the counter from certain modes. |
| 409 | */ |
| 410 | if ((!armpmu->set_event_filter || |
| 411 | armpmu->set_event_filter(hwc, &event->attr)) && |
| 412 | event_requires_mode_exclusion(&event->attr)) { |
| 413 | pr_debug("ARM performance counters do not support " |
| 414 | "mode exclusion\n"); |
| 415 | return -EOPNOTSUPP; |
| 416 | } |
| 417 | |
| 418 | /* |
| 419 | * Store the event encoding into the config_base field. |
| 420 | */ |
| 421 | hwc->config_base |= (unsigned long)mapping; |
| 422 | |
| 423 | if (!hwc->sample_period) { |
| 424 | /* |
| 425 | * For non-sampling runs, limit the sample_period to half |
| 426 | * of the counter width. That way, the new counter value |
| 427 | * is far less likely to overtake the previous one unless |
| 428 | * you have some serious IRQ latency issues. |
| 429 | */ |
| 430 | hwc->sample_period = armpmu->max_period >> 1; |
| 431 | hwc->last_period = hwc->sample_period; |
| 432 | local64_set(&hwc->period_left, hwc->sample_period); |
| 433 | } |
| 434 | |
| 435 | if (event->group_leader != event) { |
| 436 | if (validate_group(event) != 0) |
| 437 | return -EINVAL; |
| 438 | } |
| 439 | |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | static int armpmu_event_init(struct perf_event *event) |
| 444 | { |
| 445 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 446 | int err = 0; |
| 447 | atomic_t *active_events = &armpmu->active_events; |
| 448 | |
| 449 | if (event->cpu != -1 && |
| 450 | !cpumask_test_cpu(event->cpu, &armpmu->valid_cpus)) |
| 451 | return -ENOENT; |
| 452 | |
| 453 | /* does not support taken branch sampling */ |
| 454 | if (has_branch_stack(event)) |
| 455 | return -EOPNOTSUPP; |
| 456 | |
| 457 | if (armpmu->map_event(event) == -ENOENT) |
| 458 | return -ENOENT; |
| 459 | |
| 460 | event->destroy = hw_perf_event_destroy; |
| 461 | |
| 462 | if (!atomic_inc_not_zero(active_events)) { |
| 463 | mutex_lock(&armpmu->reserve_mutex); |
| 464 | if (atomic_read(active_events) == 0) |
| 465 | err = armpmu_reserve_hardware(armpmu); |
| 466 | |
| 467 | if (!err) |
| 468 | atomic_inc(active_events); |
| 469 | mutex_unlock(&armpmu->reserve_mutex); |
| 470 | } |
| 471 | |
| 472 | if (err) |
| 473 | return err; |
| 474 | |
| 475 | err = __hw_perf_event_init(event); |
| 476 | if (err) |
| 477 | hw_perf_event_destroy(event); |
| 478 | |
| 479 | return err; |
| 480 | } |
| 481 | |
| 482 | static void armpmu_enable(struct pmu *pmu) |
| 483 | { |
| 484 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
| 485 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
| 486 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
| 487 | |
| 488 | if (enabled) |
| 489 | armpmu->start(armpmu); |
| 490 | } |
| 491 | |
| 492 | static void armpmu_disable(struct pmu *pmu) |
| 493 | { |
| 494 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
| 495 | armpmu->stop(armpmu); |
| 496 | } |
| 497 | |
| 498 | #ifdef CONFIG_PM_RUNTIME |
| 499 | static int armpmu_runtime_resume(struct device *dev) |
| 500 | { |
| 501 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); |
| 502 | |
| 503 | if (plat && plat->runtime_resume) |
| 504 | return plat->runtime_resume(dev); |
| 505 | |
| 506 | return 0; |
| 507 | } |
| 508 | |
| 509 | static int armpmu_runtime_suspend(struct device *dev) |
| 510 | { |
| 511 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); |
| 512 | |
| 513 | if (plat && plat->runtime_suspend) |
| 514 | return plat->runtime_suspend(dev); |
| 515 | |
| 516 | return 0; |
| 517 | } |
| 518 | #endif |
| 519 | |
| 520 | const struct dev_pm_ops armpmu_dev_pm_ops = { |
| 521 | SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) |
| 522 | }; |
| 523 | |
| 524 | static void armpmu_init(struct arm_pmu *armpmu) |
| 525 | { |
| 526 | atomic_set(&armpmu->active_events, 0); |
| 527 | mutex_init(&armpmu->reserve_mutex); |
| 528 | |
| 529 | armpmu->pmu = (struct pmu) { |
| 530 | .pmu_enable = armpmu_enable, |
| 531 | .pmu_disable = armpmu_disable, |
| 532 | .event_init = armpmu_event_init, |
| 533 | .add = armpmu_add, |
| 534 | .del = armpmu_del, |
| 535 | .start = armpmu_start, |
| 536 | .stop = armpmu_stop, |
| 537 | .read = armpmu_read, |
| 538 | }; |
| 539 | } |
| 540 | |
| 541 | int armpmu_register(struct arm_pmu *armpmu, int type) |
| 542 | { |
| 543 | armpmu_init(armpmu); |
| 544 | pm_runtime_enable(&armpmu->plat_device->dev); |
| 545 | pr_info("enabled with %s PMU driver, %d counters available\n", |
| 546 | armpmu->name, armpmu->num_events); |
| 547 | return perf_pmu_register(&armpmu->pmu, armpmu->name, type); |
| 548 | } |
| 549 | |
| 550 | /* |
| 551 | * Callchain handling code. |
| 552 | */ |
| 553 | |
| 554 | /* |
| 555 | * The registers we're interested in are at the end of the variable |
| 556 | * length saved register structure. The fp points at the end of this |
| 557 | * structure so the address of this struct is: |
| 558 | * (struct frame_tail *)(xxx->fp)-1 |
| 559 | * |
| 560 | * This code has been adapted from the ARM OProfile support. |
| 561 | */ |
| 562 | struct frame_tail { |
| 563 | struct frame_tail __user *fp; |
| 564 | unsigned long sp; |
| 565 | unsigned long lr; |
| 566 | } __attribute__((packed)); |
| 567 | |
| 568 | /* |
| 569 | * Get the return address for a single stackframe and return a pointer to the |
| 570 | * next frame tail. |
| 571 | */ |
| 572 | static struct frame_tail __user * |
| 573 | user_backtrace(struct frame_tail __user *tail, |
| 574 | struct perf_callchain_entry *entry) |
| 575 | { |
| 576 | struct frame_tail buftail; |
| 577 | |
| 578 | /* Also check accessibility of one struct frame_tail beyond */ |
| 579 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) |
| 580 | return NULL; |
| 581 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) |
| 582 | return NULL; |
| 583 | |
| 584 | perf_callchain_store(entry, buftail.lr); |
| 585 | |
| 586 | /* |
| 587 | * Frame pointers should strictly progress back up the stack |
| 588 | * (towards higher addresses). |
| 589 | */ |
| 590 | if (tail + 1 >= buftail.fp) |
| 591 | return NULL; |
| 592 | |
| 593 | return buftail.fp - 1; |
| 594 | } |
| 595 | |
| 596 | void |
| 597 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) |
| 598 | { |
| 599 | struct frame_tail __user *tail; |
| 600 | |
| 601 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 602 | /* We don't support guest os callchain now */ |
| 603 | return; |
| 604 | } |
| 605 | |
| 606 | perf_callchain_store(entry, regs->ARM_pc); |
| 607 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
| 608 | |
| 609 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
| 610 | tail && !((unsigned long)tail & 0x3)) |
| 611 | tail = user_backtrace(tail, entry); |
| 612 | } |
| 613 | |
| 614 | /* |
| 615 | * Gets called by walk_stackframe() for every stackframe. This will be called |
| 616 | * whist unwinding the stackframe and is like a subroutine return so we use |
| 617 | * the PC. |
| 618 | */ |
| 619 | static int |
| 620 | callchain_trace(struct stackframe *fr, |
| 621 | void *data) |
| 622 | { |
| 623 | struct perf_callchain_entry *entry = data; |
| 624 | perf_callchain_store(entry, fr->pc); |
| 625 | return 0; |
| 626 | } |
| 627 | |
| 628 | void |
| 629 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) |
| 630 | { |
| 631 | struct stackframe fr; |
| 632 | |
| 633 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 634 | /* We don't support guest os callchain now */ |
| 635 | return; |
| 636 | } |
| 637 | |
| 638 | fr.fp = regs->ARM_fp; |
| 639 | fr.sp = regs->ARM_sp; |
| 640 | fr.lr = regs->ARM_lr; |
| 641 | fr.pc = regs->ARM_pc; |
| 642 | walk_stackframe(&fr, callchain_trace, entry); |
| 643 | } |
| 644 | |
| 645 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
| 646 | { |
| 647 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
| 648 | return perf_guest_cbs->get_guest_ip(); |
| 649 | |
| 650 | return instruction_pointer(regs); |
| 651 | } |
| 652 | |
| 653 | unsigned long perf_misc_flags(struct pt_regs *regs) |
| 654 | { |
| 655 | int misc = 0; |
| 656 | |
| 657 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 658 | if (perf_guest_cbs->is_user_mode()) |
| 659 | misc |= PERF_RECORD_MISC_GUEST_USER; |
| 660 | else |
| 661 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; |
| 662 | } else { |
| 663 | if (user_mode(regs)) |
| 664 | misc |= PERF_RECORD_MISC_USER; |
| 665 | else |
| 666 | misc |= PERF_RECORD_MISC_KERNEL; |
| 667 | } |
| 668 | |
| 669 | return misc; |
| 670 | } |