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[ALSA] ac97_codec: increase timeout for analog subsections
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / intel8x0.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
c1017a4c 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
1da177e4
LT		 29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/moduleparam.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#include <asm/cacheflush.h>
44
c1017a4c 45MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
1da177e4
LT		 46MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
49 "{Intel,82901AB-ICH0},"
50 "{Intel,82801BA-ICH2},"
51 "{Intel,82801CA-ICH3},"
52 "{Intel,82801DB-ICH4},"
53 "{Intel,ICH5},"
54 "{Intel,ICH6},"
55 "{Intel,ICH7},"
56 "{Intel,6300ESB},"
c4c8ea94 57 "{Intel,ESB2},"
1da177e4
LT		 58 "{Intel,MX440},"
59 "{SiS,SI7012},"
60 "{NVidia,nForce Audio},"
61 "{NVidia,nForce2 Audio},"
a2854dc5
AB		 62 "{NVidia,nForce3 Audio},"
63 "{NVidia,MCP04},"
64 "{NVidia,MCP501},"
65 "{NVidia,CK804},"
66 "{NVidia,CK8},"
67 "{NVidia,CK8S},"
1da177e4
LT		 68 "{AMD,AMD768},"
69 "{AMD,AMD8111},"
70 "{ALI,M5455}}");
71
b7fe4622
CL		 72static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
73static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
6581f4e7 74static int ac97_clock;
b7fe4622
CL		 75static char *ac97_quirk;
76static int buggy_semaphore;
beef08a5 77static int buggy_irq = -1; /* auto-check */
b7fe4622 78static int xbox;
a9e99660 79static int spdif_aclink = -1;
b7fe4622
CL		 80
81module_param(index, int, 0444);
1da177e4 82MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
b7fe4622 83module_param(id, charp, 0444);
1da177e4 84MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
b7fe4622 85module_param(ac97_clock, int, 0444);
2b3b5485 86MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
b7fe4622 87module_param(ac97_quirk, charp, 0444);
1da177e4 88MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
b7fe4622 89module_param(buggy_semaphore, bool, 0444);
a06147d2 90MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
b7fe4622 91module_param(buggy_irq, bool, 0444);
1da177e4 92MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
b7fe4622 93module_param(xbox, bool, 0444);
1da177e4 94MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
a9e99660
TI		 95module_param(spdif_aclink, int, 0444);
96MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
1da177e4 97
2b3e584b
TI		 98/* just for backward compatibility */
99static int enable;
698444f3 100module_param(enable, bool, 0444);
2b3e584b
TI		 101static int joystick;
102module_param(joystick, int, 0444);
103
1da177e4
LT		 104/*
105 * Direct registers
106 */
1da177e4
LT		 107enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
108
109#define ICHREG(x) ICH_REG_##x
110
111#define DEFINE_REGSET(name,base) \
112enum { \
113 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
114 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
115 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
116 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
117 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
118 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
119 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
120};
121
122/* busmaster blocks */
123DEFINE_REGSET(OFF, 0); /* offset */
124DEFINE_REGSET(PI, 0x00); /* PCM in */
125DEFINE_REGSET(PO, 0x10); /* PCM out */
126DEFINE_REGSET(MC, 0x20); /* Mic in */
127
128/* ICH4 busmaster blocks */
129DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
130DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
131DEFINE_REGSET(SP, 0x60); /* SPDIF out */
132
133/* values for each busmaster block */
134
135/* LVI */
136#define ICH_REG_LVI_MASK 0x1f
137
138/* SR */
139#define ICH_FIFOE 0x10 /* FIFO error */
140#define ICH_BCIS 0x08 /* buffer completion interrupt status */
141#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
142#define ICH_CELV 0x02 /* current equals last valid */
143#define ICH_DCH 0x01 /* DMA controller halted */
144
145/* PIV */
146#define ICH_REG_PIV_MASK 0x1f /* mask */
147
148/* CR */
149#define ICH_IOCE 0x10 /* interrupt on completion enable */
150#define ICH_FEIE 0x08 /* fifo error interrupt enable */
151#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
152#define ICH_RESETREGS 0x02 /* reset busmaster registers */
153#define ICH_STARTBM 0x01 /* start busmaster operation */
154
155
156/* global block */
157#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
158#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
159#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
160#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
161#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
162#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
163#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
4235a317
TI		 164#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
165#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
1da177e4
LT		 166#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
167#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
168#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
169#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
170#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
171#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
172#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
173#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
174#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
175#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
176#define ICH_ACLINK 0x00000008 /* AClink shut off */
177#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
178#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
179#define ICH_GIE 0x00000001 /* GPI interrupt enable */
180#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
181#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
182#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
183#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
184#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
185#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
186#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
187#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
188#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
189#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
84a43bd5
TI		 190#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
191#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
1da177e4
LT		 192#define ICH_MD3 0x00020000 /* modem power down semaphore */
193#define ICH_AD3 0x00010000 /* audio power down semaphore */
194#define ICH_RCS 0x00008000 /* read completion status */
195#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
196#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
197#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
198#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
199#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
200#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
201#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
202#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
203#define ICH_POINT 0x00000040 /* playback interrupt */
204#define ICH_PIINT 0x00000020 /* capture interrupt */
205#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
206#define ICH_MOINT 0x00000004 /* modem playback interrupt */
207#define ICH_MIINT 0x00000002 /* modem capture interrupt */
208#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
209#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
210#define ICH_CAS 0x01 /* codec access semaphore */
211#define ICH_REG_SDM 0x80
212#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
213#define ICH_DI2L_SHIFT 6
214#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
215#define ICH_DI1L_SHIFT 4
216#define ICH_SE 0x00000008 /* steer enable */
217#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
218
219#define ICH_MAX_FRAGS 32 /* max hw frags */
220
221
222/*
223 * registers for Ali5455
224 */
225
226/* ALi 5455 busmaster blocks */
227DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
228DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
229DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
230DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
231DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
232DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
233DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
234DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
235DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
236DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
237DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
238
239enum {
240 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
241 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
242 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
243 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
244 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
245 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
246 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
247 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
248 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
249 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
250 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
251 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
252 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
253 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
254 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
255 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
256 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
257 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
258 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
259 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
260 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
261};
262
263#define ALI_CAS_SEM_BUSY 0x80000000
264#define ALI_CPR_ADDR_SECONDARY 0x100
265#define ALI_CPR_ADDR_READ 0x80
266#define ALI_CSPSR_CODEC_READY 0x08
267#define ALI_CSPSR_READ_OK 0x02
268#define ALI_CSPSR_WRITE_OK 0x01
269
270/* interrupts for the whole chip by interrupt status register finish */
271
272#define ALI_INT_MICIN2 (1<<26)
273#define ALI_INT_PCMIN2 (1<<25)
274#define ALI_INT_I2SIN (1<<24)
275#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
276#define ALI_INT_SPDIFIN (1<<22)
277#define ALI_INT_LFEOUT (1<<21)
278#define ALI_INT_CENTEROUT (1<<20)
279#define ALI_INT_CODECSPDIFOUT (1<<19)
280#define ALI_INT_MICIN (1<<18)
281#define ALI_INT_PCMOUT (1<<17)
282#define ALI_INT_PCMIN (1<<16)
283#define ALI_INT_CPRAIS (1<<7) /* command port available */
284#define ALI_INT_SPRAIS (1<<5) /* status port available */
285#define ALI_INT_GPIO (1<<1)
6b75a9d8
TI		 286#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
287 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
1da177e4
LT		 288
289#define ICH_ALI_SC_RESET (1<<31) /* master reset */
290#define ICH_ALI_SC_AC97_DBL (1<<30)
291#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
292#define ICH_ALI_SC_IN_BITS (3<<18)
293#define ICH_ALI_SC_OUT_BITS (3<<16)
294#define ICH_ALI_SC_6CH_CFG (3<<14)
295#define ICH_ALI_SC_PCM_4 (1<<8)
296#define ICH_ALI_SC_PCM_6 (2<<8)
297#define ICH_ALI_SC_PCM_246_MASK (3<<8)
298
299#define ICH_ALI_SS_SEC_ID (3<<5)
300#define ICH_ALI_SS_PRI_ID (3<<3)
301
302#define ICH_ALI_IF_AC97SP (1<<21)
303#define ICH_ALI_IF_MC (1<<20)
304#define ICH_ALI_IF_PI (1<<19)
305#define ICH_ALI_IF_MC2 (1<<18)
306#define ICH_ALI_IF_PI2 (1<<17)
307#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
308#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
309#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
310#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
311#define ICH_ALI_IF_PO_SPDF (1<<3)
312#define ICH_ALI_IF_PO (1<<1)
313
314/*
315 *
316 */
317
6b75a9d8
TI		 318enum {
319 ICHD_PCMIN,
320 ICHD_PCMOUT,
321 ICHD_MIC,
322 ICHD_MIC2,
323 ICHD_PCM2IN,
324 ICHD_SPBAR,
325 ICHD_LAST = ICHD_SPBAR
326};
327enum {
328 NVD_PCMIN,
329 NVD_PCMOUT,
330 NVD_MIC,
331 NVD_SPBAR,
332 NVD_LAST = NVD_SPBAR
333};
334enum {
335 ALID_PCMIN,
336 ALID_PCMOUT,
337 ALID_MIC,
338 ALID_AC97SPDIFOUT,
339 ALID_SPDIFIN,
340 ALID_SPDIFOUT,
341 ALID_LAST = ALID_SPDIFOUT
342};
1da177e4 343
6b75a9d8 344#define get_ichdev(substream) (substream->runtime->private_data)
1da177e4 345
6b75a9d8 346struct ichdev {
1da177e4
LT		 347 unsigned int ichd; /* ich device number */
348 unsigned long reg_offset; /* offset to bmaddr */
349 u32 *bdbar; /* CPU address (32bit) */
350 unsigned int bdbar_addr; /* PCI bus address (32bit) */
6b75a9d8 351 struct snd_pcm_substream *substream;
1da177e4
LT		 352 unsigned int physbuf; /* physical address (32bit) */
353 unsigned int size;
354 unsigned int fragsize;
355 unsigned int fragsize1;
356 unsigned int position;
357 unsigned int pos_shift;
da2436a2
JK		 358 unsigned int last_pos;
359 unsigned long last_pos_jiffies;
360 unsigned int jiffy_to_bytes;
1da177e4
LT		 361 int frags;
362 int lvi;
363 int lvi_frag;
364 int civ;
365 int ack;
366 int ack_reload;
367 unsigned int ack_bit;
368 unsigned int roff_sr;
369 unsigned int roff_picb;
370 unsigned int int_sta_mask; /* interrupt status mask */
371 unsigned int ali_slot; /* ALI DMA slot */
372 struct ac97_pcm *pcm;
373 int pcm_open_flag;
374 unsigned int page_attr_changed: 1;
1cfe43d2 375 unsigned int suspended: 1;
6b75a9d8 376};
1da177e4 377
6b75a9d8 378struct intel8x0 {
1da177e4
LT		 379 unsigned int device_type;
380
381 int irq;
382
3388c37e
TI		 383 void __iomem *addr;
384 void __iomem *bmaddr;
1da177e4
LT		 385
386 struct pci_dev *pci;
6b75a9d8 387 struct snd_card *card;
1da177e4
LT		 388
389 int pcm_devs;
6b75a9d8
TI		 390 struct snd_pcm *pcm[6];
391 struct ichdev ichd[6];
1da177e4
LT		 392
393 unsigned multi4: 1,
394 multi6: 1,
4235a317 395 multi8 :1,
1da177e4
LT		 396 dra: 1,
397 smp20bit: 1;
398 unsigned in_ac97_init: 1,
399 in_sdin_init: 1;
400 unsigned in_measurement: 1; /* during ac97 clock measurement */
401 unsigned fix_nocache: 1; /* workaround for 440MX */
402 unsigned buggy_irq: 1; /* workaround for buggy mobos */
403 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
a06147d2 404 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
1da177e4
LT		 405
406 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 407 unsigned int sdm_saved; /* SDM reg value */
1da177e4 408
6b75a9d8
TI		 409 struct snd_ac97_bus *ac97_bus;
410 struct snd_ac97 *ac97[3];
1da177e4 411 unsigned int ac97_sdin[3];
84a43bd5
TI		 412 unsigned int max_codecs, ncodecs;
413 unsigned int *codec_bit;
414 unsigned int codec_isr_bits;
415 unsigned int codec_ready_bits;
1da177e4
LT		 416
417 spinlock_t reg_lock;
418
419 u32 bdbars_count;
420 struct snd_dma_buffer bdbars;
421 u32 int_sta_reg; /* interrupt status register */
422 u32 int_sta_mask; /* interrupt status mask */
423};
424
f40b6890 425static struct pci_device_id snd_intel8x0_ids[] = {
1da177e4
LT		 426 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
427 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
428 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
429 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
430 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
431 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
432 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
433 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
434 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
c4c8ea94 435 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
1da177e4
LT		 436 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
437 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
438 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
439 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
440 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
441 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
442 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
443 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
444 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
89ac9c25 445 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
1da177e4
LT		 446 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
447 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
448 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
449 { 0, }
450};
451
452MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
453
454/*
455 * Lowlevel I/O - busmaster
456 */
457
3388c37e 458static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
1da177e4 459{
3388c37e 460 return ioread8(chip->bmaddr + offset);
1da177e4
LT		 461}
462
3388c37e 463static inline u16 igetword(struct intel8x0 *chip, u32 offset)
1da177e4 464{
3388c37e 465 return ioread16(chip->bmaddr + offset);
1da177e4
LT		 466}
467
3388c37e 468static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
1da177e4 469{
3388c37e 470 return ioread32(chip->bmaddr + offset);
1da177e4
LT		 471}
472
3388c37e 473static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
1da177e4 474{
3388c37e 475 iowrite8(val, chip->bmaddr + offset);
1da177e4
LT		 476}
477
3388c37e 478static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4 479{
3388c37e 480 iowrite16(val, chip->bmaddr + offset);
1da177e4
LT		 481}
482
3388c37e 483static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
1da177e4 484{
3388c37e 485 iowrite32(val, chip->bmaddr + offset);
1da177e4
LT		 486}
487
488/*
489 * Lowlevel I/O - AC'97 registers
490 */
491
3388c37e 492static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
1da177e4 493{
3388c37e 494 return ioread16(chip->addr + offset);
1da177e4
LT		 495}
496
3388c37e 497static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4 498{
3388c37e 499 iowrite16(val, chip->addr + offset);
1da177e4
LT		 500}
501
502/*
503 * Basic I/O
504 */
505
506/*
507 * access to AC97 codec via normal i/o (for ICH and SIS7012)
508 */
509
6b75a9d8 510static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
1da177e4
LT		 511{
512 int time;
513
514 if (codec > 2)
515 return -EIO;
516 if (chip->in_sdin_init) {
517 /* we don't know the ready bit assignment at the moment */
518 /* so we check any */
84a43bd5 519 codec = chip->codec_isr_bits;
1da177e4 520 } else {
84a43bd5 521 codec = chip->codec_bit[chip->ac97_sdin[codec]];
1da177e4
LT		 522 }
523
524 /* codec ready ? */
525 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
526 return -EIO;
527
a06147d2
TI		 528 if (chip->buggy_semaphore)
529 return 0; /* just ignore ... */
530
1da177e4
LT		 531 /* Anyone holding a semaphore for 1 msec should be shot... */
532 time = 100;
533 do {
534 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
535 return 0;
536 udelay(10);
537 } while (time--);
538
539 /* access to some forbidden (non existant) ac97 registers will not
540 * reset the semaphore. So even if you don't get the semaphore, still
541 * continue the access. We don't need the semaphore anyway. */
99b359ba 542 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
1da177e4
LT		 543 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
544 iagetword(chip, 0); /* clear semaphore flag */
545 /* I don't care about the semaphore */
546 return -EBUSY;
547}
548
6b75a9d8 549static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 550 unsigned short reg,
551 unsigned short val)
552{
6b75a9d8 553 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 554
555 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
556 if (! chip->in_ac97_init)
99b359ba 557 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 558 }
559 iaputword(chip, reg + ac97->num * 0x80, val);
560}
561
6b75a9d8 562static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
1da177e4
LT		 563 unsigned short reg)
564{
6b75a9d8 565 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 566 unsigned short res;
567 unsigned int tmp;
568
569 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
570 if (! chip->in_ac97_init)
99b359ba 571 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 572 res = 0xffff;
573 } else {
574 res = iagetword(chip, reg + ac97->num * 0x80);
575 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
576 /* reset RCS and preserve other R/WC bits */
6b75a9d8 577 iputdword(chip, ICHREG(GLOB_STA), tmp &
84a43bd5 578 ~(chip->codec_ready_bits | ICH_GSCI));
1da177e4 579 if (! chip->in_ac97_init)
99b359ba 580 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 581 res = 0xffff;
582 }
583 }
584 return res;
585}
586
84a43bd5
TI		 587static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
588 unsigned int codec)
1da177e4
LT		 589{
590 unsigned int tmp;
591
592 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
593 iagetword(chip, codec * 0x80);
594 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
595 /* reset RCS and preserve other R/WC bits */
6b75a9d8 596 iputdword(chip, ICHREG(GLOB_STA), tmp &
84a43bd5 597 ~(chip->codec_ready_bits | ICH_GSCI));
1da177e4
LT		 598 }
599 }
600}
601
602/*
603 * access to AC97 for Ali5455
604 */
6b75a9d8 605static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
1da177e4
LT		 606{
607 int count = 0;
608 for (count = 0; count < 0x7f; count++) {
609 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
610 if (val & mask)
611 return 0;
612 }
79ba34b9
TI		 613 if (! chip->in_ac97_init)
614 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
1da177e4
LT		 615 return -EBUSY;
616}
617
6b75a9d8 618static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
1da177e4
LT		 619{
620 int time = 100;
79ba34b9
TI		 621 if (chip->buggy_semaphore)
622 return 0; /* just ignore ... */
67d8a3c1 623 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
1da177e4 624 udelay(1);
79ba34b9 625 if (! time && ! chip->in_ac97_init)
1da177e4
LT		 626 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
627 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
628}
629
6b75a9d8 630static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 631{
6b75a9d8 632 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 633 unsigned short data = 0xffff;
634
635 if (snd_intel8x0_ali_codec_semaphore(chip))
636 goto __err;
637 reg |= ALI_CPR_ADDR_READ;
638 if (ac97->num)
639 reg |= ALI_CPR_ADDR_SECONDARY;
640 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
641 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
642 goto __err;
643 data = igetword(chip, ICHREG(ALI_SPR));
644 __err:
645 return data;
646}
647
6b75a9d8
TI		 648static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
649 unsigned short val)
1da177e4 650{
6b75a9d8 651 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 652
653 if (snd_intel8x0_ali_codec_semaphore(chip))
654 return;
655 iputword(chip, ICHREG(ALI_CPR), val);
656 if (ac97->num)
657 reg |= ALI_CPR_ADDR_SECONDARY;
658 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
659 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
660}
661
662
663/*
664 * DMA I/O
665 */
6b75a9d8 666static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 667{
668 int idx;
669 u32 *bdbar = ichdev->bdbar;
670 unsigned long port = ichdev->reg_offset;
671
672 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
673 if (ichdev->size == ichdev->fragsize) {
674 ichdev->ack_reload = ichdev->ack = 2;
675 ichdev->fragsize1 = ichdev->fragsize >> 1;
676 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
677 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
678 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
679 ichdev->fragsize1 >> ichdev->pos_shift);
680 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
681 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
682 ichdev->fragsize1 >> ichdev->pos_shift);
683 }
684 ichdev->frags = 2;
685 } else {
686 ichdev->ack_reload = ichdev->ack = 1;
687 ichdev->fragsize1 = ichdev->fragsize;
688 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
6b75a9d8
TI		 689 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
690 (((idx >> 1) * ichdev->fragsize) %
691 ichdev->size));
1da177e4
LT		 692 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
693 ichdev->fragsize >> ichdev->pos_shift);
6b75a9d8 694#if 0
14ab0861 695 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
6b75a9d8
TI		 696 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
697#endif
1da177e4
LT		 698 }
699 ichdev->frags = ichdev->size / ichdev->fragsize;
700 }
701 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
702 ichdev->civ = 0;
703 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
704 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
705 ichdev->position = 0;
706#if 0
14ab0861
TI		 707 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
708 "period_size1 = 0x%x\n",
709 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
710 ichdev->fragsize1);
1da177e4
LT		 711#endif
712 /* clear interrupts */
713 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
714}
715
716#ifdef __i386__
717/*
718 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
719 * which aborts PCI busmaster for audio transfer. A workaround is to set
720 * the pages as non-cached. For details, see the errata in
721 * http://www.intel.com/design/chipsets/specupdt/245051.htm
722 */
723static void fill_nocache(void *buf, int size, int nocache)
724{
725 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
6d238cc4
AV		 726 if (nocache)
727 set_pages_uc(virt_to_page(buf), size);
728 else
729 set_pages_wb(virt_to_page(buf), size);
1da177e4
LT		 730}
731#else
6d238cc4 732#define fill_nocache(buf, size, nocache) do { ; } while (0)
1da177e4
LT		 733#endif
734
735/*
736 * Interrupt handler
737 */
738
6b75a9d8 739static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 740{
741 unsigned long port = ichdev->reg_offset;
883be793 742 unsigned long flags;
1da177e4
LT		 743 int status, civ, i, step;
744 int ack = 0;
745
883be793 746 spin_lock_irqsave(&chip->reg_lock, flags);
1da177e4
LT		 747 status = igetbyte(chip, port + ichdev->roff_sr);
748 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
749 if (!(status & ICH_BCIS)) {
750 step = 0;
751 } else if (civ == ichdev->civ) {
752 // snd_printd("civ same %d\n", civ);
753 step = 1;
754 ichdev->civ++;
755 ichdev->civ &= ICH_REG_LVI_MASK;
756 } else {
757 step = civ - ichdev->civ;
758 if (step < 0)
759 step += ICH_REG_LVI_MASK + 1;
760 // if (step != 1)
761 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
762 ichdev->civ = civ;
763 }
764
765 ichdev->position += step * ichdev->fragsize1;
766 if (! chip->in_measurement)
767 ichdev->position %= ichdev->size;
768 ichdev->lvi += step;
769 ichdev->lvi &= ICH_REG_LVI_MASK;
770 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
771 for (i = 0; i < step; i++) {
772 ichdev->lvi_frag++;
773 ichdev->lvi_frag %= ichdev->frags;
774 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
6b75a9d8 775#if 0
14ab0861
TI		 776 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
777 "all = 0x%x, 0x%x\n",
6b75a9d8
TI		 778 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
779 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
780 inl(port + 4), inb(port + ICH_REG_OFF_CR));
781#endif
1da177e4
LT		 782 if (--ichdev->ack == 0) {
783 ichdev->ack = ichdev->ack_reload;
784 ack = 1;
785 }
786 }
883be793 787 spin_unlock_irqrestore(&chip->reg_lock, flags);
1da177e4
LT		 788 if (ack && ichdev->substream) {
789 snd_pcm_period_elapsed(ichdev->substream);
790 }
791 iputbyte(chip, port + ichdev->roff_sr,
792 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
793}
794
7d12e780 795static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
1da177e4 796{
6b75a9d8
TI		 797 struct intel8x0 *chip = dev_id;
798 struct ichdev *ichdev;
1da177e4
LT		 799 unsigned int status;
800 unsigned int i;
801
802 status = igetdword(chip, chip->int_sta_reg);
803 if (status == 0xffffffff) /* we are not yet resumed */
804 return IRQ_NONE;
805
806 if ((status & chip->int_sta_mask) == 0) {
807 if (status) {
808 /* ack */
809 iputdword(chip, chip->int_sta_reg, status);
810 if (! chip->buggy_irq)
811 status = 0;
812 }
813 return IRQ_RETVAL(status);
814 }
815
816 for (i = 0; i < chip->bdbars_count; i++) {
817 ichdev = &chip->ichd[i];
818 if (status & ichdev->int_sta_mask)
819 snd_intel8x0_update(chip, ichdev);
820 }
821
822 /* ack them */
823 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
824
825 return IRQ_HANDLED;
826}
827
828/*
829 * PCM part
830 */
831
6b75a9d8 832static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 833{
6b75a9d8
TI		 834 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
835 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 836 unsigned char val = 0;
837 unsigned long port = ichdev->reg_offset;
838
839 switch (cmd) {
1da177e4 840 case SNDRV_PCM_TRIGGER_RESUME:
1cfe43d2
TI		 841 ichdev->suspended = 0;
842 /* fallthru */
843 case SNDRV_PCM_TRIGGER_START:
da2436a2 844 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4 845 val = ICH_IOCE | ICH_STARTBM;
da2436a2
JK		 846 ichdev->last_pos = ichdev->position;
847 ichdev->last_pos_jiffies = jiffies;
1da177e4 848 break;
1da177e4 849 case SNDRV_PCM_TRIGGER_SUSPEND:
1cfe43d2
TI		 850 ichdev->suspended = 1;
851 /* fallthru */
852 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 853 val = 0;
854 break;
855 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
856 val = ICH_IOCE;
857 break;
1da177e4
LT		 858 default:
859 return -EINVAL;
860 }
861 iputbyte(chip, port + ICH_REG_OFF_CR, val);
862 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
863 /* wait until DMA stopped */
864 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
865 /* reset whole DMA things */
866 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
867 }
868 return 0;
869}
870
6b75a9d8 871static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 872{
6b75a9d8
TI		 873 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
874 struct ichdev *ichdev = get_ichdev(substream);
1da177e4 875 unsigned long port = ichdev->reg_offset;
6b75a9d8
TI		 876 static int fiforeg[] = {
877 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
878 };
1da177e4
LT		 879 unsigned int val, fifo;
880
881 val = igetdword(chip, ICHREG(ALI_DMACR));
882 switch (cmd) {
1cfe43d2
TI		 883 case SNDRV_PCM_TRIGGER_RESUME:
884 ichdev->suspended = 0;
885 /* fallthru */
1da177e4
LT		 886 case SNDRV_PCM_TRIGGER_START:
887 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4
LT		 888 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
889 /* clear FIFO for synchronization of channels */
890 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
891 fifo &= ~(0xff << (ichdev->ali_slot % 4));
892 fifo |= 0x83 << (ichdev->ali_slot % 4);
893 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
894 }
895 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
896 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
6b75a9d8
TI		 897 /* start DMA */
898 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
1da177e4 899 break;
1cfe43d2
TI		 900 case SNDRV_PCM_TRIGGER_SUSPEND:
901 ichdev->suspended = 1;
902 /* fallthru */
1da177e4
LT		 903 case SNDRV_PCM_TRIGGER_STOP:
904 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
6b75a9d8
TI		 905 /* pause */
906 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
1da177e4
LT		 907 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
908 while (igetbyte(chip, port + ICH_REG_OFF_CR))
909 ;
910 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
911 break;
912 /* reset whole DMA things */
913 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
914 /* clear interrupts */
6b75a9d8
TI		 915 iputbyte(chip, port + ICH_REG_OFF_SR,
916 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
1da177e4
LT		 917 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
918 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
919 break;
920 default:
921 return -EINVAL;
922 }
923 return 0;
924}
925
6b75a9d8
TI		 926static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
927 struct snd_pcm_hw_params *hw_params)
1da177e4 928{
6b75a9d8
TI		 929 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
930 struct ichdev *ichdev = get_ichdev(substream);
931 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 932 int dbl = params_rate(hw_params) > 48000;
933 int err;
934
935 if (chip->fix_nocache && ichdev->page_attr_changed) {
936 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
937 ichdev->page_attr_changed = 0;
938 }
939 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
940 if (err < 0)
941 return err;
942 if (chip->fix_nocache) {
943 if (runtime->dma_area && ! ichdev->page_attr_changed) {
944 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
945 ichdev->page_attr_changed = 1;
946 }
947 }
948 if (ichdev->pcm_open_flag) {
949 snd_ac97_pcm_close(ichdev->pcm);
950 ichdev->pcm_open_flag = 0;
951 }
952 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
953 params_channels(hw_params),
954 ichdev->pcm->r[dbl].slots);
955 if (err >= 0) {
956 ichdev->pcm_open_flag = 1;
957 /* Force SPDIF setting */
958 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
6b75a9d8
TI		 959 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
960 params_rate(hw_params));
1da177e4
LT		 961 }
962 return err;
963}
964
6b75a9d8 965static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
1da177e4 966{
6b75a9d8
TI		 967 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
968 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 969
970 if (ichdev->pcm_open_flag) {
971 snd_ac97_pcm_close(ichdev->pcm);
972 ichdev->pcm_open_flag = 0;
973 }
974 if (chip->fix_nocache && ichdev->page_attr_changed) {
975 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
976 ichdev->page_attr_changed = 0;
977 }
978 return snd_pcm_lib_free_pages(substream);
979}
980
6b75a9d8
TI		 981static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
982 struct snd_pcm_runtime *runtime)
1da177e4
LT		 983{
984 unsigned int cnt;
985 int dbl = runtime->rate > 48000;
1cfe43d2
TI		 986
987 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 988 switch (chip->device_type) {
989 case DEVICE_ALI:
990 cnt = igetdword(chip, ICHREG(ALI_SCR));
991 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
992 if (runtime->channels == 4 || dbl)
993 cnt |= ICH_ALI_SC_PCM_4;
994 else if (runtime->channels == 6)
995 cnt |= ICH_ALI_SC_PCM_6;
996 iputdword(chip, ICHREG(ALI_SCR), cnt);
997 break;
998 case DEVICE_SIS:
999 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1000 cnt &= ~ICH_SIS_PCM_246_MASK;
1001 if (runtime->channels == 4 || dbl)
1002 cnt |= ICH_SIS_PCM_4;
1003 else if (runtime->channels == 6)
1004 cnt |= ICH_SIS_PCM_6;
1005 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1006 break;
1007 default:
1008 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1009 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1010 if (runtime->channels == 4 || dbl)
1011 cnt |= ICH_PCM_4;
1012 else if (runtime->channels == 6)
1013 cnt |= ICH_PCM_6;
4235a317
TI		 1014 else if (runtime->channels == 8)
1015 cnt |= ICH_PCM_8;
1da177e4
LT		 1016 if (chip->device_type == DEVICE_NFORCE) {
1017 /* reset to 2ch once to keep the 6 channel data in alignment,
1018 * to start from Front Left always
1019 */
1020 if (cnt & ICH_PCM_246_MASK) {
1021 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1022 spin_unlock_irq(&chip->reg_lock);
1023 msleep(50); /* grrr... */
1024 spin_lock_irq(&chip->reg_lock);
1025 }
1026 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1027 if (runtime->sample_bits > 16)
1028 cnt |= ICH_PCM_20BIT;
1029 }
1030 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1031 break;
1032 }
1cfe43d2 1033 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1034}
1035
6b75a9d8 1036static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 1037{
6b75a9d8
TI		 1038 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1039 struct snd_pcm_runtime *runtime = substream->runtime;
1040 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 1041
1042 ichdev->physbuf = runtime->dma_addr;
1043 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1044 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1da177e4
LT		 1045 if (ichdev->ichd == ICHD_PCMOUT) {
1046 snd_intel8x0_setup_pcm_out(chip, runtime);
1cfe43d2 1047 if (chip->device_type == DEVICE_INTEL_ICH4)
1da177e4 1048 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1da177e4
LT		 1049 }
1050 snd_intel8x0_setup_periods(chip, ichdev);
da2436a2 1051 ichdev->jiffy_to_bytes = (runtime->rate * 4 * ichdev->pos_shift) / HZ;
1da177e4
LT		 1052 return 0;
1053}
1054
6b75a9d8 1055static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1056{
6b75a9d8
TI		 1057 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1058 struct ichdev *ichdev = get_ichdev(substream);
1da177e4 1059 size_t ptr1, ptr;
da2436a2 1060 int civ, timeout = 10;
1da177e4
LT		 1061 unsigned int position;
1062
1063 spin_lock(&chip->reg_lock);
1064 do {
1065 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1066 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1067 position = ichdev->position;
1068 if (ptr1 == 0) {
1069 udelay(10);
1070 continue;
1071 }
1072 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1073 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1074 break;
1075 } while (timeout--);
da2436a2
JK		 1076 if (ptr1 != 0) {
1077 ptr1 <<= ichdev->pos_shift;
1078 ptr = ichdev->fragsize1 - ptr1;
1079 ptr += position;
1080 ichdev->last_pos = ptr;
1081 ichdev->last_pos_jiffies = jiffies;
1082 } else {
1083 ptr1 = jiffies - ichdev->last_pos_jiffies;
1084 if (ptr1)
1085 ptr1 -= 1;
1086 ptr = ichdev->last_pos + ptr1 * ichdev->jiffy_to_bytes;
1087 ptr %= ichdev->size;
1088 }
1da177e4
LT		 1089 spin_unlock(&chip->reg_lock);
1090 if (ptr >= ichdev->size)
1091 return 0;
1092 return bytes_to_frames(substream->runtime, ptr);
1093}
1094
6b75a9d8 1095static struct snd_pcm_hardware snd_intel8x0_stream =
1da177e4
LT		 1096{
1097 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1098 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1099 SNDRV_PCM_INFO_MMAP_VALID |
1100 SNDRV_PCM_INFO_PAUSE |
1101 SNDRV_PCM_INFO_RESUME),
1102 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1103 .rates = SNDRV_PCM_RATE_48000,
1104 .rate_min = 48000,
1105 .rate_max = 48000,
1106 .channels_min = 2,
1107 .channels_max = 2,
1108 .buffer_bytes_max = 128 * 1024,
1109 .period_bytes_min = 32,
1110 .period_bytes_max = 128 * 1024,
1111 .periods_min = 1,
1112 .periods_max = 1024,
1113 .fifo_size = 0,
1114};
1115
1116static unsigned int channels4[] = {
1117 2, 4,
1118};
1119
6b75a9d8 1120static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1da177e4
LT		 1121 .count = ARRAY_SIZE(channels4),
1122 .list = channels4,
1123 .mask = 0,
1124};
1125
1126static unsigned int channels6[] = {
1127 2, 4, 6,
1128};
1129
6b75a9d8 1130static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1da177e4
LT		 1131 .count = ARRAY_SIZE(channels6),
1132 .list = channels6,
1133 .mask = 0,
1134};
1135
4235a317
TI		 1136static unsigned int channels8[] = {
1137 2, 4, 6, 8,
1138};
1139
1140static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1141 .count = ARRAY_SIZE(channels8),
1142 .list = channels8,
1143 .mask = 0,
1144};
1145
6b75a9d8 1146static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1da177e4 1147{
6b75a9d8
TI		 1148 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1149 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1150 int err;
1151
1152 ichdev->substream = substream;
1153 runtime->hw = snd_intel8x0_stream;
1154 runtime->hw.rates = ichdev->pcm->rates;
1155 snd_pcm_limit_hw_rates(runtime);
1156 if (chip->device_type == DEVICE_SIS) {
1157 runtime->hw.buffer_bytes_max = 64*1024;
1158 runtime->hw.period_bytes_max = 64*1024;
1159 }
1160 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1161 return err;
1162 runtime->private_data = ichdev;
1163 return 0;
1164}
1165
6b75a9d8 1166static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1da177e4 1167{
6b75a9d8
TI		 1168 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1169 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1170 int err;
1171
1172 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1173 if (err < 0)
1174 return err;
1175
4235a317
TI		 1176 if (chip->multi8) {
1177 runtime->hw.channels_max = 8;
1178 snd_pcm_hw_constraint_list(runtime, 0,
1179 SNDRV_PCM_HW_PARAM_CHANNELS,
1180 &hw_constraints_channels8);
1181 } else if (chip->multi6) {
1da177e4 1182 runtime->hw.channels_max = 6;
6b75a9d8
TI		 1183 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1184 &hw_constraints_channels6);
1da177e4
LT		 1185 } else if (chip->multi4) {
1186 runtime->hw.channels_max = 4;
6b75a9d8
TI		 1187 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1188 &hw_constraints_channels4);
1da177e4
LT		 1189 }
1190 if (chip->dra) {
1191 snd_ac97_pcm_double_rate_rules(runtime);
1192 }
1193 if (chip->smp20bit) {
1194 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1195 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1196 }
1197 return 0;
1198}
1199
6b75a9d8 1200static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1da177e4 1201{
6b75a9d8 1202 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1203
1204 chip->ichd[ICHD_PCMOUT].substream = NULL;
1205 return 0;
1206}
1207
6b75a9d8 1208static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1da177e4 1209{
6b75a9d8 1210 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1211
1212 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1213}
1214
6b75a9d8 1215static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1da177e4 1216{
6b75a9d8 1217 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1218
1219 chip->ichd[ICHD_PCMIN].substream = NULL;
1220 return 0;
1221}
1222
6b75a9d8 1223static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1da177e4 1224{
6b75a9d8 1225 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1226
1227 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1228}
1229
6b75a9d8 1230static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1da177e4 1231{
6b75a9d8 1232 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1233
1234 chip->ichd[ICHD_MIC].substream = NULL;
1235 return 0;
1236}
1237
6b75a9d8 1238static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1da177e4 1239{
6b75a9d8 1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1241
1242 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1243}
1244
6b75a9d8 1245static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1da177e4 1246{
6b75a9d8 1247 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1248
1249 chip->ichd[ICHD_MIC2].substream = NULL;
1250 return 0;
1251}
1252
6b75a9d8 1253static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1da177e4 1254{
6b75a9d8 1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1256
1257 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1258}
1259
6b75a9d8 1260static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1da177e4 1261{
6b75a9d8 1262 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1263
1264 chip->ichd[ICHD_PCM2IN].substream = NULL;
1265 return 0;
1266}
1267
6b75a9d8 1268static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1269{
6b75a9d8 1270 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1271 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1272
1273 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1274}
1275
6b75a9d8 1276static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1277{
6b75a9d8 1278 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1279 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1280
1281 chip->ichd[idx].substream = NULL;
1282 return 0;
1283}
1284
6b75a9d8 1285static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1286{
6b75a9d8 1287 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1288 unsigned int val;
1289
1290 spin_lock_irq(&chip->reg_lock);
1291 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1292 val |= ICH_ALI_IF_AC97SP;
1293 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1294 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1295 spin_unlock_irq(&chip->reg_lock);
1296
1297 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1298}
1299
6b75a9d8 1300static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1301{
6b75a9d8 1302 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1303 unsigned int val;
1304
1305 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1306 spin_lock_irq(&chip->reg_lock);
1307 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1308 val &= ~ICH_ALI_IF_AC97SP;
1309 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1310 spin_unlock_irq(&chip->reg_lock);
1311
1312 return 0;
1313}
1314
1a183131 1315#if 0 // NYI
6b75a9d8 1316static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1da177e4 1317{
6b75a9d8 1318 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1319
1320 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1321}
1322
6b75a9d8 1323static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1da177e4 1324{
6b75a9d8 1325 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1326
1327 chip->ichd[ALID_SPDIFIN].substream = NULL;
1328 return 0;
1329}
1330
6b75a9d8 1331static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1332{
6b75a9d8 1333 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1334
1335 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1336}
1337
6b75a9d8 1338static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1339{
6b75a9d8 1340 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1341
1342 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1343 return 0;
1344}
1345#endif
1346
6b75a9d8 1347static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1da177e4
LT		 1348 .open = snd_intel8x0_playback_open,
1349 .close = snd_intel8x0_playback_close,
1350 .ioctl = snd_pcm_lib_ioctl,
1351 .hw_params = snd_intel8x0_hw_params,
1352 .hw_free = snd_intel8x0_hw_free,
1353 .prepare = snd_intel8x0_pcm_prepare,
1354 .trigger = snd_intel8x0_pcm_trigger,
1355 .pointer = snd_intel8x0_pcm_pointer,
1356};
1357
6b75a9d8 1358static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1da177e4
LT		 1359 .open = snd_intel8x0_capture_open,
1360 .close = snd_intel8x0_capture_close,
1361 .ioctl = snd_pcm_lib_ioctl,
1362 .hw_params = snd_intel8x0_hw_params,
1363 .hw_free = snd_intel8x0_hw_free,
1364 .prepare = snd_intel8x0_pcm_prepare,
1365 .trigger = snd_intel8x0_pcm_trigger,
1366 .pointer = snd_intel8x0_pcm_pointer,
1367};
1368
6b75a9d8 1369static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1da177e4
LT		 1370 .open = snd_intel8x0_mic_open,
1371 .close = snd_intel8x0_mic_close,
1372 .ioctl = snd_pcm_lib_ioctl,
1373 .hw_params = snd_intel8x0_hw_params,
1374 .hw_free = snd_intel8x0_hw_free,
1375 .prepare = snd_intel8x0_pcm_prepare,
1376 .trigger = snd_intel8x0_pcm_trigger,
1377 .pointer = snd_intel8x0_pcm_pointer,
1378};
1379
6b75a9d8 1380static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1da177e4
LT		 1381 .open = snd_intel8x0_mic2_open,
1382 .close = snd_intel8x0_mic2_close,
1383 .ioctl = snd_pcm_lib_ioctl,
1384 .hw_params = snd_intel8x0_hw_params,
1385 .hw_free = snd_intel8x0_hw_free,
1386 .prepare = snd_intel8x0_pcm_prepare,
1387 .trigger = snd_intel8x0_pcm_trigger,
1388 .pointer = snd_intel8x0_pcm_pointer,
1389};
1390
6b75a9d8 1391static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1da177e4
LT		 1392 .open = snd_intel8x0_capture2_open,
1393 .close = snd_intel8x0_capture2_close,
1394 .ioctl = snd_pcm_lib_ioctl,
1395 .hw_params = snd_intel8x0_hw_params,
1396 .hw_free = snd_intel8x0_hw_free,
1397 .prepare = snd_intel8x0_pcm_prepare,
1398 .trigger = snd_intel8x0_pcm_trigger,
1399 .pointer = snd_intel8x0_pcm_pointer,
1400};
1401
6b75a9d8 1402static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1da177e4
LT		 1403 .open = snd_intel8x0_spdif_open,
1404 .close = snd_intel8x0_spdif_close,
1405 .ioctl = snd_pcm_lib_ioctl,
1406 .hw_params = snd_intel8x0_hw_params,
1407 .hw_free = snd_intel8x0_hw_free,
1408 .prepare = snd_intel8x0_pcm_prepare,
1409 .trigger = snd_intel8x0_pcm_trigger,
1410 .pointer = snd_intel8x0_pcm_pointer,
1411};
1412
6b75a9d8 1413static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1da177e4
LT		 1414 .open = snd_intel8x0_playback_open,
1415 .close = snd_intel8x0_playback_close,
1416 .ioctl = snd_pcm_lib_ioctl,
1417 .hw_params = snd_intel8x0_hw_params,
1418 .hw_free = snd_intel8x0_hw_free,
1419 .prepare = snd_intel8x0_pcm_prepare,
1420 .trigger = snd_intel8x0_ali_trigger,
1421 .pointer = snd_intel8x0_pcm_pointer,
1422};
1423
6b75a9d8 1424static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1da177e4
LT		 1425 .open = snd_intel8x0_capture_open,
1426 .close = snd_intel8x0_capture_close,
1427 .ioctl = snd_pcm_lib_ioctl,
1428 .hw_params = snd_intel8x0_hw_params,
1429 .hw_free = snd_intel8x0_hw_free,
1430 .prepare = snd_intel8x0_pcm_prepare,
1431 .trigger = snd_intel8x0_ali_trigger,
1432 .pointer = snd_intel8x0_pcm_pointer,
1433};
1434
6b75a9d8 1435static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1da177e4
LT		 1436 .open = snd_intel8x0_mic_open,
1437 .close = snd_intel8x0_mic_close,
1438 .ioctl = snd_pcm_lib_ioctl,
1439 .hw_params = snd_intel8x0_hw_params,
1440 .hw_free = snd_intel8x0_hw_free,
1441 .prepare = snd_intel8x0_pcm_prepare,
1442 .trigger = snd_intel8x0_ali_trigger,
1443 .pointer = snd_intel8x0_pcm_pointer,
1444};
1445
6b75a9d8 1446static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1da177e4
LT		 1447 .open = snd_intel8x0_ali_ac97spdifout_open,
1448 .close = snd_intel8x0_ali_ac97spdifout_close,
1449 .ioctl = snd_pcm_lib_ioctl,
1450 .hw_params = snd_intel8x0_hw_params,
1451 .hw_free = snd_intel8x0_hw_free,
1452 .prepare = snd_intel8x0_pcm_prepare,
1453 .trigger = snd_intel8x0_ali_trigger,
1454 .pointer = snd_intel8x0_pcm_pointer,
1455};
1456
1a183131 1457#if 0 // NYI
6b75a9d8 1458static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1da177e4
LT		 1459 .open = snd_intel8x0_ali_spdifin_open,
1460 .close = snd_intel8x0_ali_spdifin_close,
1461 .ioctl = snd_pcm_lib_ioctl,
1462 .hw_params = snd_intel8x0_hw_params,
1463 .hw_free = snd_intel8x0_hw_free,
1464 .prepare = snd_intel8x0_pcm_prepare,
1465 .trigger = snd_intel8x0_pcm_trigger,
1466 .pointer = snd_intel8x0_pcm_pointer,
1467};
1468
6b75a9d8 1469static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1da177e4
LT		 1470 .open = snd_intel8x0_ali_spdifout_open,
1471 .close = snd_intel8x0_ali_spdifout_close,
1472 .ioctl = snd_pcm_lib_ioctl,
1473 .hw_params = snd_intel8x0_hw_params,
1474 .hw_free = snd_intel8x0_hw_free,
1475 .prepare = snd_intel8x0_pcm_prepare,
1476 .trigger = snd_intel8x0_pcm_trigger,
1477 .pointer = snd_intel8x0_pcm_pointer,
1478};
1479#endif // NYI
1480
1481struct ich_pcm_table {
1482 char *suffix;
6b75a9d8
TI		 1483 struct snd_pcm_ops *playback_ops;
1484 struct snd_pcm_ops *capture_ops;
1da177e4
LT		 1485 size_t prealloc_size;
1486 size_t prealloc_max_size;
1487 int ac97_idx;
1488};
1489
6b75a9d8
TI		 1490static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1491 struct ich_pcm_table *rec)
1da177e4 1492{
6b75a9d8 1493 struct snd_pcm *pcm;
1da177e4
LT		 1494 int err;
1495 char name[32];
1496
1497 if (rec->suffix)
1498 sprintf(name, "Intel ICH - %s", rec->suffix);
1499 else
1500 strcpy(name, "Intel ICH");
1501 err = snd_pcm_new(chip->card, name, device,
1502 rec->playback_ops ? 1 : 0,
1503 rec->capture_ops ? 1 : 0, &pcm);
1504 if (err < 0)
1505 return err;
1506
1507 if (rec->playback_ops)
1508 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1509 if (rec->capture_ops)
1510 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1511
1512 pcm->private_data = chip;
1513 pcm->info_flags = 0;
1514 if (rec->suffix)
1515 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1516 else
1517 strcpy(pcm->name, chip->card->shortname);
1518 chip->pcm[device] = pcm;
1519
6b75a9d8
TI		 1520 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1521 snd_dma_pci_data(chip->pci),
1da177e4
LT		 1522 rec->prealloc_size, rec->prealloc_max_size);
1523
1524 return 0;
1525}
1526
1527static struct ich_pcm_table intel_pcms[] __devinitdata = {
1528 {
1529 .playback_ops = &snd_intel8x0_playback_ops,
1530 .capture_ops = &snd_intel8x0_capture_ops,
1531 .prealloc_size = 64 * 1024,
1532 .prealloc_max_size = 128 * 1024,
1533 },
1534 {
1535 .suffix = "MIC ADC",
1536 .capture_ops = &snd_intel8x0_capture_mic_ops,
1537 .prealloc_size = 0,
1538 .prealloc_max_size = 128 * 1024,
1539 .ac97_idx = ICHD_MIC,
1540 },
1541 {
1542 .suffix = "MIC2 ADC",
1543 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1544 .prealloc_size = 0,
1545 .prealloc_max_size = 128 * 1024,
1546 .ac97_idx = ICHD_MIC2,
1547 },
1548 {
1549 .suffix = "ADC2",
1550 .capture_ops = &snd_intel8x0_capture2_ops,
1551 .prealloc_size = 0,
1552 .prealloc_max_size = 128 * 1024,
1553 .ac97_idx = ICHD_PCM2IN,
1554 },
1555 {
1556 .suffix = "IEC958",
1557 .playback_ops = &snd_intel8x0_spdif_ops,
1558 .prealloc_size = 64 * 1024,
1559 .prealloc_max_size = 128 * 1024,
1560 .ac97_idx = ICHD_SPBAR,
1561 },
1562};
1563
1564static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1565 {
1566 .playback_ops = &snd_intel8x0_playback_ops,
1567 .capture_ops = &snd_intel8x0_capture_ops,
1568 .prealloc_size = 64 * 1024,
1569 .prealloc_max_size = 128 * 1024,
1570 },
1571 {
1572 .suffix = "MIC ADC",
1573 .capture_ops = &snd_intel8x0_capture_mic_ops,
1574 .prealloc_size = 0,
1575 .prealloc_max_size = 128 * 1024,
1576 .ac97_idx = NVD_MIC,
1577 },
1578 {
1579 .suffix = "IEC958",
1580 .playback_ops = &snd_intel8x0_spdif_ops,
1581 .prealloc_size = 64 * 1024,
1582 .prealloc_max_size = 128 * 1024,
1583 .ac97_idx = NVD_SPBAR,
1584 },
1585};
1586
1587static struct ich_pcm_table ali_pcms[] __devinitdata = {
1588 {
1589 .playback_ops = &snd_intel8x0_ali_playback_ops,
1590 .capture_ops = &snd_intel8x0_ali_capture_ops,
1591 .prealloc_size = 64 * 1024,
1592 .prealloc_max_size = 128 * 1024,
1593 },
1594 {
1595 .suffix = "MIC ADC",
1596 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1597 .prealloc_size = 0,
1598 .prealloc_max_size = 128 * 1024,
1599 .ac97_idx = ALID_MIC,
1600 },
1601 {
1602 .suffix = "IEC958",
1603 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1a183131 1604 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1da177e4
LT		 1605 .prealloc_size = 64 * 1024,
1606 .prealloc_max_size = 128 * 1024,
1607 .ac97_idx = ALID_AC97SPDIFOUT,
1608 },
1609#if 0 // NYI
1610 {
1611 .suffix = "HW IEC958",
1612 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1613 .prealloc_size = 64 * 1024,
1614 .prealloc_max_size = 128 * 1024,
1615 },
1616#endif
1617};
1618
6b75a9d8 1619static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1da177e4
LT		 1620{
1621 int i, tblsize, device, err;
1622 struct ich_pcm_table *tbl, *rec;
1623
1624 switch (chip->device_type) {
1625 case DEVICE_INTEL_ICH4:
1626 tbl = intel_pcms;
1627 tblsize = ARRAY_SIZE(intel_pcms);
a9e99660
TI		 1628 if (spdif_aclink)
1629 tblsize--;
1da177e4
LT		 1630 break;
1631 case DEVICE_NFORCE:
1632 tbl = nforce_pcms;
1633 tblsize = ARRAY_SIZE(nforce_pcms);
a9e99660
TI		 1634 if (spdif_aclink)
1635 tblsize--;
1da177e4
LT		 1636 break;
1637 case DEVICE_ALI:
1638 tbl = ali_pcms;
1639 tblsize = ARRAY_SIZE(ali_pcms);
1640 break;
1641 default:
1642 tbl = intel_pcms;
1643 tblsize = 2;
1644 break;
1645 }
1646
1647 device = 0;
1648 for (i = 0; i < tblsize; i++) {
1649 rec = tbl + i;
1650 if (i > 0 && rec->ac97_idx) {
1651 /* activate PCM only when associated AC'97 codec */
1652 if (! chip->ichd[rec->ac97_idx].pcm)
1653 continue;
1654 }
1655 err = snd_intel8x0_pcm1(chip, device, rec);
1656 if (err < 0)
1657 return err;
1658 device++;
1659 }
1660
1661 chip->pcm_devs = device;
1662 return 0;
1663}
1664
1665
1666/*
1667 * Mixer part
1668 */
1669
6b75a9d8 1670static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1671{
6b75a9d8 1672 struct intel8x0 *chip = bus->private_data;
1da177e4
LT		 1673 chip->ac97_bus = NULL;
1674}
1675
6b75a9d8 1676static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1677{
6b75a9d8 1678 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 1679 chip->ac97[ac97->num] = NULL;
1680}
1681
1682static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1683 /* front PCM */
1684 {
1685 .exclusive = 1,
1686 .r = { {
1687 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1688 (1 << AC97_SLOT_PCM_RIGHT) |
1689 (1 << AC97_SLOT_PCM_CENTER) |
1690 (1 << AC97_SLOT_PCM_SLEFT) |
1691 (1 << AC97_SLOT_PCM_SRIGHT) |
1692 (1 << AC97_SLOT_LFE)
1693 },
1694 {
1695 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1696 (1 << AC97_SLOT_PCM_RIGHT) |
1697 (1 << AC97_SLOT_PCM_LEFT_0) |
1698 (1 << AC97_SLOT_PCM_RIGHT_0)
1699 }
1700 }
1701 },
1702 /* PCM IN #1 */
1703 {
1704 .stream = 1,
1705 .exclusive = 1,
1706 .r = { {
1707 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1708 (1 << AC97_SLOT_PCM_RIGHT)
1709 }
1710 }
1711 },
1712 /* MIC IN #1 */
1713 {
1714 .stream = 1,
1715 .exclusive = 1,
1716 .r = { {
1717 .slots = (1 << AC97_SLOT_MIC)
1718 }
1719 }
1720 },
1721 /* S/PDIF PCM */
1722 {
1723 .exclusive = 1,
1724 .spdif = 1,
1725 .r = { {
1726 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1727 (1 << AC97_SLOT_SPDIF_RIGHT2)
1728 }
1729 }
1730 },
1731 /* PCM IN #2 */
1732 {
1733 .stream = 1,
1734 .exclusive = 1,
1735 .r = { {
1736 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1737 (1 << AC97_SLOT_PCM_RIGHT)
1738 }
1739 }
1740 },
1741 /* MIC IN #2 */
1742 {
1743 .stream = 1,
1744 .exclusive = 1,
1745 .r = { {
1746 .slots = (1 << AC97_SLOT_MIC)
1747 }
1748 }
1749 },
1750};
1751
1752static struct ac97_quirk ac97_quirks[] __devinitdata = {
0d9ac27a
TI		 1753 {
1754 .subvendor = 0x0e11,
1755 .subdevice = 0x000e,
1756 .name = "Compaq Deskpro EN", /* AD1885 */
1757 .type = AC97_TUNE_HP_ONLY
1758 },
1da177e4 1759 {
6fd8b87f
JCD		 1760 .subvendor = 0x0e11,
1761 .subdevice = 0x008a,
1da177e4
LT		 1762 .name = "Compaq Evo W4000", /* AD1885 */
1763 .type = AC97_TUNE_HP_ONLY
1764 },
1765 {
6fd8b87f
JCD		 1766 .subvendor = 0x0e11,
1767 .subdevice = 0x00b8,
1da177e4
LT		 1768 .name = "Compaq Evo D510C",
1769 .type = AC97_TUNE_HP_ONLY
1770 },
1771 {
6fd8b87f
JCD		 1772 .subvendor = 0x0e11,
1773 .subdevice = 0x0860,
1da177e4
LT		 1774 .name = "HP/Compaq nx7010",
1775 .type = AC97_TUNE_MUTE_LED
1776 },
1777 {
6fd8b87f
JCD		 1778 .subvendor = 0x1014,
1779 .subdevice = 0x1f00,
1da177e4
LT		 1780 .name = "MS-9128",
1781 .type = AC97_TUNE_ALC_JACK
1782 },
5d529390
TI		 1783 {
1784 .subvendor = 0x1014,
1785 .subdevice = 0x0267,
1786 .name = "IBM NetVista A30p", /* AD1981B */
1787 .type = AC97_TUNE_HP_ONLY
b6a370b6
TI		 1788 },
1789 {
1790 .subvendor = 0x1025,
1791 .subdevice = 0x0082,
1792 .name = "Acer Travelmate 2310",
1793 .type = AC97_TUNE_HP_ONLY
5d529390 1794 },
72c8986c
DS		 1795 {
1796 .subvendor = 0x1025,
1797 .subdevice = 0x0083,
1798 .name = "Acer Aspire 3003LCi",
1799 .type = AC97_TUNE_HP_ONLY
1800 },
1da177e4 1801 {
6fd8b87f
JCD		 1802 .subvendor = 0x1028,
1803 .subdevice = 0x00d8,
1da177e4
LT		 1804 .name = "Dell Precision 530", /* AD1885 */
1805 .type = AC97_TUNE_HP_ONLY
1806 },
1807 {
6fd8b87f
JCD		 1808 .subvendor = 0x1028,
1809 .subdevice = 0x010d,
1da177e4
LT		 1810 .name = "Dell", /* which model? AD1885 */
1811 .type = AC97_TUNE_HP_ONLY
1812 },
1813 {
6fd8b87f
JCD		 1814 .subvendor = 0x1028,
1815 .subdevice = 0x0126,
1da177e4
LT		 1816 .name = "Dell Optiplex GX260", /* AD1981A */
1817 .type = AC97_TUNE_HP_ONLY
1818 },
1819 {
6fd8b87f
JCD		 1820 .subvendor = 0x1028,
1821 .subdevice = 0x012c,
1da177e4
LT		 1822 .name = "Dell Precision 650", /* AD1981A */
1823 .type = AC97_TUNE_HP_ONLY
1824 },
1825 {
6fd8b87f
JCD		 1826 .subvendor = 0x1028,
1827 .subdevice = 0x012d,
1da177e4
LT		 1828 .name = "Dell Precision 450", /* AD1981B*/
1829 .type = AC97_TUNE_HP_ONLY
1830 },
1831 {
6fd8b87f
JCD		 1832 .subvendor = 0x1028,
1833 .subdevice = 0x0147,
1da177e4
LT		 1834 .name = "Dell", /* which model? AD1981B*/
1835 .type = AC97_TUNE_HP_ONLY
1836 },
c9fe51c4
CB		 1837 {
1838 .subvendor = 0x1028,
1839 .subdevice = 0x0151,
1840 .name = "Dell Optiplex GX270", /* AD1981B */
1841 .type = AC97_TUNE_HP_ONLY
1842 },
1781a9af
DC		 1843 {
1844 .subvendor = 0x1028,
1845 .subdevice = 0x014e,
1846 .name = "Dell D800", /* STAC9750/51 */
1847 .type = AC97_TUNE_HP_ONLY
1848 },
1da177e4 1849 {
6fd8b87f
JCD		 1850 .subvendor = 0x1028,
1851 .subdevice = 0x0163,
1da177e4
LT		 1852 .name = "Dell Unknown", /* STAC9750/51 */
1853 .type = AC97_TUNE_HP_ONLY
1854 },
8286c53e
DC		 1855 {
1856 .subvendor = 0x1028,
1857 .subdevice = 0x0186,
1858 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1859 .type = AC97_TUNE_HP_MUTE_LED
1860 },
1861 {
1862 .subvendor = 0x1028,
1863 .subdevice = 0x0188,
1864 .name = "Dell Inspiron 6000",
1865 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1866 },
6d6f9156
KL		 1867 {
1868 .subvendor = 0x1028,
1869 .subdevice = 0x0191,
1870 .name = "Dell Inspiron 8600",
1871 .type = AC97_TUNE_HP_ONLY
1872 },
1da177e4 1873 {
6fd8b87f
JCD		 1874 .subvendor = 0x103c,
1875 .subdevice = 0x006d,
1da177e4
LT		 1876 .name = "HP zv5000",
1877 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1878 },
1879 { /* FIXME: which codec? */
6fd8b87f
JCD		 1880 .subvendor = 0x103c,
1881 .subdevice = 0x00c3,
1da177e4
LT		 1882 .name = "HP xw6000",
1883 .type = AC97_TUNE_HP_ONLY
1884 },
1885 {
6fd8b87f
JCD		 1886 .subvendor = 0x103c,
1887 .subdevice = 0x088c,
1da177e4 1888 .name = "HP nc8000",
8286c53e 1889 .type = AC97_TUNE_HP_MUTE_LED
1da177e4
LT		 1890 },
1891 {
6fd8b87f
JCD		 1892 .subvendor = 0x103c,
1893 .subdevice = 0x0890,
1da177e4
LT		 1894 .name = "HP nc6000",
1895 .type = AC97_TUNE_MUTE_LED
1896 },
e0c93cf3
DH		 1897 {
1898 .subvendor = 0x103c,
1899 .subdevice = 0x0934,
1900 .name = "HP nx8220",
1901 .type = AC97_TUNE_MUTE_LED
1902 },
1da177e4 1903 {
6fd8b87f
JCD		 1904 .subvendor = 0x103c,
1905 .subdevice = 0x129d,
1da177e4
LT		 1906 .name = "HP xw8000",
1907 .type = AC97_TUNE_HP_ONLY
1908 },
a0faefed
MG		 1909 {
1910 .subvendor = 0x103c,
1911 .subdevice = 0x0938,
1912 .name = "HP nc4200",
1913 .type = AC97_TUNE_HP_MUTE_LED
1914 },
1915 {
1916 .subvendor = 0x103c,
1917 .subdevice = 0x099c,
d82ed2ff 1918 .name = "HP nx6110/nc6120",
a0faefed
MG		 1919 .type = AC97_TUNE_HP_MUTE_LED
1920 },
1921 {
1922 .subvendor = 0x103c,
1923 .subdevice = 0x0944,
1924 .name = "HP nc6220",
1925 .type = AC97_TUNE_HP_MUTE_LED
1926 },
1927 {
1928 .subvendor = 0x103c,
1929 .subdevice = 0x0934,
1930 .name = "HP nc8220",
1931 .type = AC97_TUNE_HP_MUTE_LED
1932 },
1da177e4 1933 {
6fd8b87f
JCD		 1934 .subvendor = 0x103c,
1935 .subdevice = 0x12f1,
1da177e4
LT		 1936 .name = "HP xw8200", /* AD1981B*/
1937 .type = AC97_TUNE_HP_ONLY
1938 },
1939 {
6fd8b87f
JCD		 1940 .subvendor = 0x103c,
1941 .subdevice = 0x12f2,
1da177e4
LT		 1942 .name = "HP xw6200",
1943 .type = AC97_TUNE_HP_ONLY
1944 },
1945 {
6fd8b87f
JCD		 1946 .subvendor = 0x103c,
1947 .subdevice = 0x3008,
1da177e4
LT		 1948 .name = "HP xw4200", /* AD1981B*/
1949 .type = AC97_TUNE_HP_ONLY
1950 },
1951 {
6fd8b87f
JCD		 1952 .subvendor = 0x104d,
1953 .subdevice = 0x8197,
1da177e4
LT		 1954 .name = "Sony S1XP",
1955 .type = AC97_TUNE_INV_EAPD
1956 },
1957 {
6fd8b87f
JCD		 1958 .subvendor = 0x1043,
1959 .subdevice = 0x80f3,
1da177e4
LT		 1960 .name = "ASUS ICH5/AD1985",
1961 .type = AC97_TUNE_AD_SHARING
1962 },
1963 {
6fd8b87f
JCD		 1964 .subvendor = 0x10cf,
1965 .subdevice = 0x11c3,
1da177e4
LT		 1966 .name = "Fujitsu-Siemens E4010",
1967 .type = AC97_TUNE_HP_ONLY
1968 },
98c7f212
TI		 1969 {
1970 .subvendor = 0x10cf,
1971 .subdevice = 0x1225,
1972 .name = "Fujitsu-Siemens T3010",
1973 .type = AC97_TUNE_HP_ONLY
1974 },
1da177e4 1975 {
6fd8b87f
JCD		 1976 .subvendor = 0x10cf,
1977 .subdevice = 0x1253,
1da177e4
LT		 1978 .name = "Fujitsu S6210", /* STAC9750/51 */
1979 .type = AC97_TUNE_HP_ONLY
1980 },
37c34ffb
TI		 1981 {
1982 .subvendor = 0x10cf,
1983 .subdevice = 0x127d,
1984 .name = "Fujitsu Lifebook P7010",
1985 .type = AC97_TUNE_HP_ONLY
1986 },
8286c53e
DC		 1987 {
1988 .subvendor = 0x10cf,
1989 .subdevice = 0x127e,
1990 .name = "Fujitsu Lifebook C1211D",
1991 .type = AC97_TUNE_HP_ONLY
1992 },
9970dce5
TI		 1993 {
1994 .subvendor = 0x10cf,
1995 .subdevice = 0x12ec,
1996 .name = "Fujitsu-Siemens 4010",
1997 .type = AC97_TUNE_HP_ONLY
1998 },
2eb061f4
JK		 1999 {
2000 .subvendor = 0x10cf,
2001 .subdevice = 0x12f2,
2002 .name = "Fujitsu-Siemens Celsius H320",
2003 .type = AC97_TUNE_SWAP_HP
2004 },
1da177e4 2005 {
6fd8b87f
JCD		 2006 .subvendor = 0x10f1,
2007 .subdevice = 0x2665,
1da177e4
LT		 2008 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2009 .type = AC97_TUNE_HP_ONLY
2010 },
2011 {
6fd8b87f
JCD		 2012 .subvendor = 0x10f1,
2013 .subdevice = 0x2885,
1da177e4
LT		 2014 .name = "AMD64 Mobo", /* ALC650 */
2015 .type = AC97_TUNE_HP_ONLY
2016 },
4f42bcc1
TI		 2017 {
2018 .subvendor = 0x10f1,
2019 .subdevice = 0x2895,
2020 .name = "Tyan Thunder K8WE",
2021 .type = AC97_TUNE_HP_ONLY
2022 },
6c504447
KP		 2023 {
2024 .subvendor = 0x10f7,
2025 .subdevice = 0x834c,
2026 .name = "Panasonic CF-R4",
2027 .type = AC97_TUNE_HP_ONLY,
2028 },
1da177e4 2029 {
6fd8b87f
JCD		 2030 .subvendor = 0x110a,
2031 .subdevice = 0x0056,
1da177e4
LT		 2032 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2033 .type = AC97_TUNE_HP_ONLY
2034 },
2035 {
6fd8b87f
JCD		 2036 .subvendor = 0x11d4,
2037 .subdevice = 0x5375,
1da177e4
LT		 2038 .name = "ADI AD1985 (discrete)",
2039 .type = AC97_TUNE_HP_ONLY
2040 },
2041 {
6fd8b87f
JCD		 2042 .subvendor = 0x1462,
2043 .subdevice = 0x5470,
1da177e4
LT		 2044 .name = "MSI P4 ATX 645 Ultra",
2045 .type = AC97_TUNE_HP_ONLY
2046 },
2047 {
6fd8b87f
JCD		 2048 .subvendor = 0x1734,
2049 .subdevice = 0x0088,
1da177e4
LT		 2050 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2051 .type = AC97_TUNE_HP_ONLY
2052 },
2053 {
6fd8b87f
JCD		 2054 .subvendor = 0x8086,
2055 .subdevice = 0x2000,
1da177e4
LT		 2056 .mask = 0xfff0,
2057 .name = "Intel ICH5/AD1985",
2058 .type = AC97_TUNE_AD_SHARING
2059 },
2060 {
6fd8b87f
JCD		 2061 .subvendor = 0x8086,
2062 .subdevice = 0x4000,
1da177e4
LT		 2063 .mask = 0xfff0,
2064 .name = "Intel ICH5/AD1985",
2065 .type = AC97_TUNE_AD_SHARING
2066 },
2067 {
6fd8b87f
JCD		 2068 .subvendor = 0x8086,
2069 .subdevice = 0x4856,
1da177e4
LT		 2070 .name = "Intel D845WN (82801BA)",
2071 .type = AC97_TUNE_SWAP_HP
2072 },
2073 {
6fd8b87f
JCD		 2074 .subvendor = 0x8086,
2075 .subdevice = 0x4d44,
1da177e4
LT		 2076 .name = "Intel D850EMV2", /* AD1885 */
2077 .type = AC97_TUNE_HP_ONLY
2078 },
2079 {
6fd8b87f
JCD		 2080 .subvendor = 0x8086,
2081 .subdevice = 0x4d56,
1da177e4
LT		 2082 .name = "Intel ICH/AD1885",
2083 .type = AC97_TUNE_HP_ONLY
2084 },
2085 {
6fd8b87f
JCD		 2086 .subvendor = 0x8086,
2087 .subdevice = 0x6000,
1da177e4
LT		 2088 .mask = 0xfff0,
2089 .name = "Intel ICH5/AD1985",
2090 .type = AC97_TUNE_AD_SHARING
2091 },
2092 {
6fd8b87f
JCD		 2093 .subvendor = 0x8086,
2094 .subdevice = 0xe000,
1da177e4
LT		 2095 .mask = 0xfff0,
2096 .name = "Intel ICH5/AD1985",
2097 .type = AC97_TUNE_AD_SHARING
2098 },
2099#if 0 /* FIXME: this seems wrong on most boards */
2100 {
6fd8b87f
JCD		 2101 .subvendor = 0x8086,
2102 .subdevice = 0xa000,
1da177e4
LT		 2103 .mask = 0xfff0,
2104 .name = "Intel ICH5/AD1985",
2105 .type = AC97_TUNE_HP_ONLY
2106 },
2107#endif
2108 { } /* terminator */
2109};
2110
6b75a9d8
TI		 2111static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2112 const char *quirk_override)
1da177e4 2113{
6b75a9d8
TI		 2114 struct snd_ac97_bus *pbus;
2115 struct snd_ac97_template ac97;
1da177e4
LT		 2116 int err;
2117 unsigned int i, codecs;
2118 unsigned int glob_sta = 0;
6b75a9d8
TI		 2119 struct snd_ac97_bus_ops *ops;
2120 static struct snd_ac97_bus_ops standard_bus_ops = {
1da177e4
LT		 2121 .write = snd_intel8x0_codec_write,
2122 .read = snd_intel8x0_codec_read,
2123 };
6b75a9d8 2124 static struct snd_ac97_bus_ops ali_bus_ops = {
1da177e4
LT		 2125 .write = snd_intel8x0_ali_codec_write,
2126 .read = snd_intel8x0_ali_codec_read,
2127 };
2128
2129 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
a9e99660
TI		 2130 if (!spdif_aclink) {
2131 switch (chip->device_type) {
2132 case DEVICE_NFORCE:
2133 chip->spdif_idx = NVD_SPBAR;
2134 break;
2135 case DEVICE_ALI:
2136 chip->spdif_idx = ALID_AC97SPDIFOUT;
2137 break;
2138 case DEVICE_INTEL_ICH4:
2139 chip->spdif_idx = ICHD_SPBAR;
2140 break;
2141 };
2142 }
1da177e4
LT		 2143
2144 chip->in_ac97_init = 1;
2145
2146 memset(&ac97, 0, sizeof(ac97));
2147 ac97.private_data = chip;
2148 ac97.private_free = snd_intel8x0_mixer_free_ac97;
f1a63a38 2149 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1da177e4
LT		 2150 if (chip->xbox)
2151 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2152 if (chip->device_type != DEVICE_ALI) {
2153 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2154 ops = &standard_bus_ops;
84a43bd5
TI		 2155 chip->in_sdin_init = 1;
2156 codecs = 0;
2157 for (i = 0; i < chip->max_codecs; i++) {
2158 if (! (glob_sta & chip->codec_bit[i]))
2159 continue;
2160 if (chip->device_type == DEVICE_INTEL_ICH4) {
2161 snd_intel8x0_codec_read_test(chip, codecs);
2162 chip->ac97_sdin[codecs] =
2163 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
da3cec35
TI		 2164 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2165 chip->ac97_sdin[codecs] = 0;
84a43bd5
TI		 2166 } else
2167 chip->ac97_sdin[codecs] = i;
2168 codecs++;
1da177e4 2169 }
84a43bd5
TI		 2170 chip->in_sdin_init = 0;
2171 if (! codecs)
2172 codecs = 1;
1da177e4
LT		 2173 } else {
2174 ops = &ali_bus_ops;
2175 codecs = 1;
2176 /* detect the secondary codec */
2177 for (i = 0; i < 100; i++) {
2178 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2179 if (reg & 0x40) {
2180 codecs = 2;
2181 break;
2182 }
2183 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2184 udelay(1);
2185 }
2186 }
2187 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2188 goto __err;
2189 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1da177e4
LT		 2190 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2191 pbus->clock = ac97_clock;
2192 /* FIXME: my test board doesn't work well with VRA... */
2193 if (chip->device_type == DEVICE_ALI)
2194 pbus->no_vra = 1;
2195 else
2196 pbus->dra = 1;
2197 chip->ac97_bus = pbus;
84a43bd5 2198 chip->ncodecs = codecs;
1da177e4
LT		 2199
2200 ac97.pci = chip->pci;
2201 for (i = 0; i < codecs; i++) {
2202 ac97.num = i;
2203 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2204 if (err != -EACCES)
2205 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2206 if (i == 0)
2207 goto __err;
1da177e4
LT		 2208 }
2209 }
2210 /* tune up the primary codec */
2211 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2212 /* enable separate SDINs for ICH4 */
2213 if (chip->device_type == DEVICE_INTEL_ICH4)
2214 pbus->isdin = 1;
2215 /* find the available PCM streams */
2216 i = ARRAY_SIZE(ac97_pcm_defs);
2217 if (chip->device_type != DEVICE_INTEL_ICH4)
2218 i -= 2; /* do not allocate PCM2IN and MIC2 */
2219 if (chip->spdif_idx < 0)
2220 i--; /* do not allocate S/PDIF */
2221 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2222 if (err < 0)
2223 goto __err;
2224 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2225 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2226 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2227 if (chip->spdif_idx >= 0)
2228 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2229 if (chip->device_type == DEVICE_INTEL_ICH4) {
2230 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2231 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2232 }
2233 /* enable separate SDINs for ICH4 */
2234 if (chip->device_type == DEVICE_INTEL_ICH4) {
2235 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2236 u8 tmp = igetbyte(chip, ICHREG(SDM));
2237 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2238 if (pcm) {
2239 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2240 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2241 for (i = 1; i < 4; i++) {
2242 if (pcm->r[0].codec[i]) {
2243 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2244 break;
2245 }
2246 }
2247 } else {
2248 tmp &= ~ICH_SE; /* steer disable */
2249 }
2250 iputbyte(chip, ICHREG(SDM), tmp);
2251 }
2252 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2253 chip->multi4 = 1;
4235a317 2254 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
1da177e4 2255 chip->multi6 = 1;
4235a317
TI		 2256 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2257 chip->multi8 = 1;
2258 }
1da177e4
LT		 2259 }
2260 if (pbus->pcms[0].r[1].rslots[0]) {
2261 chip->dra = 1;
2262 }
2263 if (chip->device_type == DEVICE_INTEL_ICH4) {
2264 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2265 chip->smp20bit = 1;
2266 }
a9e99660 2267 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2268 /* 48kHz only */
2269 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2270 }
a9e99660 2271 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
1da177e4
LT		 2272 /* use slot 10/11 for SPDIF */
2273 u32 val;
2274 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2275 val |= ICH_PCM_SPDIF_1011;
2276 iputdword(chip, ICHREG(GLOB_CNT), val);
2277 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2278 }
2279 chip->in_ac97_init = 0;
2280 return 0;
2281
2282 __err:
2283 /* clear the cold-reset bit for the next chance */
2284 if (chip->device_type != DEVICE_ALI)
6b75a9d8
TI		 2285 iputdword(chip, ICHREG(GLOB_CNT),
2286 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1da177e4
LT		 2287 return err;
2288}
2289
2290
2291/*
2292 *
2293 */
2294
6b75a9d8 2295static void do_ali_reset(struct intel8x0 *chip)
1da177e4
LT		 2296{
2297 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2298 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2299 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2300 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2301 iputdword(chip, ICHREG(ALI_INTERFACECR),
d78bec21 2302 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1da177e4
LT		 2303 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2304 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2305}
2306
e3e9c5e7
TLSC		 2307#ifdef CONFIG_SND_AC97_POWER_SAVE
2308static struct snd_pci_quirk ich_chip_reset_mode[] = {
2309 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2310 { } /* end */
2311};
1da177e4 2312
e3e9c5e7
TLSC		 2313static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2314{
2315 unsigned int cnt;
1da177e4 2316 /* ACLink on, 2 channels */
e3e9c5e7
TLSC		 2317
2318 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2319 return -EIO;
2320
1da177e4
LT		 2321 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2322 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
e3e9c5e7 2323
6dbe6628
TI		 2324 /* do cold reset - the full ac97 powerdown may leave the controller
2325 * in a warm state but actually it cannot communicate with the codec.
2326 */
2327 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2328 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2329 udelay(10);
2330 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2331 msleep(1);
e3e9c5e7
TLSC		 2332 return 0;
2333}
2334#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2335 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
6dbe6628 2336#else
e1672800 2337#define snd_intel8x0_ich_chip_cold_reset(chip) 0
e3e9c5e7
TLSC		 2338#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2339#endif
2340
2341static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2342{
2343 unsigned long end_time;
2344 unsigned int cnt;
2345 /* ACLink on, 2 channels */
2346 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2347 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
1da177e4
LT		 2348 /* finish cold or do warm reset */
2349 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2350 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2351 end_time = (jiffies + (HZ / 4)) + 1;
2352 do {
2353 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
e3e9c5e7 2354 return 0;
954bea35 2355 schedule_timeout_uninterruptible(1);
1da177e4 2356 } while (time_after_eq(end_time, jiffies));
6b75a9d8
TI		 2357 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2358 igetdword(chip, ICHREG(GLOB_CNT)));
1da177e4 2359 return -EIO;
e3e9c5e7
TLSC		 2360}
2361
2362static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2363{
2364 unsigned long end_time;
2365 unsigned int status, nstatus;
2366 unsigned int cnt;
2367 int err;
2368
2369 /* put logic to right state */
2370 /* first clear status bits */
2371 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2372 if (chip->device_type == DEVICE_NFORCE)
2373 status |= ICH_NVSPINT;
2374 cnt = igetdword(chip, ICHREG(GLOB_STA));
2375 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2376
2377 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2378 err = snd_intel8x0_ich_chip_cold_reset(chip);
2379 else
2380 err = snd_intel8x0_ich_chip_reset(chip);
2381 if (err < 0)
2382 return err;
1da177e4 2383
1da177e4
LT		 2384 if (probing) {
2385 /* wait for any codec ready status.
2386 * Once it becomes ready it should remain ready
2387 * as long as we do not disable the ac97 link.
2388 */
2389 end_time = jiffies + HZ;
2390 do {
6b75a9d8 2391 status = igetdword(chip, ICHREG(GLOB_STA)) &
84a43bd5 2392 chip->codec_isr_bits;
1da177e4
LT		 2393 if (status)
2394 break;
954bea35 2395 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2396 } while (time_after_eq(end_time, jiffies));
2397 if (! status) {
2398 /* no codec is found */
6b75a9d8
TI		 2399 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2400 igetdword(chip, ICHREG(GLOB_STA)));
1da177e4
LT		 2401 return -EIO;
2402 }
2403
1da177e4
LT		 2404 /* wait for other codecs ready status. */
2405 end_time = jiffies + HZ / 4;
84a43bd5
TI		 2406 while (status != chip->codec_isr_bits &&
2407 time_after_eq(end_time, jiffies)) {
954bea35 2408 schedule_timeout_uninterruptible(1);
84a43bd5
TI		 2409 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2410 chip->codec_isr_bits;
1da177e4
LT		 2411 }
2412
2413 } else {
2414 /* resume phase */
2415 int i;
2416 status = 0;
84a43bd5 2417 for (i = 0; i < chip->ncodecs; i++)
1da177e4 2418 if (chip->ac97[i])
84a43bd5 2419 status |= chip->codec_bit[chip->ac97_sdin[i]];
1da177e4
LT		 2420 /* wait until all the probed codecs are ready */
2421 end_time = jiffies + HZ;
2422 do {
6b75a9d8 2423 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
84a43bd5 2424 chip->codec_isr_bits;
1da177e4
LT		 2425 if (status == nstatus)
2426 break;
954bea35 2427 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2428 } while (time_after_eq(end_time, jiffies));
2429 }
2430
2431 if (chip->device_type == DEVICE_SIS) {
2432 /* unmute the output on SIS7012 */
2433 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2434 }
a9e99660 2435 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2436 /* enable SPDIF interrupt */
2437 unsigned int val;
2438 pci_read_config_dword(chip->pci, 0x4c, &val);
2439 val |= 0x1000000;
2440 pci_write_config_dword(chip->pci, 0x4c, val);
2441 }
2442 return 0;
2443}
2444
6b75a9d8 2445static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
1da177e4
LT		 2446{
2447 u32 reg;
2448 int i = 0;
2449
2450 reg = igetdword(chip, ICHREG(ALI_SCR));
2451 if ((reg & 2) == 0) /* Cold required */
2452 reg |= 2;
2453 else
2454 reg |= 1; /* Warm */
2455 reg &= ~0x80000000; /* ACLink on */
2456 iputdword(chip, ICHREG(ALI_SCR), reg);
2457
2458 for (i = 0; i < HZ / 2; i++) {
2459 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2460 goto __ok;
954bea35 2461 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2462 }
2463 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2464 if (probing)
2465 return -EIO;
2466
2467 __ok:
2468 for (i = 0; i < HZ / 2; i++) {
2469 reg = igetdword(chip, ICHREG(ALI_RTSR));
2470 if (reg & 0x80) /* primary codec */
2471 break;
2472 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
954bea35 2473 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2474 }
2475
2476 do_ali_reset(chip);
2477 return 0;
2478}
2479
6b75a9d8 2480static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
1da177e4 2481{
253b999f 2482 unsigned int i, timeout;
1da177e4
LT		 2483 int err;
2484
2485 if (chip->device_type != DEVICE_ALI) {
2486 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2487 return err;
2488 iagetword(chip, 0); /* clear semaphore flag */
2489 } else {
2490 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2491 return err;
2492 }
2493
2494 /* disable interrupts */
2495 for (i = 0; i < chip->bdbars_count; i++)
2496 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2497 /* reset channels */
2498 for (i = 0; i < chip->bdbars_count; i++)
2499 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
253b999f
JK		 2500 for (i = 0; i < chip->bdbars_count; i++) {
2501 timeout = 100000;
2502 while (--timeout != 0) {
2503 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2504 break;
2505 }
2506 if (timeout == 0)
2507 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2508 }
1da177e4
LT		 2509 /* initialize Buffer Descriptor Lists */
2510 for (i = 0; i < chip->bdbars_count; i++)
6b75a9d8
TI		 2511 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2512 chip->ichd[i].bdbar_addr);
1da177e4
LT		 2513 return 0;
2514}
2515
6b75a9d8 2516static int snd_intel8x0_free(struct intel8x0 *chip)
1da177e4
LT		 2517{
2518 unsigned int i;
2519
2520 if (chip->irq < 0)
2521 goto __hw_end;
2522 /* disable interrupts */
2523 for (i = 0; i < chip->bdbars_count; i++)
2524 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2525 /* reset channels */
2526 for (i = 0; i < chip->bdbars_count; i++)
2527 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
a9e99660 2528 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
1da177e4
LT		 2529 /* stop the spdif interrupt */
2530 unsigned int val;
2531 pci_read_config_dword(chip->pci, 0x4c, &val);
2532 val &= ~0x1000000;
2533 pci_write_config_dword(chip->pci, 0x4c, val);
2534 }
2535 /* --- */
f000fd80 2536
1da177e4
LT		 2537 __hw_end:
2538 if (chip->irq >= 0)
6b75a9d8 2539 free_irq(chip->irq, chip);
1da177e4
LT		 2540 if (chip->bdbars.area) {
2541 if (chip->fix_nocache)
2542 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2543 snd_dma_free_pages(&chip->bdbars);
2544 }
3388c37e
TI		 2545 if (chip->addr)
2546 pci_iounmap(chip->pci, chip->addr);
2547 if (chip->bmaddr)
2548 pci_iounmap(chip->pci, chip->bmaddr);
1da177e4
LT		 2549 pci_release_regions(chip->pci);
2550 pci_disable_device(chip->pci);
2551 kfree(chip);
2552 return 0;
2553}
2554
2555#ifdef CONFIG_PM
2556/*
2557 * power management
2558 */
5809c6c4 2559static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2560{
5809c6c4
TI		 2561 struct snd_card *card = pci_get_drvdata(pci);
2562 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2563 int i;
2564
5809c6c4 2565 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 2566 for (i = 0; i < chip->pcm_devs; i++)
2567 snd_pcm_suspend_all(chip->pcm[i]);
2568 /* clear nocache */
2569 if (chip->fix_nocache) {
2570 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2571 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2572 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2573 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2574 if (runtime->dma_area)
2575 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2576 }
2577 }
2578 }
84a43bd5 2579 for (i = 0; i < chip->ncodecs; i++)
5809c6c4 2580 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2581 if (chip->device_type == DEVICE_INTEL_ICH4)
2582 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
adbedd34 2583
30b35399 2584 if (chip->irq >= 0) {
6b75a9d8 2585 free_irq(chip->irq, chip);
30b35399
TI		 2586 chip->irq = -1;
2587 }
5809c6c4
TI		 2588 pci_disable_device(pci);
2589 pci_save_state(pci);
19bfafb2
TK		 2590 /* The call below may disable built-in speaker on some laptops
2591 * after S2RAM. So, don't touch it.
2592 */
2593 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
1da177e4
LT		 2594 return 0;
2595}
2596
5809c6c4 2597static int intel8x0_resume(struct pci_dev *pci)
1da177e4 2598{
5809c6c4
TI		 2599 struct snd_card *card = pci_get_drvdata(pci);
2600 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2601 int i;
2602
30b35399 2603 pci_set_power_state(pci, PCI_D0);
5809c6c4 2604 pci_restore_state(pci);
30b35399
TI		 2605 if (pci_enable_device(pci) < 0) {
2606 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2607 "disabling device\n");
2608 snd_card_disconnect(card);
2609 return -EIO;
2610 }
5809c6c4 2611 pci_set_master(pci);
2078f38c 2612 snd_intel8x0_chip_init(chip, 0);
30b35399 2613 if (request_irq(pci->irq, snd_intel8x0_interrupt,
437a5a46 2614 IRQF_SHARED, card->shortname, chip)) {
30b35399
TI		 2615 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2616 "disabling device\n", pci->irq);
2617 snd_card_disconnect(card);
2618 return -EIO;
2619 }
5809c6c4 2620 chip->irq = pci->irq;
90158b83 2621 synchronize_irq(chip->irq);
1da177e4 2622
52b72388 2623 /* re-initialize mixer stuff */
a9e99660 2624 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
52b72388
TI		 2625 /* enable separate SDINs for ICH4 */
2626 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2627 /* use slot 10/11 for SPDIF */
2628 iputdword(chip, ICHREG(GLOB_CNT),
2629 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2630 ICH_PCM_SPDIF_1011);
2631 }
2632
1da177e4
LT		 2633 /* refill nocache */
2634 if (chip->fix_nocache)
2635 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2636
84a43bd5 2637 for (i = 0; i < chip->ncodecs; i++)
5809c6c4 2638 snd_ac97_resume(chip->ac97[i]);
1da177e4
LT		 2639
2640 /* refill nocache */
2641 if (chip->fix_nocache) {
2642 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2643 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2644 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2645 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2646 if (runtime->dma_area)
2647 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2648 }
2649 }
2650 }
2651
1cfe43d2
TI		 2652 /* resume status */
2653 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2654 struct ichdev *ichdev = &chip->ichd[i];
1cfe43d2
TI		 2655 unsigned long port = ichdev->reg_offset;
2656 if (! ichdev->substream || ! ichdev->suspended)
2657 continue;
2658 if (ichdev->ichd == ICHD_PCMOUT)
2659 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2660 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2661 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2662 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2663 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2664 }
2665
5809c6c4 2666 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2667 return 0;
2668}
2669#endif /* CONFIG_PM */
2670
2671#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2672
6b75a9d8 2673static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
1da177e4 2674{
6b75a9d8
TI		 2675 struct snd_pcm_substream *subs;
2676 struct ichdev *ichdev;
1da177e4 2677 unsigned long port;
920e4ae3 2678 unsigned long pos, pos1, t;
2ec775e7 2679 int civ, timeout = 1000, attempt = 1;
920e4ae3 2680 struct timespec start_time, stop_time;
1da177e4
LT		 2681
2682 if (chip->ac97_bus->clock != 48000)
2683 return; /* specified in module option */
2684
2ec775e7 2685 __again:
1da177e4
LT		 2686 subs = chip->pcm[0]->streams[0].substream;
2687 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
99b359ba 2688 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
1da177e4
LT		 2689 return;
2690 }
2691 ichdev = &chip->ichd[ICHD_PCMOUT];
2692 ichdev->physbuf = subs->dma_buffer.addr;
29dab4fd 2693 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
1da177e4
LT		 2694 ichdev->substream = NULL; /* don't process interrupts */
2695
2696 /* set rate */
2697 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2698 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2699 return;
2700 }
2701 snd_intel8x0_setup_periods(chip, ichdev);
2702 port = ichdev->reg_offset;
2703 spin_lock_irq(&chip->reg_lock);
2704 chip->in_measurement = 1;
2705 /* trigger */
2706 if (chip->device_type != DEVICE_ALI)
2707 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2708 else {
2709 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2710 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2711 }
920e4ae3 2712 do_posix_clock_monotonic_gettime(&start_time);
1da177e4 2713 spin_unlock_irq(&chip->reg_lock);
ef21ca24 2714 msleep(50);
1da177e4
LT		 2715 spin_lock_irq(&chip->reg_lock);
2716 /* check the position */
920e4ae3
JK		 2717 do {
2718 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2719 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2720 if (pos1 == 0) {
2721 udelay(10);
2722 continue;
2723 }
2724 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2725 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2726 break;
2727 } while (timeout--);
da2436a2
JK		 2728 if (pos1 == 0) { /* oops, this value is not reliable */
2729 pos = 0;
2730 } else {
2731 pos = ichdev->fragsize1;
2732 pos -= pos1 << ichdev->pos_shift;
2733 pos += ichdev->position;
2734 }
1da177e4 2735 chip->in_measurement = 0;
920e4ae3 2736 do_posix_clock_monotonic_gettime(&stop_time);
1da177e4
LT		 2737 /* stop */
2738 if (chip->device_type == DEVICE_ALI) {
d78bec21 2739 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
1da177e4
LT		 2740 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2741 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2742 ;
2743 } else {
2744 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2745 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2746 ;
2747 }
2748 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2749 spin_unlock_irq(&chip->reg_lock);
2750
da2436a2
JK		 2751 if (pos == 0) {
2752 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2ec775e7
JK		 2753 __retry:
2754 if (attempt < 2) {
2755 attempt++;
2756 goto __again;
2757 }
da2436a2
JK		 2758 return;
2759 }
2760
920e4ae3 2761 pos /= 4;
1da177e4
LT		 2762 t = stop_time.tv_sec - start_time.tv_sec;
2763 t *= 1000000;
920e4ae3
JK		 2764 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2765 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
1da177e4 2766 if (t == 0) {
920e4ae3 2767 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2ec775e7 2768 goto __retry;
1da177e4 2769 }
920e4ae3 2770 pos *= 1000;
1da177e4 2771 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2ec775e7 2772 if (pos < 40000 || pos >= 60000) {
1da177e4
LT		 2773 /* abnormal value. hw problem? */
2774 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2ec775e7
JK		 2775 goto __retry;
2776 } else if (pos > 40500 && pos < 41500)
920e4ae3
JK		 2777 /* first exception - 41000Hz reference clock */
2778 chip->ac97_bus->clock = 41000;
29dab4fd 2779 else if (pos > 43600 && pos < 44600)
920e4ae3
JK		 2780 /* second exception - 44100HZ reference clock */
2781 chip->ac97_bus->clock = 44100;
1da177e4
LT		 2782 else if (pos < 47500 || pos > 48500)
2783 /* not 48000Hz, tuning the clock.. */
2784 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2785 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
6dbe6628 2786 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
1da177e4
LT		 2787}
2788
d695e4ea
TI		 2789static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2790 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2791 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2792 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
78fad343 2793 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
d695e4ea
TI		 2794 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2795 { } /* terminator */
2b3b5485
JK		 2796};
2797
2798static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2799{
2800 struct pci_dev *pci = chip->pci;
d695e4ea
TI		 2801 const struct snd_pci_quirk *wl;
2802
2803 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2804 if (!wl)
2805 return 0;
2806 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2807 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2808 chip->ac97_bus->clock = wl->value;
2809 return 1;
2b3b5485
JK		 2810}
2811
adf1b3d2 2812#ifdef CONFIG_PROC_FS
6b75a9d8
TI		 2813static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2814 struct snd_info_buffer *buffer)
1da177e4 2815{
6b75a9d8 2816 struct intel8x0 *chip = entry->private_data;
1da177e4
LT		 2817 unsigned int tmp;
2818
2819 snd_iprintf(buffer, "Intel8x0\n\n");
2820 if (chip->device_type == DEVICE_ALI)
2821 return;
2822 tmp = igetdword(chip, ICHREG(GLOB_STA));
2823 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2824 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2825 if (chip->device_type == DEVICE_INTEL_ICH4)
2826 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
84a43bd5
TI		 2827 snd_iprintf(buffer, "AC'97 codecs ready :");
2828 if (tmp & chip->codec_isr_bits) {
2829 int i;
2830 static const char *codecs[3] = {
2831 "primary", "secondary", "tertiary"
2832 };
2833 for (i = 0; i < chip->max_codecs; i++)
2834 if (tmp & chip->codec_bit[i])
2835 snd_iprintf(buffer, " %s", codecs[i]);
2836 } else
2837 snd_iprintf(buffer, " none");
2838 snd_iprintf(buffer, "\n");
2839 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2840 chip->device_type == DEVICE_SIS)
1da177e4
LT		 2841 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2842 chip->ac97_sdin[0],
2843 chip->ac97_sdin[1],
2844 chip->ac97_sdin[2]);
2845}
2846
6b75a9d8 2847static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
1da177e4 2848{
6b75a9d8 2849 struct snd_info_entry *entry;
1da177e4
LT		 2850
2851 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
bf850204 2852 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
1da177e4 2853}
adf1b3d2
TI		 2854#else
2855#define snd_intel8x0_proc_init(x)
2856#endif
1da177e4 2857
6b75a9d8 2858static int snd_intel8x0_dev_free(struct snd_device *device)
1da177e4 2859{
6b75a9d8 2860 struct intel8x0 *chip = device->device_data;
1da177e4
LT		 2861 return snd_intel8x0_free(chip);
2862}
2863
2864struct ich_reg_info {
2865 unsigned int int_sta_mask;
2866 unsigned int offset;
2867};
2868
84a43bd5
TI		 2869static unsigned int ich_codec_bits[3] = {
2870 ICH_PCR, ICH_SCR, ICH_TCR
2871};
2872static unsigned int sis_codec_bits[3] = {
2873 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2874};
2875
6b75a9d8 2876static int __devinit snd_intel8x0_create(struct snd_card *card,
1da177e4
LT		 2877 struct pci_dev *pci,
2878 unsigned long device_type,
6b75a9d8 2879 struct intel8x0 ** r_intel8x0)
1da177e4 2880{
6b75a9d8 2881 struct intel8x0 *chip;
1da177e4
LT		 2882 int err;
2883 unsigned int i;
2884 unsigned int int_sta_masks;
6b75a9d8
TI		 2885 struct ichdev *ichdev;
2886 static struct snd_device_ops ops = {
1da177e4
LT		 2887 .dev_free = snd_intel8x0_dev_free,
2888 };
2889
2890 static unsigned int bdbars[] = {
2891 3, /* DEVICE_INTEL */
2892 6, /* DEVICE_INTEL_ICH4 */
2893 3, /* DEVICE_SIS */
2894 6, /* DEVICE_ALI */
2895 4, /* DEVICE_NFORCE */
2896 };
2897 static struct ich_reg_info intel_regs[6] = {
2898 { ICH_PIINT, 0 },
2899 { ICH_POINT, 0x10 },
2900 { ICH_MCINT, 0x20 },
2901 { ICH_M2INT, 0x40 },
2902 { ICH_P2INT, 0x50 },
2903 { ICH_SPINT, 0x60 },
2904 };
2905 static struct ich_reg_info nforce_regs[4] = {
2906 { ICH_PIINT, 0 },
2907 { ICH_POINT, 0x10 },
2908 { ICH_MCINT, 0x20 },
2909 { ICH_NVSPINT, 0x70 },
2910 };
2911 static struct ich_reg_info ali_regs[6] = {
2912 { ALI_INT_PCMIN, 0x40 },
2913 { ALI_INT_PCMOUT, 0x50 },
2914 { ALI_INT_MICIN, 0x60 },
2915 { ALI_INT_CODECSPDIFOUT, 0x70 },
2916 { ALI_INT_SPDIFIN, 0xa0 },
2917 { ALI_INT_SPDIFOUT, 0xb0 },
2918 };
2919 struct ich_reg_info *tbl;
2920
2921 *r_intel8x0 = NULL;
2922
2923 if ((err = pci_enable_device(pci)) < 0)
2924 return err;
2925
e560d8d8 2926 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 2927 if (chip == NULL) {
2928 pci_disable_device(pci);
2929 return -ENOMEM;
2930 }
2931 spin_lock_init(&chip->reg_lock);
2932 chip->device_type = device_type;
2933 chip->card = card;
2934 chip->pci = pci;
2935 chip->irq = -1;
c829b052
TI		 2936
2937 /* module parameters */
2938 chip->buggy_irq = buggy_irq;
2939 chip->buggy_semaphore = buggy_semaphore;
2940 if (xbox)
2941 chip->xbox = 1;
1da177e4
LT		 2942
2943 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2944 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2945 chip->fix_nocache = 1; /* enable workaround */
2946
1da177e4
LT		 2947 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2948 kfree(chip);
2949 pci_disable_device(pci);
2950 return err;
2951 }
2952
2953 if (device_type == DEVICE_ALI) {
2954 /* ALI5455 has no ac97 region */
3388c37e 2955 chip->bmaddr = pci_iomap(pci, 0, 0);
1da177e4
LT		 2956 goto port_inited;
2957 }
2958
3388c37e
TI		 2959 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2960 chip->addr = pci_iomap(pci, 2, 0);
2961 else
2962 chip->addr = pci_iomap(pci, 0, 0);
2963 if (!chip->addr) {
2964 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2965 snd_intel8x0_free(chip);
2966 return -EIO;
2967 }
2968 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2969 chip->bmaddr = pci_iomap(pci, 3, 0);
2970 else
2971 chip->bmaddr = pci_iomap(pci, 1, 0);
2972 if (!chip->bmaddr) {
2973 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2974 snd_intel8x0_free(chip);
2975 return -EIO;
1da177e4
LT		 2976 }
2977
2978 port_inited:
1da177e4
LT		 2979 chip->bdbars_count = bdbars[device_type];
2980
2981 /* initialize offsets */
2982 switch (device_type) {
2983 case DEVICE_NFORCE:
2984 tbl = nforce_regs;
2985 break;
2986 case DEVICE_ALI:
2987 tbl = ali_regs;
2988 break;
2989 default:
2990 tbl = intel_regs;
2991 break;
2992 }
2993 for (i = 0; i < chip->bdbars_count; i++) {
2994 ichdev = &chip->ichd[i];
2995 ichdev->ichd = i;
2996 ichdev->reg_offset = tbl[i].offset;
2997 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2998 if (device_type == DEVICE_SIS) {
2999 /* SiS 7012 swaps the registers */
3000 ichdev->roff_sr = ICH_REG_OFF_PICB;
3001 ichdev->roff_picb = ICH_REG_OFF_SR;
3002 } else {
3003 ichdev->roff_sr = ICH_REG_OFF_SR;
3004 ichdev->roff_picb = ICH_REG_OFF_PICB;
3005 }
3006 if (device_type == DEVICE_ALI)
3007 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3008 /* SIS7012 handles the pcm data in bytes, others are in samples */
3009 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3010 }
3011
3012 /* allocate buffer descriptor lists */
3013 /* the start of each lists must be aligned to 8 bytes */
3014 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3015 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3016 &chip->bdbars) < 0) {
3017 snd_intel8x0_free(chip);
3018 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3019 return -ENOMEM;
3020 }
3021 /* tables must be aligned to 8 bytes here, but the kernel pages
3022 are much bigger, so we don't care (on i386) */
3023 /* workaround for 440MX */
3024 if (chip->fix_nocache)
3025 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3026 int_sta_masks = 0;
3027 for (i = 0; i < chip->bdbars_count; i++) {
3028 ichdev = &chip->ichd[i];
beef08a5
TI		 3029 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3030 (i * ICH_MAX_FRAGS * 2);
3031 ichdev->bdbar_addr = chip->bdbars.addr +
3032 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1da177e4
LT		 3033 int_sta_masks |= ichdev->int_sta_mask;
3034 }
beef08a5
TI		 3035 chip->int_sta_reg = device_type == DEVICE_ALI ?
3036 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
1da177e4
LT		 3037 chip->int_sta_mask = int_sta_masks;
3038
beef08a5 3039 pci_set_master(pci);
beef08a5 3040
84a43bd5
TI		 3041 switch(chip->device_type) {
3042 case DEVICE_INTEL_ICH4:
3043 /* ICH4 can have three codecs */
3044 chip->max_codecs = 3;
3045 chip->codec_bit = ich_codec_bits;
3046 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3047 break;
3048 case DEVICE_SIS:
3049 /* recent SIS7012 can have three codecs */
3050 chip->max_codecs = 3;
3051 chip->codec_bit = sis_codec_bits;
3052 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3053 break;
3054 default:
3055 /* others up to two codecs */
3056 chip->max_codecs = 2;
3057 chip->codec_bit = ich_codec_bits;
3058 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3059 break;
3060 }
3061 for (i = 0; i < chip->max_codecs; i++)
3062 chip->codec_isr_bits |= chip->codec_bit[i];
3063
1da177e4
LT		 3064 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3065 snd_intel8x0_free(chip);
3066 return err;
3067 }
3068
2078f38c
TI		 3069 /* request irq after initializaing int_sta_mask, etc */
3070 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3071 IRQF_SHARED, card->shortname, chip)) {
3072 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3073 snd_intel8x0_free(chip);
3074 return -EBUSY;
3075 }
3076 chip->irq = pci->irq;
3077
1da177e4
LT		 3078 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3079 snd_intel8x0_free(chip);
3080 return err;
3081 }
3082
3083 snd_card_set_dev(card, &pci->dev);
3084
3085 *r_intel8x0 = chip;
3086 return 0;
3087}
3088
3089static struct shortname_table {
3090 unsigned int id;
3091 const char *s;
3092} shortnames[] __devinitdata = {
8cdfd251
TI		 3093 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3094 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3095 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
1da177e4 3096 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
8cdfd251
TI		 3097 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3098 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3099 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
1da177e4
LT		 3100 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3101 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3102 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 3103 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4 3104 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
8cdfd251 3105 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
1da177e4
LT		 3106 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3107 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3108 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3109 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3110 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3111 { 0x003a, "NVidia MCP04" },
3112 { 0x746d, "AMD AMD8111" },
3113 { 0x7445, "AMD AMD768" },
3114 { 0x5455, "ALi M5455" },
3115 { 0, NULL },
3116};
3117
a9e99660
TI		 3118static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3119 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3120 { } /* end */
3121};
3122
3123/* look up white/black list for SPDIF over ac-link */
3124static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3125{
3126 const struct snd_pci_quirk *w;
3127
3128 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3129 if (w) {
3130 if (w->value)
3131 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3132 "AC-Link for %s\n", w->name);
3133 else
3134 snd_printdd(KERN_INFO "intel8x0: Using integrated "
3135 "SPDIF DMA for %s\n", w->name);
3136 return w->value;
3137 }
3138 return 0;
3139}
3140
1da177e4
LT		 3141static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3142 const struct pci_device_id *pci_id)
3143{
6b75a9d8
TI		 3144 struct snd_card *card;
3145 struct intel8x0 *chip;
1da177e4
LT		 3146 int err;
3147 struct shortname_table *name;
3148
e58de7ba
TI		 3149 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3150 if (err < 0)
3151 return err;
1da177e4 3152
a9e99660
TI		 3153 if (spdif_aclink < 0)
3154 spdif_aclink = check_default_spdif_aclink(pci);
3155
3156 strcpy(card->driver, "ICH");
3157 if (!spdif_aclink) {
3158 switch (pci_id->driver_data) {
3159 case DEVICE_NFORCE:
3160 strcpy(card->driver, "NFORCE");
3161 break;
3162 case DEVICE_INTEL_ICH4:
3163 strcpy(card->driver, "ICH4");
3164 }
1da177e4
LT		 3165 }
3166
3167 strcpy(card->shortname, "Intel ICH");
3168 for (name = shortnames; name->id; name++) {
3169 if (pci->device == name->id) {
3170 strcpy(card->shortname, name->s);
3171 break;
3172 }
3173 }
3174
beef08a5
TI		 3175 if (buggy_irq < 0) {
3176 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3177 * Needs to return IRQ_HANDLED for unknown irqs.
3178 */
3179 if (pci_id->driver_data == DEVICE_NFORCE)
3180 buggy_irq = 1;
3181 else
3182 buggy_irq = 0;
3183 }
3184
a06147d2 3185 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
c829b052 3186 &chip)) < 0) {
1da177e4
LT		 3187 snd_card_free(card);
3188 return err;
3189 }
5809c6c4 3190 card->private_data = chip;
1da177e4 3191
b7fe4622 3192 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
1da177e4
LT		 3193 snd_card_free(card);
3194 return err;
3195 }
3196 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3197 snd_card_free(card);
3198 return err;
3199 }
3200
3201 snd_intel8x0_proc_init(chip);
3202
3203 snprintf(card->longname, sizeof(card->longname),
3388c37e
TI		 3204 "%s with %s at irq %i", card->shortname,
3205 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
1da177e4 3206
2b3b5485
JK		 3207 if (ac97_clock == 0 || ac97_clock == 1) {
3208 if (ac97_clock == 0) {
3209 if (intel8x0_in_clock_list(chip) == 0)
3210 intel8x0_measure_ac97_clock(chip);
3211 } else {
3212 intel8x0_measure_ac97_clock(chip);
3213 }
3214 }
1da177e4
LT		 3215
3216 if ((err = snd_card_register(card)) < 0) {
3217 snd_card_free(card);
3218 return err;
3219 }
3220 pci_set_drvdata(pci, card);
1da177e4
LT		 3221 return 0;
3222}
3223
3224static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3225{
3226 snd_card_free(pci_get_drvdata(pci));
3227 pci_set_drvdata(pci, NULL);
3228}
3229
3230static struct pci_driver driver = {
3231 .name = "Intel ICH",
3232 .id_table = snd_intel8x0_ids,
3233 .probe = snd_intel8x0_probe,
3234 .remove = __devexit_p(snd_intel8x0_remove),
5809c6c4
TI		 3235#ifdef CONFIG_PM
3236 .suspend = intel8x0_suspend,
3237 .resume = intel8x0_resume,
3238#endif
1da177e4
LT		 3239};
3240
3241
3242static int __init alsa_card_intel8x0_init(void)
3243{
01d25d46 3244 return pci_register_driver(&driver);
1da177e4
LT		 3245}
3246
3247static void __exit alsa_card_intel8x0_exit(void)
3248{
3249 pci_unregister_driver(&driver);
3250}
3251
3252module_init(alsa_card_intel8x0_init)
3253module_exit(alsa_card_intel8x0_exit)
kernel source for telekom puls (alcatel/mediatek)