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[ALSA] ens1371 - added extra delay for ac97 codec initialization
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / intel8x0.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <linux/moduleparam.h>
37#include <sound/core.h>
38#include <sound/pcm.h>
39#include <sound/ac97_codec.h>
40#include <sound/info.h>
41#include <sound/initval.h>
42/* for 440MX workaround */
43#include <asm/pgtable.h>
44#include <asm/cacheflush.h>
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
c4c8ea94 58 "{Intel,ESB2},"
1da177e4
LT		 59 "{Intel,MX440},"
60 "{SiS,SI7012},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
63 "{AMD,AMD768},"
64 "{AMD,AMD8111},"
65 "{ALI,M5455}}");
66
67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
69static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
70static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
71static char *ac97_quirk[SNDRV_CARDS];
72static int buggy_irq[SNDRV_CARDS];
73static int xbox[SNDRV_CARDS];
74
75#ifdef SUPPORT_MIDI
76static int mpu_port[SNDRV_CARDS]; /* disabled */
77#endif
78
79module_param_array(index, int, NULL, 0444);
80MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
81module_param_array(id, charp, NULL, 0444);
82MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
83module_param_array(enable, bool, NULL, 0444);
84MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
85module_param_array(ac97_clock, int, NULL, 0444);
86MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
87module_param_array(ac97_quirk, charp, NULL, 0444);
88MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
89module_param_array(buggy_irq, bool, NULL, 0444);
90MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
91module_param_array(xbox, bool, NULL, 0444);
92MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
93
94/*
95 * Direct registers
96 */
97
98#ifndef PCI_DEVICE_ID_INTEL_82801
99#define PCI_DEVICE_ID_INTEL_82801 0x2415
100#endif
101#ifndef PCI_DEVICE_ID_INTEL_82901
102#define PCI_DEVICE_ID_INTEL_82901 0x2425
103#endif
104#ifndef PCI_DEVICE_ID_INTEL_82801BA
105#define PCI_DEVICE_ID_INTEL_82801BA 0x2445
106#endif
107#ifndef PCI_DEVICE_ID_INTEL_440MX
108#define PCI_DEVICE_ID_INTEL_440MX 0x7195
109#endif
110#ifndef PCI_DEVICE_ID_INTEL_ICH3
111#define PCI_DEVICE_ID_INTEL_ICH3 0x2485
112#endif
113#ifndef PCI_DEVICE_ID_INTEL_ICH4
114#define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
115#endif
116#ifndef PCI_DEVICE_ID_INTEL_ICH5
117#define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
118#endif
119#ifndef PCI_DEVICE_ID_INTEL_ESB_5
120#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
121#endif
122#ifndef PCI_DEVICE_ID_INTEL_ICH6_18
123#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
124#endif
125#ifndef PCI_DEVICE_ID_INTEL_ICH7_20
126#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
127#endif
3437c5df
JG		 128#ifndef PCI_DEVICE_ID_INTEL_ESB2_14
129#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
c4c8ea94 130#endif
1da177e4
LT		 131#ifndef PCI_DEVICE_ID_SI_7012
132#define PCI_DEVICE_ID_SI_7012 0x7012
133#endif
134#ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
135#define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
136#endif
137#ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
138#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
139#endif
140#ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
141#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
142#endif
143#ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
144#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
145#endif
146#ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
147#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
148#endif
149#ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
150#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
151#endif
152
153enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
154
155#define ICHREG(x) ICH_REG_##x
156
157#define DEFINE_REGSET(name,base) \
158enum { \
159 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
160 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
161 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
162 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
163 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
164 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
165 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
166};
167
168/* busmaster blocks */
169DEFINE_REGSET(OFF, 0); /* offset */
170DEFINE_REGSET(PI, 0x00); /* PCM in */
171DEFINE_REGSET(PO, 0x10); /* PCM out */
172DEFINE_REGSET(MC, 0x20); /* Mic in */
173
174/* ICH4 busmaster blocks */
175DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
176DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
177DEFINE_REGSET(SP, 0x60); /* SPDIF out */
178
179/* values for each busmaster block */
180
181/* LVI */
182#define ICH_REG_LVI_MASK 0x1f
183
184/* SR */
185#define ICH_FIFOE 0x10 /* FIFO error */
186#define ICH_BCIS 0x08 /* buffer completion interrupt status */
187#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
188#define ICH_CELV 0x02 /* current equals last valid */
189#define ICH_DCH 0x01 /* DMA controller halted */
190
191/* PIV */
192#define ICH_REG_PIV_MASK 0x1f /* mask */
193
194/* CR */
195#define ICH_IOCE 0x10 /* interrupt on completion enable */
196#define ICH_FEIE 0x08 /* fifo error interrupt enable */
197#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
198#define ICH_RESETREGS 0x02 /* reset busmaster registers */
199#define ICH_STARTBM 0x01 /* start busmaster operation */
200
201
202/* global block */
203#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
204#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
205#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
206#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
207#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
208#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
209#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
210#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
211#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
212#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
213#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
214#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
215#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
216#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
217#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
218#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
219#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
220#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
221#define ICH_ACLINK 0x00000008 /* AClink shut off */
222#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
223#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
224#define ICH_GIE 0x00000001 /* GPI interrupt enable */
225#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
226#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
227#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
228#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
229#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
230#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
231#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
232#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
233#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
234#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
235#define ICH_MD3 0x00020000 /* modem power down semaphore */
236#define ICH_AD3 0x00010000 /* audio power down semaphore */
237#define ICH_RCS 0x00008000 /* read completion status */
238#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
239#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
240#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
241#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
242#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
243#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
244#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
245#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
246#define ICH_POINT 0x00000040 /* playback interrupt */
247#define ICH_PIINT 0x00000020 /* capture interrupt */
248#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
249#define ICH_MOINT 0x00000004 /* modem playback interrupt */
250#define ICH_MIINT 0x00000002 /* modem capture interrupt */
251#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
252#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
253#define ICH_CAS 0x01 /* codec access semaphore */
254#define ICH_REG_SDM 0x80
255#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
256#define ICH_DI2L_SHIFT 6
257#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
258#define ICH_DI1L_SHIFT 4
259#define ICH_SE 0x00000008 /* steer enable */
260#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
261
262#define ICH_MAX_FRAGS 32 /* max hw frags */
263
264
265/*
266 * registers for Ali5455
267 */
268
269/* ALi 5455 busmaster blocks */
270DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
271DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
272DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
273DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
274DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
275DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
276DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
277DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
278DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
279DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
280DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
281
282enum {
283 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
284 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
285 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
286 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
287 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
288 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
289 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
290 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
291 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
292 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
293 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
294 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
295 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
296 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
297 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
298 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
299 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
300 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
301 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
302 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
303 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
304};
305
306#define ALI_CAS_SEM_BUSY 0x80000000
307#define ALI_CPR_ADDR_SECONDARY 0x100
308#define ALI_CPR_ADDR_READ 0x80
309#define ALI_CSPSR_CODEC_READY 0x08
310#define ALI_CSPSR_READ_OK 0x02
311#define ALI_CSPSR_WRITE_OK 0x01
312
313/* interrupts for the whole chip by interrupt status register finish */
314
315#define ALI_INT_MICIN2 (1<<26)
316#define ALI_INT_PCMIN2 (1<<25)
317#define ALI_INT_I2SIN (1<<24)
318#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
319#define ALI_INT_SPDIFIN (1<<22)
320#define ALI_INT_LFEOUT (1<<21)
321#define ALI_INT_CENTEROUT (1<<20)
322#define ALI_INT_CODECSPDIFOUT (1<<19)
323#define ALI_INT_MICIN (1<<18)
324#define ALI_INT_PCMOUT (1<<17)
325#define ALI_INT_PCMIN (1<<16)
326#define ALI_INT_CPRAIS (1<<7) /* command port available */
327#define ALI_INT_SPRAIS (1<<5) /* status port available */
328#define ALI_INT_GPIO (1<<1)
329#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
330
331#define ICH_ALI_SC_RESET (1<<31) /* master reset */
332#define ICH_ALI_SC_AC97_DBL (1<<30)
333#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
334#define ICH_ALI_SC_IN_BITS (3<<18)
335#define ICH_ALI_SC_OUT_BITS (3<<16)
336#define ICH_ALI_SC_6CH_CFG (3<<14)
337#define ICH_ALI_SC_PCM_4 (1<<8)
338#define ICH_ALI_SC_PCM_6 (2<<8)
339#define ICH_ALI_SC_PCM_246_MASK (3<<8)
340
341#define ICH_ALI_SS_SEC_ID (3<<5)
342#define ICH_ALI_SS_PRI_ID (3<<3)
343
344#define ICH_ALI_IF_AC97SP (1<<21)
345#define ICH_ALI_IF_MC (1<<20)
346#define ICH_ALI_IF_PI (1<<19)
347#define ICH_ALI_IF_MC2 (1<<18)
348#define ICH_ALI_IF_PI2 (1<<17)
349#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
350#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
351#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
352#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
353#define ICH_ALI_IF_PO_SPDF (1<<3)
354#define ICH_ALI_IF_PO (1<<1)
355
356/*
357 *
358 */
359
360enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
361enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
362enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
363
364#define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
365
366typedef struct {
367 unsigned int ichd; /* ich device number */
368 unsigned long reg_offset; /* offset to bmaddr */
369 u32 *bdbar; /* CPU address (32bit) */
370 unsigned int bdbar_addr; /* PCI bus address (32bit) */
371 snd_pcm_substream_t *substream;
372 unsigned int physbuf; /* physical address (32bit) */
373 unsigned int size;
374 unsigned int fragsize;
375 unsigned int fragsize1;
376 unsigned int position;
377 unsigned int pos_shift;
378 int frags;
379 int lvi;
380 int lvi_frag;
381 int civ;
382 int ack;
383 int ack_reload;
384 unsigned int ack_bit;
385 unsigned int roff_sr;
386 unsigned int roff_picb;
387 unsigned int int_sta_mask; /* interrupt status mask */
388 unsigned int ali_slot; /* ALI DMA slot */
389 struct ac97_pcm *pcm;
390 int pcm_open_flag;
391 unsigned int page_attr_changed: 1;
392} ichdev_t;
393
394typedef struct _snd_intel8x0 intel8x0_t;
395
396struct _snd_intel8x0 {
397 unsigned int device_type;
398
399 int irq;
400
401 unsigned int mmio;
402 unsigned long addr;
403 void __iomem *remap_addr;
404 unsigned int bm_mmio;
405 unsigned long bmaddr;
406 void __iomem *remap_bmaddr;
407
408 struct pci_dev *pci;
409 snd_card_t *card;
410
411 int pcm_devs;
412 snd_pcm_t *pcm[6];
413 ichdev_t ichd[6];
414
415 unsigned multi4: 1,
416 multi6: 1,
417 dra: 1,
418 smp20bit: 1;
419 unsigned in_ac97_init: 1,
420 in_sdin_init: 1;
421 unsigned in_measurement: 1; /* during ac97 clock measurement */
422 unsigned fix_nocache: 1; /* workaround for 440MX */
423 unsigned buggy_irq: 1; /* workaround for buggy mobos */
424 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
425
426 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 427 unsigned int sdm_saved; /* SDM reg value */
1da177e4
LT		 428
429 ac97_bus_t *ac97_bus;
430 ac97_t *ac97[3];
431 unsigned int ac97_sdin[3];
432
433 spinlock_t reg_lock;
434
435 u32 bdbars_count;
436 struct snd_dma_buffer bdbars;
437 u32 int_sta_reg; /* interrupt status register */
438 u32 int_sta_mask; /* interrupt status mask */
439};
440
441static struct pci_device_id snd_intel8x0_ids[] = {
442 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
443 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
444 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
445 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
446 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
447 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
448 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
449 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
450 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
c4c8ea94 451 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
1da177e4
LT		 452 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
453 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
454 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
455 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
456 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
457 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
458 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
459 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
460 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
461 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
462 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
463 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
464 { 0, }
465};
466
467MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
468
469/*
470 * Lowlevel I/O - busmaster
471 */
472
473static u8 igetbyte(intel8x0_t *chip, u32 offset)
474{
475 if (chip->bm_mmio)
476 return readb(chip->remap_bmaddr + offset);
477 else
478 return inb(chip->bmaddr + offset);
479}
480
481static u16 igetword(intel8x0_t *chip, u32 offset)
482{
483 if (chip->bm_mmio)
484 return readw(chip->remap_bmaddr + offset);
485 else
486 return inw(chip->bmaddr + offset);
487}
488
489static u32 igetdword(intel8x0_t *chip, u32 offset)
490{
491 if (chip->bm_mmio)
492 return readl(chip->remap_bmaddr + offset);
493 else
494 return inl(chip->bmaddr + offset);
495}
496
497static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
498{
499 if (chip->bm_mmio)
500 writeb(val, chip->remap_bmaddr + offset);
501 else
502 outb(val, chip->bmaddr + offset);
503}
504
505static void iputword(intel8x0_t *chip, u32 offset, u16 val)
506{
507 if (chip->bm_mmio)
508 writew(val, chip->remap_bmaddr + offset);
509 else
510 outw(val, chip->bmaddr + offset);
511}
512
513static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
514{
515 if (chip->bm_mmio)
516 writel(val, chip->remap_bmaddr + offset);
517 else
518 outl(val, chip->bmaddr + offset);
519}
520
521/*
522 * Lowlevel I/O - AC'97 registers
523 */
524
525static u16 iagetword(intel8x0_t *chip, u32 offset)
526{
527 if (chip->mmio)
528 return readw(chip->remap_addr + offset);
529 else
530 return inw(chip->addr + offset);
531}
532
533static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
534{
535 if (chip->mmio)
536 writew(val, chip->remap_addr + offset);
537 else
538 outw(val, chip->addr + offset);
539}
540
541/*
542 * Basic I/O
543 */
544
545/*
546 * access to AC97 codec via normal i/o (for ICH and SIS7012)
547 */
548
549/* return the GLOB_STA bit for the corresponding codec */
550static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
551{
552 static unsigned int codec_bit[3] = {
553 ICH_PCR, ICH_SCR, ICH_TCR
554 };
555 snd_assert(codec < 3, return ICH_PCR);
556 if (chip->device_type == DEVICE_INTEL_ICH4)
557 codec = chip->ac97_sdin[codec];
558 return codec_bit[codec];
559}
560
561static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
562{
563 int time;
564
565 if (codec > 2)
566 return -EIO;
567 if (chip->in_sdin_init) {
568 /* we don't know the ready bit assignment at the moment */
569 /* so we check any */
570 codec = ICH_PCR | ICH_SCR | ICH_TCR;
571 } else {
572 codec = get_ich_codec_bit(chip, codec);
573 }
574
575 /* codec ready ? */
576 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
577 return -EIO;
578
579 /* Anyone holding a semaphore for 1 msec should be shot... */
580 time = 100;
581 do {
582 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
583 return 0;
584 udelay(10);
585 } while (time--);
586
587 /* access to some forbidden (non existant) ac97 registers will not
588 * reset the semaphore. So even if you don't get the semaphore, still
589 * continue the access. We don't need the semaphore anyway. */
590 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
591 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
592 iagetword(chip, 0); /* clear semaphore flag */
593 /* I don't care about the semaphore */
594 return -EBUSY;
595}
596
597static void snd_intel8x0_codec_write(ac97_t *ac97,
598 unsigned short reg,
599 unsigned short val)
600{
601 intel8x0_t *chip = ac97->private_data;
602
603 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
604 if (! chip->in_ac97_init)
605 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
606 }
607 iaputword(chip, reg + ac97->num * 0x80, val);
608}
609
610static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
611 unsigned short reg)
612{
613 intel8x0_t *chip = ac97->private_data;
614 unsigned short res;
615 unsigned int tmp;
616
617 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
618 if (! chip->in_ac97_init)
619 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
620 res = 0xffff;
621 } else {
622 res = iagetword(chip, reg + ac97->num * 0x80);
623 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
624 /* reset RCS and preserve other R/WC bits */
625 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
626 if (! chip->in_ac97_init)
627 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
628 res = 0xffff;
629 }
630 }
631 return res;
632}
633
634static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
635{
636 unsigned int tmp;
637
638 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
639 iagetword(chip, codec * 0x80);
640 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
641 /* reset RCS and preserve other R/WC bits */
642 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
643 }
644 }
645}
646
647/*
648 * access to AC97 for Ali5455
649 */
650static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
651{
652 int count = 0;
653 for (count = 0; count < 0x7f; count++) {
654 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
655 if (val & mask)
656 return 0;
657 }
658 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
659 return -EBUSY;
660}
661
662static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
663{
664 int time = 100;
665 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
666 udelay(1);
667 if (! time)
668 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
669 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
670}
671
672static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
673{
674 intel8x0_t *chip = ac97->private_data;
675 unsigned short data = 0xffff;
676
677 if (snd_intel8x0_ali_codec_semaphore(chip))
678 goto __err;
679 reg |= ALI_CPR_ADDR_READ;
680 if (ac97->num)
681 reg |= ALI_CPR_ADDR_SECONDARY;
682 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
683 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
684 goto __err;
685 data = igetword(chip, ICHREG(ALI_SPR));
686 __err:
687 return data;
688}
689
690static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
691{
692 intel8x0_t *chip = ac97->private_data;
693
694 if (snd_intel8x0_ali_codec_semaphore(chip))
695 return;
696 iputword(chip, ICHREG(ALI_CPR), val);
697 if (ac97->num)
698 reg |= ALI_CPR_ADDR_SECONDARY;
699 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
700 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
701}
702
703
704/*
705 * DMA I/O
706 */
707static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
708{
709 int idx;
710 u32 *bdbar = ichdev->bdbar;
711 unsigned long port = ichdev->reg_offset;
712
713 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
714 if (ichdev->size == ichdev->fragsize) {
715 ichdev->ack_reload = ichdev->ack = 2;
716 ichdev->fragsize1 = ichdev->fragsize >> 1;
717 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
718 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
719 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
720 ichdev->fragsize1 >> ichdev->pos_shift);
721 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
722 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
723 ichdev->fragsize1 >> ichdev->pos_shift);
724 }
725 ichdev->frags = 2;
726 } else {
727 ichdev->ack_reload = ichdev->ack = 1;
728 ichdev->fragsize1 = ichdev->fragsize;
729 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
730 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
731 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
732 ichdev->fragsize >> ichdev->pos_shift);
733 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
734 }
735 ichdev->frags = ichdev->size / ichdev->fragsize;
736 }
737 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
738 ichdev->civ = 0;
739 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
740 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
741 ichdev->position = 0;
742#if 0
743 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
744 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
745#endif
746 /* clear interrupts */
747 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
748}
749
750#ifdef __i386__
751/*
752 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
753 * which aborts PCI busmaster for audio transfer. A workaround is to set
754 * the pages as non-cached. For details, see the errata in
755 * http://www.intel.com/design/chipsets/specupdt/245051.htm
756 */
757static void fill_nocache(void *buf, int size, int nocache)
758{
759 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
760 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
761 global_flush_tlb();
762}
763#else
764#define fill_nocache(buf,size,nocache)
765#endif
766
767/*
768 * Interrupt handler
769 */
770
771static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
772{
773 unsigned long port = ichdev->reg_offset;
774 int status, civ, i, step;
775 int ack = 0;
776
777 spin_lock(&chip->reg_lock);
778 status = igetbyte(chip, port + ichdev->roff_sr);
779 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
780 if (!(status & ICH_BCIS)) {
781 step = 0;
782 } else if (civ == ichdev->civ) {
783 // snd_printd("civ same %d\n", civ);
784 step = 1;
785 ichdev->civ++;
786 ichdev->civ &= ICH_REG_LVI_MASK;
787 } else {
788 step = civ - ichdev->civ;
789 if (step < 0)
790 step += ICH_REG_LVI_MASK + 1;
791 // if (step != 1)
792 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
793 ichdev->civ = civ;
794 }
795
796 ichdev->position += step * ichdev->fragsize1;
797 if (! chip->in_measurement)
798 ichdev->position %= ichdev->size;
799 ichdev->lvi += step;
800 ichdev->lvi &= ICH_REG_LVI_MASK;
801 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
802 for (i = 0; i < step; i++) {
803 ichdev->lvi_frag++;
804 ichdev->lvi_frag %= ichdev->frags;
805 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
806 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
807 if (--ichdev->ack == 0) {
808 ichdev->ack = ichdev->ack_reload;
809 ack = 1;
810 }
811 }
812 spin_unlock(&chip->reg_lock);
813 if (ack && ichdev->substream) {
814 snd_pcm_period_elapsed(ichdev->substream);
815 }
816 iputbyte(chip, port + ichdev->roff_sr,
817 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
818}
819
820static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
821{
822 intel8x0_t *chip = dev_id;
823 ichdev_t *ichdev;
824 unsigned int status;
825 unsigned int i;
826
827 status = igetdword(chip, chip->int_sta_reg);
828 if (status == 0xffffffff) /* we are not yet resumed */
829 return IRQ_NONE;
830
831 if ((status & chip->int_sta_mask) == 0) {
832 if (status) {
833 /* ack */
834 iputdword(chip, chip->int_sta_reg, status);
835 if (! chip->buggy_irq)
836 status = 0;
837 }
838 return IRQ_RETVAL(status);
839 }
840
841 for (i = 0; i < chip->bdbars_count; i++) {
842 ichdev = &chip->ichd[i];
843 if (status & ichdev->int_sta_mask)
844 snd_intel8x0_update(chip, ichdev);
845 }
846
847 /* ack them */
848 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
849
850 return IRQ_HANDLED;
851}
852
853/*
854 * PCM part
855 */
856
857static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
858{
859 intel8x0_t *chip = snd_pcm_substream_chip(substream);
860 ichdev_t *ichdev = get_ichdev(substream);
861 unsigned char val = 0;
862 unsigned long port = ichdev->reg_offset;
863
864 switch (cmd) {
865 case SNDRV_PCM_TRIGGER_START:
866 case SNDRV_PCM_TRIGGER_RESUME:
867 val = ICH_IOCE | ICH_STARTBM;
868 break;
869 case SNDRV_PCM_TRIGGER_STOP:
870 case SNDRV_PCM_TRIGGER_SUSPEND:
871 val = 0;
872 break;
873 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
874 val = ICH_IOCE;
875 break;
876 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
877 val = ICH_IOCE | ICH_STARTBM;
878 break;
879 default:
880 return -EINVAL;
881 }
882 iputbyte(chip, port + ICH_REG_OFF_CR, val);
883 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
884 /* wait until DMA stopped */
885 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
886 /* reset whole DMA things */
887 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
888 }
889 return 0;
890}
891
892static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
893{
894 intel8x0_t *chip = snd_pcm_substream_chip(substream);
895 ichdev_t *ichdev = get_ichdev(substream);
896 unsigned long port = ichdev->reg_offset;
897 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
898 unsigned int val, fifo;
899
900 val = igetdword(chip, ICHREG(ALI_DMACR));
901 switch (cmd) {
902 case SNDRV_PCM_TRIGGER_START:
903 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
904 case SNDRV_PCM_TRIGGER_RESUME:
905 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
906 /* clear FIFO for synchronization of channels */
907 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
908 fifo &= ~(0xff << (ichdev->ali_slot % 4));
909 fifo |= 0x83 << (ichdev->ali_slot % 4);
910 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
911 }
912 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
913 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
914 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
915 break;
916 case SNDRV_PCM_TRIGGER_STOP:
917 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
918 case SNDRV_PCM_TRIGGER_SUSPEND:
919 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
920 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
921 while (igetbyte(chip, port + ICH_REG_OFF_CR))
922 ;
923 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
924 break;
925 /* reset whole DMA things */
926 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
927 /* clear interrupts */
928 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
929 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
930 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
931 break;
932 default:
933 return -EINVAL;
934 }
935 return 0;
936}
937
938static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
939 snd_pcm_hw_params_t * hw_params)
940{
941 intel8x0_t *chip = snd_pcm_substream_chip(substream);
942 ichdev_t *ichdev = get_ichdev(substream);
943 snd_pcm_runtime_t *runtime = substream->runtime;
944 int dbl = params_rate(hw_params) > 48000;
945 int err;
946
947 if (chip->fix_nocache && ichdev->page_attr_changed) {
948 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
949 ichdev->page_attr_changed = 0;
950 }
951 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
952 if (err < 0)
953 return err;
954 if (chip->fix_nocache) {
955 if (runtime->dma_area && ! ichdev->page_attr_changed) {
956 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
957 ichdev->page_attr_changed = 1;
958 }
959 }
960 if (ichdev->pcm_open_flag) {
961 snd_ac97_pcm_close(ichdev->pcm);
962 ichdev->pcm_open_flag = 0;
963 }
964 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
965 params_channels(hw_params),
966 ichdev->pcm->r[dbl].slots);
967 if (err >= 0) {
968 ichdev->pcm_open_flag = 1;
969 /* Force SPDIF setting */
970 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
971 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
972 }
973 return err;
974}
975
976static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
977{
978 intel8x0_t *chip = snd_pcm_substream_chip(substream);
979 ichdev_t *ichdev = get_ichdev(substream);
980
981 if (ichdev->pcm_open_flag) {
982 snd_ac97_pcm_close(ichdev->pcm);
983 ichdev->pcm_open_flag = 0;
984 }
985 if (chip->fix_nocache && ichdev->page_attr_changed) {
986 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
987 ichdev->page_attr_changed = 0;
988 }
989 return snd_pcm_lib_free_pages(substream);
990}
991
992static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
993 snd_pcm_runtime_t *runtime)
994{
995 unsigned int cnt;
996 int dbl = runtime->rate > 48000;
997 switch (chip->device_type) {
998 case DEVICE_ALI:
999 cnt = igetdword(chip, ICHREG(ALI_SCR));
1000 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1001 if (runtime->channels == 4 || dbl)
1002 cnt |= ICH_ALI_SC_PCM_4;
1003 else if (runtime->channels == 6)
1004 cnt |= ICH_ALI_SC_PCM_6;
1005 iputdword(chip, ICHREG(ALI_SCR), cnt);
1006 break;
1007 case DEVICE_SIS:
1008 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1009 cnt &= ~ICH_SIS_PCM_246_MASK;
1010 if (runtime->channels == 4 || dbl)
1011 cnt |= ICH_SIS_PCM_4;
1012 else if (runtime->channels == 6)
1013 cnt |= ICH_SIS_PCM_6;
1014 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1015 break;
1016 default:
1017 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1018 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1019 if (runtime->channels == 4 || dbl)
1020 cnt |= ICH_PCM_4;
1021 else if (runtime->channels == 6)
1022 cnt |= ICH_PCM_6;
1023 if (chip->device_type == DEVICE_NFORCE) {
1024 /* reset to 2ch once to keep the 6 channel data in alignment,
1025 * to start from Front Left always
1026 */
1027 if (cnt & ICH_PCM_246_MASK) {
1028 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1029 spin_unlock_irq(&chip->reg_lock);
1030 msleep(50); /* grrr... */
1031 spin_lock_irq(&chip->reg_lock);
1032 }
1033 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1034 if (runtime->sample_bits > 16)
1035 cnt |= ICH_PCM_20BIT;
1036 }
1037 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1038 break;
1039 }
1040}
1041
1042static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1043{
1044 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1045 snd_pcm_runtime_t *runtime = substream->runtime;
1046 ichdev_t *ichdev = get_ichdev(substream);
1047
1048 ichdev->physbuf = runtime->dma_addr;
1049 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1050 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1051 spin_lock_irq(&chip->reg_lock);
1052 if (ichdev->ichd == ICHD_PCMOUT) {
1053 snd_intel8x0_setup_pcm_out(chip, runtime);
1054 if (chip->device_type == DEVICE_INTEL_ICH4) {
1055 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1056 }
1057 }
1058 snd_intel8x0_setup_periods(chip, ichdev);
1059 spin_unlock_irq(&chip->reg_lock);
1060 return 0;
1061}
1062
1063static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1064{
1065 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1066 ichdev_t *ichdev = get_ichdev(substream);
1067 size_t ptr1, ptr;
1068 int civ, timeout = 100;
1069 unsigned int position;
1070
1071 spin_lock(&chip->reg_lock);
1072 do {
1073 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1074 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1075 position = ichdev->position;
1076 if (ptr1 == 0) {
1077 udelay(10);
1078 continue;
1079 }
1080 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1081 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1082 break;
1083 } while (timeout--);
1084 ptr1 <<= ichdev->pos_shift;
1085 ptr = ichdev->fragsize1 - ptr1;
1086 ptr += position;
1087 spin_unlock(&chip->reg_lock);
1088 if (ptr >= ichdev->size)
1089 return 0;
1090 return bytes_to_frames(substream->runtime, ptr);
1091}
1092
1093static snd_pcm_hardware_t snd_intel8x0_stream =
1094{
1095 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1096 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1097 SNDRV_PCM_INFO_MMAP_VALID |
1098 SNDRV_PCM_INFO_PAUSE |
1099 SNDRV_PCM_INFO_RESUME),
1100 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1101 .rates = SNDRV_PCM_RATE_48000,
1102 .rate_min = 48000,
1103 .rate_max = 48000,
1104 .channels_min = 2,
1105 .channels_max = 2,
1106 .buffer_bytes_max = 128 * 1024,
1107 .period_bytes_min = 32,
1108 .period_bytes_max = 128 * 1024,
1109 .periods_min = 1,
1110 .periods_max = 1024,
1111 .fifo_size = 0,
1112};
1113
1114static unsigned int channels4[] = {
1115 2, 4,
1116};
1117
1118static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1119 .count = ARRAY_SIZE(channels4),
1120 .list = channels4,
1121 .mask = 0,
1122};
1123
1124static unsigned int channels6[] = {
1125 2, 4, 6,
1126};
1127
1128static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1129 .count = ARRAY_SIZE(channels6),
1130 .list = channels6,
1131 .mask = 0,
1132};
1133
1134static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1135{
1136 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1137 snd_pcm_runtime_t *runtime = substream->runtime;
1138 int err;
1139
1140 ichdev->substream = substream;
1141 runtime->hw = snd_intel8x0_stream;
1142 runtime->hw.rates = ichdev->pcm->rates;
1143 snd_pcm_limit_hw_rates(runtime);
1144 if (chip->device_type == DEVICE_SIS) {
1145 runtime->hw.buffer_bytes_max = 64*1024;
1146 runtime->hw.period_bytes_max = 64*1024;
1147 }
1148 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1149 return err;
1150 runtime->private_data = ichdev;
1151 return 0;
1152}
1153
1154static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1155{
1156 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1157 snd_pcm_runtime_t *runtime = substream->runtime;
1158 int err;
1159
1160 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1161 if (err < 0)
1162 return err;
1163
1164 if (chip->multi6) {
1165 runtime->hw.channels_max = 6;
1166 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1167 } else if (chip->multi4) {
1168 runtime->hw.channels_max = 4;
1169 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1170 }
1171 if (chip->dra) {
1172 snd_ac97_pcm_double_rate_rules(runtime);
1173 }
1174 if (chip->smp20bit) {
1175 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1176 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1177 }
1178 return 0;
1179}
1180
1181static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1182{
1183 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1184
1185 chip->ichd[ICHD_PCMOUT].substream = NULL;
1186 return 0;
1187}
1188
1189static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1190{
1191 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1192
1193 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1194}
1195
1196static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1197{
1198 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1199
1200 chip->ichd[ICHD_PCMIN].substream = NULL;
1201 return 0;
1202}
1203
1204static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1205{
1206 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1207
1208 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1209}
1210
1211static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1212{
1213 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1214
1215 chip->ichd[ICHD_MIC].substream = NULL;
1216 return 0;
1217}
1218
1219static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1220{
1221 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1222
1223 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1224}
1225
1226static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1227{
1228 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1229
1230 chip->ichd[ICHD_MIC2].substream = NULL;
1231 return 0;
1232}
1233
1234static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1235{
1236 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1237
1238 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1239}
1240
1241static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1242{
1243 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1244
1245 chip->ichd[ICHD_PCM2IN].substream = NULL;
1246 return 0;
1247}
1248
1249static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1250{
1251 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1252 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1253
1254 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1255}
1256
1257static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1258{
1259 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1260 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1261
1262 chip->ichd[idx].substream = NULL;
1263 return 0;
1264}
1265
1266static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1267{
1268 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1269 unsigned int val;
1270
1271 spin_lock_irq(&chip->reg_lock);
1272 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1273 val |= ICH_ALI_IF_AC97SP;
1274 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1275 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1276 spin_unlock_irq(&chip->reg_lock);
1277
1278 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1279}
1280
1281static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1282{
1283 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1284 unsigned int val;
1285
1286 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1287 spin_lock_irq(&chip->reg_lock);
1288 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1289 val &= ~ICH_ALI_IF_AC97SP;
1290 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1291 spin_unlock_irq(&chip->reg_lock);
1292
1293 return 0;
1294}
1295
1296static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1297{
1298 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1299
1300 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1301}
1302
1303static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1304{
1305 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1306
1307 chip->ichd[ALID_SPDIFIN].substream = NULL;
1308 return 0;
1309}
1310
1311#if 0 // NYI
1312static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1313{
1314 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1315
1316 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1317}
1318
1319static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1320{
1321 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1322
1323 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1324 return 0;
1325}
1326#endif
1327
1328static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1329 .open = snd_intel8x0_playback_open,
1330 .close = snd_intel8x0_playback_close,
1331 .ioctl = snd_pcm_lib_ioctl,
1332 .hw_params = snd_intel8x0_hw_params,
1333 .hw_free = snd_intel8x0_hw_free,
1334 .prepare = snd_intel8x0_pcm_prepare,
1335 .trigger = snd_intel8x0_pcm_trigger,
1336 .pointer = snd_intel8x0_pcm_pointer,
1337};
1338
1339static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1340 .open = snd_intel8x0_capture_open,
1341 .close = snd_intel8x0_capture_close,
1342 .ioctl = snd_pcm_lib_ioctl,
1343 .hw_params = snd_intel8x0_hw_params,
1344 .hw_free = snd_intel8x0_hw_free,
1345 .prepare = snd_intel8x0_pcm_prepare,
1346 .trigger = snd_intel8x0_pcm_trigger,
1347 .pointer = snd_intel8x0_pcm_pointer,
1348};
1349
1350static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1351 .open = snd_intel8x0_mic_open,
1352 .close = snd_intel8x0_mic_close,
1353 .ioctl = snd_pcm_lib_ioctl,
1354 .hw_params = snd_intel8x0_hw_params,
1355 .hw_free = snd_intel8x0_hw_free,
1356 .prepare = snd_intel8x0_pcm_prepare,
1357 .trigger = snd_intel8x0_pcm_trigger,
1358 .pointer = snd_intel8x0_pcm_pointer,
1359};
1360
1361static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1362 .open = snd_intel8x0_mic2_open,
1363 .close = snd_intel8x0_mic2_close,
1364 .ioctl = snd_pcm_lib_ioctl,
1365 .hw_params = snd_intel8x0_hw_params,
1366 .hw_free = snd_intel8x0_hw_free,
1367 .prepare = snd_intel8x0_pcm_prepare,
1368 .trigger = snd_intel8x0_pcm_trigger,
1369 .pointer = snd_intel8x0_pcm_pointer,
1370};
1371
1372static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1373 .open = snd_intel8x0_capture2_open,
1374 .close = snd_intel8x0_capture2_close,
1375 .ioctl = snd_pcm_lib_ioctl,
1376 .hw_params = snd_intel8x0_hw_params,
1377 .hw_free = snd_intel8x0_hw_free,
1378 .prepare = snd_intel8x0_pcm_prepare,
1379 .trigger = snd_intel8x0_pcm_trigger,
1380 .pointer = snd_intel8x0_pcm_pointer,
1381};
1382
1383static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1384 .open = snd_intel8x0_spdif_open,
1385 .close = snd_intel8x0_spdif_close,
1386 .ioctl = snd_pcm_lib_ioctl,
1387 .hw_params = snd_intel8x0_hw_params,
1388 .hw_free = snd_intel8x0_hw_free,
1389 .prepare = snd_intel8x0_pcm_prepare,
1390 .trigger = snd_intel8x0_pcm_trigger,
1391 .pointer = snd_intel8x0_pcm_pointer,
1392};
1393
1394static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1395 .open = snd_intel8x0_playback_open,
1396 .close = snd_intel8x0_playback_close,
1397 .ioctl = snd_pcm_lib_ioctl,
1398 .hw_params = snd_intel8x0_hw_params,
1399 .hw_free = snd_intel8x0_hw_free,
1400 .prepare = snd_intel8x0_pcm_prepare,
1401 .trigger = snd_intel8x0_ali_trigger,
1402 .pointer = snd_intel8x0_pcm_pointer,
1403};
1404
1405static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1406 .open = snd_intel8x0_capture_open,
1407 .close = snd_intel8x0_capture_close,
1408 .ioctl = snd_pcm_lib_ioctl,
1409 .hw_params = snd_intel8x0_hw_params,
1410 .hw_free = snd_intel8x0_hw_free,
1411 .prepare = snd_intel8x0_pcm_prepare,
1412 .trigger = snd_intel8x0_ali_trigger,
1413 .pointer = snd_intel8x0_pcm_pointer,
1414};
1415
1416static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1417 .open = snd_intel8x0_mic_open,
1418 .close = snd_intel8x0_mic_close,
1419 .ioctl = snd_pcm_lib_ioctl,
1420 .hw_params = snd_intel8x0_hw_params,
1421 .hw_free = snd_intel8x0_hw_free,
1422 .prepare = snd_intel8x0_pcm_prepare,
1423 .trigger = snd_intel8x0_ali_trigger,
1424 .pointer = snd_intel8x0_pcm_pointer,
1425};
1426
1427static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1428 .open = snd_intel8x0_ali_ac97spdifout_open,
1429 .close = snd_intel8x0_ali_ac97spdifout_close,
1430 .ioctl = snd_pcm_lib_ioctl,
1431 .hw_params = snd_intel8x0_hw_params,
1432 .hw_free = snd_intel8x0_hw_free,
1433 .prepare = snd_intel8x0_pcm_prepare,
1434 .trigger = snd_intel8x0_ali_trigger,
1435 .pointer = snd_intel8x0_pcm_pointer,
1436};
1437
1438static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1439 .open = snd_intel8x0_ali_spdifin_open,
1440 .close = snd_intel8x0_ali_spdifin_close,
1441 .ioctl = snd_pcm_lib_ioctl,
1442 .hw_params = snd_intel8x0_hw_params,
1443 .hw_free = snd_intel8x0_hw_free,
1444 .prepare = snd_intel8x0_pcm_prepare,
1445 .trigger = snd_intel8x0_pcm_trigger,
1446 .pointer = snd_intel8x0_pcm_pointer,
1447};
1448
1449#if 0 // NYI
1450static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1451 .open = snd_intel8x0_ali_spdifout_open,
1452 .close = snd_intel8x0_ali_spdifout_close,
1453 .ioctl = snd_pcm_lib_ioctl,
1454 .hw_params = snd_intel8x0_hw_params,
1455 .hw_free = snd_intel8x0_hw_free,
1456 .prepare = snd_intel8x0_pcm_prepare,
1457 .trigger = snd_intel8x0_pcm_trigger,
1458 .pointer = snd_intel8x0_pcm_pointer,
1459};
1460#endif // NYI
1461
1462struct ich_pcm_table {
1463 char *suffix;
1464 snd_pcm_ops_t *playback_ops;
1465 snd_pcm_ops_t *capture_ops;
1466 size_t prealloc_size;
1467 size_t prealloc_max_size;
1468 int ac97_idx;
1469};
1470
1471static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1472{
1473 snd_pcm_t *pcm;
1474 int err;
1475 char name[32];
1476
1477 if (rec->suffix)
1478 sprintf(name, "Intel ICH - %s", rec->suffix);
1479 else
1480 strcpy(name, "Intel ICH");
1481 err = snd_pcm_new(chip->card, name, device,
1482 rec->playback_ops ? 1 : 0,
1483 rec->capture_ops ? 1 : 0, &pcm);
1484 if (err < 0)
1485 return err;
1486
1487 if (rec->playback_ops)
1488 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1489 if (rec->capture_ops)
1490 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1491
1492 pcm->private_data = chip;
1493 pcm->info_flags = 0;
1494 if (rec->suffix)
1495 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1496 else
1497 strcpy(pcm->name, chip->card->shortname);
1498 chip->pcm[device] = pcm;
1499
1500 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1501 rec->prealloc_size, rec->prealloc_max_size);
1502
1503 return 0;
1504}
1505
1506static struct ich_pcm_table intel_pcms[] __devinitdata = {
1507 {
1508 .playback_ops = &snd_intel8x0_playback_ops,
1509 .capture_ops = &snd_intel8x0_capture_ops,
1510 .prealloc_size = 64 * 1024,
1511 .prealloc_max_size = 128 * 1024,
1512 },
1513 {
1514 .suffix = "MIC ADC",
1515 .capture_ops = &snd_intel8x0_capture_mic_ops,
1516 .prealloc_size = 0,
1517 .prealloc_max_size = 128 * 1024,
1518 .ac97_idx = ICHD_MIC,
1519 },
1520 {
1521 .suffix = "MIC2 ADC",
1522 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1523 .prealloc_size = 0,
1524 .prealloc_max_size = 128 * 1024,
1525 .ac97_idx = ICHD_MIC2,
1526 },
1527 {
1528 .suffix = "ADC2",
1529 .capture_ops = &snd_intel8x0_capture2_ops,
1530 .prealloc_size = 0,
1531 .prealloc_max_size = 128 * 1024,
1532 .ac97_idx = ICHD_PCM2IN,
1533 },
1534 {
1535 .suffix = "IEC958",
1536 .playback_ops = &snd_intel8x0_spdif_ops,
1537 .prealloc_size = 64 * 1024,
1538 .prealloc_max_size = 128 * 1024,
1539 .ac97_idx = ICHD_SPBAR,
1540 },
1541};
1542
1543static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1544 {
1545 .playback_ops = &snd_intel8x0_playback_ops,
1546 .capture_ops = &snd_intel8x0_capture_ops,
1547 .prealloc_size = 64 * 1024,
1548 .prealloc_max_size = 128 * 1024,
1549 },
1550 {
1551 .suffix = "MIC ADC",
1552 .capture_ops = &snd_intel8x0_capture_mic_ops,
1553 .prealloc_size = 0,
1554 .prealloc_max_size = 128 * 1024,
1555 .ac97_idx = NVD_MIC,
1556 },
1557 {
1558 .suffix = "IEC958",
1559 .playback_ops = &snd_intel8x0_spdif_ops,
1560 .prealloc_size = 64 * 1024,
1561 .prealloc_max_size = 128 * 1024,
1562 .ac97_idx = NVD_SPBAR,
1563 },
1564};
1565
1566static struct ich_pcm_table ali_pcms[] __devinitdata = {
1567 {
1568 .playback_ops = &snd_intel8x0_ali_playback_ops,
1569 .capture_ops = &snd_intel8x0_ali_capture_ops,
1570 .prealloc_size = 64 * 1024,
1571 .prealloc_max_size = 128 * 1024,
1572 },
1573 {
1574 .suffix = "MIC ADC",
1575 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1576 .prealloc_size = 0,
1577 .prealloc_max_size = 128 * 1024,
1578 .ac97_idx = ALID_MIC,
1579 },
1580 {
1581 .suffix = "IEC958",
1582 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1583 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1584 .prealloc_size = 64 * 1024,
1585 .prealloc_max_size = 128 * 1024,
1586 .ac97_idx = ALID_AC97SPDIFOUT,
1587 },
1588#if 0 // NYI
1589 {
1590 .suffix = "HW IEC958",
1591 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1592 .prealloc_size = 64 * 1024,
1593 .prealloc_max_size = 128 * 1024,
1594 },
1595#endif
1596};
1597
1598static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1599{
1600 int i, tblsize, device, err;
1601 struct ich_pcm_table *tbl, *rec;
1602
1603 switch (chip->device_type) {
1604 case DEVICE_INTEL_ICH4:
1605 tbl = intel_pcms;
1606 tblsize = ARRAY_SIZE(intel_pcms);
1607 break;
1608 case DEVICE_NFORCE:
1609 tbl = nforce_pcms;
1610 tblsize = ARRAY_SIZE(nforce_pcms);
1611 break;
1612 case DEVICE_ALI:
1613 tbl = ali_pcms;
1614 tblsize = ARRAY_SIZE(ali_pcms);
1615 break;
1616 default:
1617 tbl = intel_pcms;
1618 tblsize = 2;
1619 break;
1620 }
1621
1622 device = 0;
1623 for (i = 0; i < tblsize; i++) {
1624 rec = tbl + i;
1625 if (i > 0 && rec->ac97_idx) {
1626 /* activate PCM only when associated AC'97 codec */
1627 if (! chip->ichd[rec->ac97_idx].pcm)
1628 continue;
1629 }
1630 err = snd_intel8x0_pcm1(chip, device, rec);
1631 if (err < 0)
1632 return err;
1633 device++;
1634 }
1635
1636 chip->pcm_devs = device;
1637 return 0;
1638}
1639
1640
1641/*
1642 * Mixer part
1643 */
1644
1645static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1646{
1647 intel8x0_t *chip = bus->private_data;
1648 chip->ac97_bus = NULL;
1649}
1650
1651static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1652{
1653 intel8x0_t *chip = ac97->private_data;
1654 chip->ac97[ac97->num] = NULL;
1655}
1656
1657static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1658 /* front PCM */
1659 {
1660 .exclusive = 1,
1661 .r = { {
1662 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1663 (1 << AC97_SLOT_PCM_RIGHT) |
1664 (1 << AC97_SLOT_PCM_CENTER) |
1665 (1 << AC97_SLOT_PCM_SLEFT) |
1666 (1 << AC97_SLOT_PCM_SRIGHT) |
1667 (1 << AC97_SLOT_LFE)
1668 },
1669 {
1670 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1671 (1 << AC97_SLOT_PCM_RIGHT) |
1672 (1 << AC97_SLOT_PCM_LEFT_0) |
1673 (1 << AC97_SLOT_PCM_RIGHT_0)
1674 }
1675 }
1676 },
1677 /* PCM IN #1 */
1678 {
1679 .stream = 1,
1680 .exclusive = 1,
1681 .r = { {
1682 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1683 (1 << AC97_SLOT_PCM_RIGHT)
1684 }
1685 }
1686 },
1687 /* MIC IN #1 */
1688 {
1689 .stream = 1,
1690 .exclusive = 1,
1691 .r = { {
1692 .slots = (1 << AC97_SLOT_MIC)
1693 }
1694 }
1695 },
1696 /* S/PDIF PCM */
1697 {
1698 .exclusive = 1,
1699 .spdif = 1,
1700 .r = { {
1701 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1702 (1 << AC97_SLOT_SPDIF_RIGHT2)
1703 }
1704 }
1705 },
1706 /* PCM IN #2 */
1707 {
1708 .stream = 1,
1709 .exclusive = 1,
1710 .r = { {
1711 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1712 (1 << AC97_SLOT_PCM_RIGHT)
1713 }
1714 }
1715 },
1716 /* MIC IN #2 */
1717 {
1718 .stream = 1,
1719 .exclusive = 1,
1720 .r = { {
1721 .slots = (1 << AC97_SLOT_MIC)
1722 }
1723 }
1724 },
1725};
1726
1727static struct ac97_quirk ac97_quirks[] __devinitdata = {
1728 {
6fd8b87f
JCD		 1729 .subvendor = 0x0e11,
1730 .subdevice = 0x008a,
1da177e4
LT		 1731 .name = "Compaq Evo W4000", /* AD1885 */
1732 .type = AC97_TUNE_HP_ONLY
1733 },
1734 {
6fd8b87f
JCD		 1735 .subvendor = 0x0e11,
1736 .subdevice = 0x00b8,
1da177e4
LT		 1737 .name = "Compaq Evo D510C",
1738 .type = AC97_TUNE_HP_ONLY
1739 },
1740 {
6fd8b87f
JCD		 1741 .subvendor = 0x0e11,
1742 .subdevice = 0x0860,
1da177e4
LT		 1743 .name = "HP/Compaq nx7010",
1744 .type = AC97_TUNE_MUTE_LED
1745 },
1746 {
6fd8b87f
JCD		 1747 .subvendor = 0x1014,
1748 .subdevice = 0x1f00,
1da177e4
LT		 1749 .name = "MS-9128",
1750 .type = AC97_TUNE_ALC_JACK
1751 },
1752 {
6fd8b87f
JCD		 1753 .subvendor = 0x1028,
1754 .subdevice = 0x00d8,
1da177e4
LT		 1755 .name = "Dell Precision 530", /* AD1885 */
1756 .type = AC97_TUNE_HP_ONLY
1757 },
1758 {
6fd8b87f
JCD		 1759 .subvendor = 0x1028,
1760 .subdevice = 0x010d,
1da177e4
LT		 1761 .name = "Dell", /* which model? AD1885 */
1762 .type = AC97_TUNE_HP_ONLY
1763 },
1764 {
6fd8b87f
JCD		 1765 .subvendor = 0x1028,
1766 .subdevice = 0x0126,
1da177e4
LT		 1767 .name = "Dell Optiplex GX260", /* AD1981A */
1768 .type = AC97_TUNE_HP_ONLY
1769 },
1770 {
6fd8b87f
JCD		 1771 .subvendor = 0x1028,
1772 .subdevice = 0x012c,
1da177e4
LT		 1773 .name = "Dell Precision 650", /* AD1981A */
1774 .type = AC97_TUNE_HP_ONLY
1775 },
1776 {
6fd8b87f
JCD		 1777 .subvendor = 0x1028,
1778 .subdevice = 0x012d,
1da177e4
LT		 1779 .name = "Dell Precision 450", /* AD1981B*/
1780 .type = AC97_TUNE_HP_ONLY
1781 },
1782 {
6fd8b87f
JCD		 1783 .subvendor = 0x1028,
1784 .subdevice = 0x0147,
1da177e4
LT		 1785 .name = "Dell", /* which model? AD1981B*/
1786 .type = AC97_TUNE_HP_ONLY
1787 },
1788 {
6fd8b87f
JCD		 1789 .subvendor = 0x1028,
1790 .subdevice = 0x0163,
1da177e4
LT		 1791 .name = "Dell Unknown", /* STAC9750/51 */
1792 .type = AC97_TUNE_HP_ONLY
1793 },
1794 {
6fd8b87f
JCD		 1795 .subvendor = 0x103c,
1796 .subdevice = 0x006d,
1da177e4
LT		 1797 .name = "HP zv5000",
1798 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1799 },
1800 { /* FIXME: which codec? */
6fd8b87f
JCD		 1801 .subvendor = 0x103c,
1802 .subdevice = 0x00c3,
1da177e4
LT		 1803 .name = "HP xw6000",
1804 .type = AC97_TUNE_HP_ONLY
1805 },
1806 {
6fd8b87f
JCD		 1807 .subvendor = 0x103c,
1808 .subdevice = 0x088c,
1da177e4
LT		 1809 .name = "HP nc8000",
1810 .type = AC97_TUNE_MUTE_LED
1811 },
1812 {
6fd8b87f
JCD		 1813 .subvendor = 0x103c,
1814 .subdevice = 0x0890,
1da177e4
LT		 1815 .name = "HP nc6000",
1816 .type = AC97_TUNE_MUTE_LED
1817 },
1818 {
6fd8b87f
JCD		 1819 .subvendor = 0x103c,
1820 .subdevice = 0x129d,
1da177e4
LT		 1821 .name = "HP xw8000",
1822 .type = AC97_TUNE_HP_ONLY
1823 },
1824 {
6fd8b87f
JCD		 1825 .subvendor = 0x103c,
1826 .subdevice = 0x12f1,
1da177e4
LT		 1827 .name = "HP xw8200", /* AD1981B*/
1828 .type = AC97_TUNE_HP_ONLY
1829 },
1830 {
6fd8b87f
JCD		 1831 .subvendor = 0x103c,
1832 .subdevice = 0x12f2,
1da177e4
LT		 1833 .name = "HP xw6200",
1834 .type = AC97_TUNE_HP_ONLY
1835 },
1836 {
6fd8b87f
JCD		 1837 .subvendor = 0x103c,
1838 .subdevice = 0x3008,
1da177e4
LT		 1839 .name = "HP xw4200", /* AD1981B*/
1840 .type = AC97_TUNE_HP_ONLY
1841 },
1842 {
6fd8b87f
JCD		 1843 .subvendor = 0x104d,
1844 .subdevice = 0x8197,
1da177e4
LT		 1845 .name = "Sony S1XP",
1846 .type = AC97_TUNE_INV_EAPD
1847 },
1848 {
6fd8b87f
JCD		 1849 .subvendor = 0x1043,
1850 .subdevice = 0x80f3,
1da177e4
LT		 1851 .name = "ASUS ICH5/AD1985",
1852 .type = AC97_TUNE_AD_SHARING
1853 },
1854 {
6fd8b87f
JCD		 1855 .subvendor = 0x10cf,
1856 .subdevice = 0x11c3,
1da177e4
LT		 1857 .name = "Fujitsu-Siemens E4010",
1858 .type = AC97_TUNE_HP_ONLY
1859 },
98c7f212
TI		 1860 {
1861 .subvendor = 0x10cf,
1862 .subdevice = 0x1225,
1863 .name = "Fujitsu-Siemens T3010",
1864 .type = AC97_TUNE_HP_ONLY
1865 },
1da177e4 1866 {
6fd8b87f
JCD		 1867 .subvendor = 0x10cf,
1868 .subdevice = 0x1253,
1da177e4
LT		 1869 .name = "Fujitsu S6210", /* STAC9750/51 */
1870 .type = AC97_TUNE_HP_ONLY
1871 },
1872 {
6fd8b87f
JCD		 1873 .subvendor = 0x10f1,
1874 .subdevice = 0x2665,
1da177e4
LT		 1875 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1876 .type = AC97_TUNE_HP_ONLY
1877 },
1878 {
6fd8b87f
JCD		 1879 .subvendor = 0x10f1,
1880 .subdevice = 0x2885,
1da177e4
LT		 1881 .name = "AMD64 Mobo", /* ALC650 */
1882 .type = AC97_TUNE_HP_ONLY
1883 },
1884 {
6fd8b87f
JCD		 1885 .subvendor = 0x110a,
1886 .subdevice = 0x0056,
1da177e4
LT		 1887 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1888 .type = AC97_TUNE_HP_ONLY
1889 },
1890 {
6fd8b87f
JCD		 1891 .subvendor = 0x11d4,
1892 .subdevice = 0x5375,
1da177e4
LT		 1893 .name = "ADI AD1985 (discrete)",
1894 .type = AC97_TUNE_HP_ONLY
1895 },
1896 {
6fd8b87f
JCD		 1897 .subvendor = 0x1462,
1898 .subdevice = 0x5470,
1da177e4
LT		 1899 .name = "MSI P4 ATX 645 Ultra",
1900 .type = AC97_TUNE_HP_ONLY
1901 },
1902 {
6fd8b87f
JCD		 1903 .subvendor = 0x1734,
1904 .subdevice = 0x0088,
1da177e4
LT		 1905 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1906 .type = AC97_TUNE_HP_ONLY
1907 },
1908 {
6fd8b87f
JCD		 1909 .subvendor = 0x8086,
1910 .subdevice = 0x2000,
1da177e4
LT		 1911 .mask = 0xfff0,
1912 .name = "Intel ICH5/AD1985",
1913 .type = AC97_TUNE_AD_SHARING
1914 },
1915 {
6fd8b87f
JCD		 1916 .subvendor = 0x8086,
1917 .subdevice = 0x4000,
1da177e4
LT		 1918 .mask = 0xfff0,
1919 .name = "Intel ICH5/AD1985",
1920 .type = AC97_TUNE_AD_SHARING
1921 },
1922 {
6fd8b87f
JCD		 1923 .subvendor = 0x8086,
1924 .subdevice = 0x4856,
1da177e4
LT		 1925 .name = "Intel D845WN (82801BA)",
1926 .type = AC97_TUNE_SWAP_HP
1927 },
1928 {
6fd8b87f
JCD		 1929 .subvendor = 0x8086,
1930 .subdevice = 0x4d44,
1da177e4
LT		 1931 .name = "Intel D850EMV2", /* AD1885 */
1932 .type = AC97_TUNE_HP_ONLY
1933 },
1934 {
6fd8b87f
JCD		 1935 .subvendor = 0x8086,
1936 .subdevice = 0x4d56,
1da177e4
LT		 1937 .name = "Intel ICH/AD1885",
1938 .type = AC97_TUNE_HP_ONLY
1939 },
1940 {
6fd8b87f
JCD		 1941 .subvendor = 0x8086,
1942 .subdevice = 0x6000,
1da177e4
LT		 1943 .mask = 0xfff0,
1944 .name = "Intel ICH5/AD1985",
1945 .type = AC97_TUNE_AD_SHARING
1946 },
1947 {
6fd8b87f
JCD		 1948 .subvendor = 0x8086,
1949 .subdevice = 0xe000,
1da177e4
LT		 1950 .mask = 0xfff0,
1951 .name = "Intel ICH5/AD1985",
1952 .type = AC97_TUNE_AD_SHARING
1953 },
1954#if 0 /* FIXME: this seems wrong on most boards */
1955 {
6fd8b87f
JCD		 1956 .subvendor = 0x8086,
1957 .subdevice = 0xa000,
1da177e4
LT		 1958 .mask = 0xfff0,
1959 .name = "Intel ICH5/AD1985",
1960 .type = AC97_TUNE_HP_ONLY
1961 },
1962#endif
1963 { } /* terminator */
1964};
1965
1966static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
1967{
1968 ac97_bus_t *pbus;
1969 ac97_template_t ac97;
1970 int err;
1971 unsigned int i, codecs;
1972 unsigned int glob_sta = 0;
1973 ac97_bus_ops_t *ops;
1974 static ac97_bus_ops_t standard_bus_ops = {
1975 .write = snd_intel8x0_codec_write,
1976 .read = snd_intel8x0_codec_read,
1977 };
1978 static ac97_bus_ops_t ali_bus_ops = {
1979 .write = snd_intel8x0_ali_codec_write,
1980 .read = snd_intel8x0_ali_codec_read,
1981 };
1982
1983 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
1984 switch (chip->device_type) {
1985 case DEVICE_NFORCE:
1986 chip->spdif_idx = NVD_SPBAR;
1987 break;
1988 case DEVICE_ALI:
1989 chip->spdif_idx = ALID_AC97SPDIFOUT;
1990 break;
1991 case DEVICE_INTEL_ICH4:
1992 chip->spdif_idx = ICHD_SPBAR;
1993 break;
1994 };
1995
1996 chip->in_ac97_init = 1;
1997
1998 memset(&ac97, 0, sizeof(ac97));
1999 ac97.private_data = chip;
2000 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2001 ac97.scaps = AC97_SCAP_SKIP_MODEM;
2002 if (chip->xbox)
2003 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2004 if (chip->device_type != DEVICE_ALI) {
2005 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2006 ops = &standard_bus_ops;
2007 if (chip->device_type == DEVICE_INTEL_ICH4) {
2008 codecs = 0;
2009 if (glob_sta & ICH_PCR)
2010 codecs++;
2011 if (glob_sta & ICH_SCR)
2012 codecs++;
2013 if (glob_sta & ICH_TCR)
2014 codecs++;
2015 chip->in_sdin_init = 1;
2016 for (i = 0; i < codecs; i++) {
2017 snd_intel8x0_codec_read_test(chip, i);
2018 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2019 }
2020 chip->in_sdin_init = 0;
2021 } else {
2022 codecs = glob_sta & ICH_SCR ? 2 : 1;
2023 }
2024 } else {
2025 ops = &ali_bus_ops;
2026 codecs = 1;
2027 /* detect the secondary codec */
2028 for (i = 0; i < 100; i++) {
2029 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2030 if (reg & 0x40) {
2031 codecs = 2;
2032 break;
2033 }
2034 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2035 udelay(1);
2036 }
2037 }
2038 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2039 goto __err;
2040 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2041 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */
2042 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2043 pbus->clock = ac97_clock;
2044 /* FIXME: my test board doesn't work well with VRA... */
2045 if (chip->device_type == DEVICE_ALI)
2046 pbus->no_vra = 1;
2047 else
2048 pbus->dra = 1;
2049 chip->ac97_bus = pbus;
2050
2051 ac97.pci = chip->pci;
2052 for (i = 0; i < codecs; i++) {
2053 ac97.num = i;
2054 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2055 if (err != -EACCES)
2056 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2057 if (i == 0)
2058 goto __err;
2059 continue;
2060 }
2061 }
2062 /* tune up the primary codec */
2063 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2064 /* enable separate SDINs for ICH4 */
2065 if (chip->device_type == DEVICE_INTEL_ICH4)
2066 pbus->isdin = 1;
2067 /* find the available PCM streams */
2068 i = ARRAY_SIZE(ac97_pcm_defs);
2069 if (chip->device_type != DEVICE_INTEL_ICH4)
2070 i -= 2; /* do not allocate PCM2IN and MIC2 */
2071 if (chip->spdif_idx < 0)
2072 i--; /* do not allocate S/PDIF */
2073 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2074 if (err < 0)
2075 goto __err;
2076 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2077 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2078 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2079 if (chip->spdif_idx >= 0)
2080 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2081 if (chip->device_type == DEVICE_INTEL_ICH4) {
2082 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2083 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2084 }
2085 /* enable separate SDINs for ICH4 */
2086 if (chip->device_type == DEVICE_INTEL_ICH4) {
2087 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2088 u8 tmp = igetbyte(chip, ICHREG(SDM));
2089 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2090 if (pcm) {
2091 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2092 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2093 for (i = 1; i < 4; i++) {
2094 if (pcm->r[0].codec[i]) {
2095 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2096 break;
2097 }
2098 }
2099 } else {
2100 tmp &= ~ICH_SE; /* steer disable */
2101 }
2102 iputbyte(chip, ICHREG(SDM), tmp);
2103 }
2104 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2105 chip->multi4 = 1;
2106 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2107 chip->multi6 = 1;
2108 }
2109 if (pbus->pcms[0].r[1].rslots[0]) {
2110 chip->dra = 1;
2111 }
2112 if (chip->device_type == DEVICE_INTEL_ICH4) {
2113 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2114 chip->smp20bit = 1;
2115 }
2116 if (chip->device_type == DEVICE_NFORCE) {
2117 /* 48kHz only */
2118 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2119 }
2120 if (chip->device_type == DEVICE_INTEL_ICH4) {
2121 /* use slot 10/11 for SPDIF */
2122 u32 val;
2123 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2124 val |= ICH_PCM_SPDIF_1011;
2125 iputdword(chip, ICHREG(GLOB_CNT), val);
2126 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2127 }
2128 chip->in_ac97_init = 0;
2129 return 0;
2130
2131 __err:
2132 /* clear the cold-reset bit for the next chance */
2133 if (chip->device_type != DEVICE_ALI)
2134 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2135 return err;
2136}
2137
2138
2139/*
2140 *
2141 */
2142
2143static void do_ali_reset(intel8x0_t *chip)
2144{
2145 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2146 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2147 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2148 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2149 iputdword(chip, ICHREG(ALI_INTERFACECR),
2150 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2151 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2152 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2153}
2154
2155#define do_delay(chip) do {\
2156 set_current_state(TASK_UNINTERRUPTIBLE);\
2157 schedule_timeout(1);\
2158} while (0)
2159
2160static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2161{
2162 unsigned long end_time;
2163 unsigned int cnt, status, nstatus;
2164
2165 /* put logic to right state */
2166 /* first clear status bits */
2167 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2168 if (chip->device_type == DEVICE_NFORCE)
2169 status |= ICH_NVSPINT;
2170 cnt = igetdword(chip, ICHREG(GLOB_STA));
2171 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2172
2173 /* ACLink on, 2 channels */
2174 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2175 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2176 /* finish cold or do warm reset */
2177 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2178 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2179 end_time = (jiffies + (HZ / 4)) + 1;
2180 do {
2181 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2182 goto __ok;
2183 do_delay(chip);
2184 } while (time_after_eq(end_time, jiffies));
2185 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2186 return -EIO;
2187
2188 __ok:
2189 if (probing) {
2190 /* wait for any codec ready status.
2191 * Once it becomes ready it should remain ready
2192 * as long as we do not disable the ac97 link.
2193 */
2194 end_time = jiffies + HZ;
2195 do {
2196 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2197 if (status)
2198 break;
2199 do_delay(chip);
2200 } while (time_after_eq(end_time, jiffies));
2201 if (! status) {
2202 /* no codec is found */
2203 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2204 return -EIO;
2205 }
2206
2207 if (chip->device_type == DEVICE_INTEL_ICH4)
2208 /* ICH4 can have three codecs */
2209 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2210 else
2211 /* others up to two codecs */
2212 nstatus = ICH_PCR | ICH_SCR;
2213
2214 /* wait for other codecs ready status. */
2215 end_time = jiffies + HZ / 4;
2216 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2217 do_delay(chip);
2218 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2219 }
2220
2221 } else {
2222 /* resume phase */
2223 int i;
2224 status = 0;
2225 for (i = 0; i < 3; i++)
2226 if (chip->ac97[i])
2227 status |= get_ich_codec_bit(chip, i);
2228 /* wait until all the probed codecs are ready */
2229 end_time = jiffies + HZ;
2230 do {
2231 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2232 if (status == nstatus)
2233 break;
2234 do_delay(chip);
2235 } while (time_after_eq(end_time, jiffies));
2236 }
2237
2238 if (chip->device_type == DEVICE_SIS) {
2239 /* unmute the output on SIS7012 */
2240 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2241 }
2242 if (chip->device_type == DEVICE_NFORCE) {
2243 /* enable SPDIF interrupt */
2244 unsigned int val;
2245 pci_read_config_dword(chip->pci, 0x4c, &val);
2246 val |= 0x1000000;
2247 pci_write_config_dword(chip->pci, 0x4c, val);
2248 }
2249 return 0;
2250}
2251
2252static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2253{
2254 u32 reg;
2255 int i = 0;
2256
2257 reg = igetdword(chip, ICHREG(ALI_SCR));
2258 if ((reg & 2) == 0) /* Cold required */
2259 reg |= 2;
2260 else
2261 reg |= 1; /* Warm */
2262 reg &= ~0x80000000; /* ACLink on */
2263 iputdword(chip, ICHREG(ALI_SCR), reg);
2264
2265 for (i = 0; i < HZ / 2; i++) {
2266 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2267 goto __ok;
2268 do_delay(chip);
2269 }
2270 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2271 if (probing)
2272 return -EIO;
2273
2274 __ok:
2275 for (i = 0; i < HZ / 2; i++) {
2276 reg = igetdword(chip, ICHREG(ALI_RTSR));
2277 if (reg & 0x80) /* primary codec */
2278 break;
2279 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2280 do_delay(chip);
2281 }
2282
2283 do_ali_reset(chip);
2284 return 0;
2285}
2286
2287static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2288{
2289 unsigned int i;
2290 int err;
2291
2292 if (chip->device_type != DEVICE_ALI) {
2293 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2294 return err;
2295 iagetword(chip, 0); /* clear semaphore flag */
2296 } else {
2297 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2298 return err;
2299 }
2300
2301 /* disable interrupts */
2302 for (i = 0; i < chip->bdbars_count; i++)
2303 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2304 /* reset channels */
2305 for (i = 0; i < chip->bdbars_count; i++)
2306 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2307 /* initialize Buffer Descriptor Lists */
2308 for (i = 0; i < chip->bdbars_count; i++)
2309 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2310 return 0;
2311}
2312
2313static int snd_intel8x0_free(intel8x0_t *chip)
2314{
2315 unsigned int i;
2316
2317 if (chip->irq < 0)
2318 goto __hw_end;
2319 /* disable interrupts */
2320 for (i = 0; i < chip->bdbars_count; i++)
2321 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2322 /* reset channels */
2323 for (i = 0; i < chip->bdbars_count; i++)
2324 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2325 if (chip->device_type == DEVICE_NFORCE) {
2326 /* stop the spdif interrupt */
2327 unsigned int val;
2328 pci_read_config_dword(chip->pci, 0x4c, &val);
2329 val &= ~0x1000000;
2330 pci_write_config_dword(chip->pci, 0x4c, val);
2331 }
2332 /* --- */
2333 synchronize_irq(chip->irq);
2334 __hw_end:
2335 if (chip->irq >= 0)
2336 free_irq(chip->irq, (void *)chip);
2337 if (chip->bdbars.area) {
2338 if (chip->fix_nocache)
2339 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2340 snd_dma_free_pages(&chip->bdbars);
2341 }
2342 if (chip->remap_addr)
2343 iounmap(chip->remap_addr);
2344 if (chip->remap_bmaddr)
2345 iounmap(chip->remap_bmaddr);
2346 pci_release_regions(chip->pci);
2347 pci_disable_device(chip->pci);
2348 kfree(chip);
2349 return 0;
2350}
2351
2352#ifdef CONFIG_PM
2353/*
2354 * power management
2355 */
2356static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
2357{
2358 intel8x0_t *chip = card->pm_private_data;
2359 int i;
2360
2361 for (i = 0; i < chip->pcm_devs; i++)
2362 snd_pcm_suspend_all(chip->pcm[i]);
2363 /* clear nocache */
2364 if (chip->fix_nocache) {
2365 for (i = 0; i < chip->bdbars_count; i++) {
2366 ichdev_t *ichdev = &chip->ichd[i];
2367 if (ichdev->substream && ichdev->page_attr_changed) {
2368 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2369 if (runtime->dma_area)
2370 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2371 }
2372 }
2373 }
2374 for (i = 0; i < 3; i++)
2375 if (chip->ac97[i])
2376 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2377 if (chip->device_type == DEVICE_INTEL_ICH4)
2378 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
1da177e4
LT		 2379 pci_disable_device(chip->pci);
2380 return 0;
2381}
2382
2383static int intel8x0_resume(snd_card_t *card)
2384{
2385 intel8x0_t *chip = card->pm_private_data;
2386 int i;
2387
2388 pci_enable_device(chip->pci);
2389 pci_set_master(chip->pci);
2390 snd_intel8x0_chip_init(chip, 0);
2391
52b72388
TI		 2392 /* re-initialize mixer stuff */
2393 if (chip->device_type == DEVICE_INTEL_ICH4) {
2394 /* enable separate SDINs for ICH4 */
2395 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2396 /* use slot 10/11 for SPDIF */
2397 iputdword(chip, ICHREG(GLOB_CNT),
2398 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2399 ICH_PCM_SPDIF_1011);
2400 }
2401
1da177e4
LT		 2402 /* refill nocache */
2403 if (chip->fix_nocache)
2404 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2405
2406 for (i = 0; i < 3; i++)
2407 if (chip->ac97[i])
2408 snd_ac97_resume(chip->ac97[i]);
2409
2410 /* refill nocache */
2411 if (chip->fix_nocache) {
2412 for (i = 0; i < chip->bdbars_count; i++) {
2413 ichdev_t *ichdev = &chip->ichd[i];
2414 if (ichdev->substream && ichdev->page_attr_changed) {
2415 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2416 if (runtime->dma_area)
2417 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2418 }
2419 }
2420 }
2421
2422 return 0;
2423}
2424#endif /* CONFIG_PM */
2425
2426#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2427
2428static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2429{
2430 snd_pcm_substream_t *subs;
2431 ichdev_t *ichdev;
2432 unsigned long port;
2433 unsigned long pos, t;
2434 struct timeval start_time, stop_time;
2435
2436 if (chip->ac97_bus->clock != 48000)
2437 return; /* specified in module option */
2438
2439 subs = chip->pcm[0]->streams[0].substream;
2440 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2441 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2442 return;
2443 }
2444 ichdev = &chip->ichd[ICHD_PCMOUT];
2445 ichdev->physbuf = subs->dma_buffer.addr;
2446 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2447 ichdev->substream = NULL; /* don't process interrupts */
2448
2449 /* set rate */
2450 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2451 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2452 return;
2453 }
2454 snd_intel8x0_setup_periods(chip, ichdev);
2455 port = ichdev->reg_offset;
2456 spin_lock_irq(&chip->reg_lock);
2457 chip->in_measurement = 1;
2458 /* trigger */
2459 if (chip->device_type != DEVICE_ALI)
2460 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2461 else {
2462 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2463 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2464 }
2465 do_gettimeofday(&start_time);
2466 spin_unlock_irq(&chip->reg_lock);
2467 set_current_state(TASK_UNINTERRUPTIBLE);
2468 schedule_timeout(HZ / 20);
2469 spin_lock_irq(&chip->reg_lock);
2470 /* check the position */
2471 pos = ichdev->fragsize1;
2472 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2473 pos += ichdev->position;
2474 chip->in_measurement = 0;
2475 do_gettimeofday(&stop_time);
2476 /* stop */
2477 if (chip->device_type == DEVICE_ALI) {
2478 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2479 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2480 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2481 ;
2482 } else {
2483 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2484 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2485 ;
2486 }
2487 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2488 spin_unlock_irq(&chip->reg_lock);
2489
2490 t = stop_time.tv_sec - start_time.tv_sec;
2491 t *= 1000000;
2492 t += stop_time.tv_usec - start_time.tv_usec;
2493 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2494 if (t == 0) {
2495 snd_printk(KERN_ERR "?? calculation error..\n");
2496 return;
2497 }
2498 pos = (pos / 4) * 1000;
2499 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2500 if (pos < 40000 || pos >= 60000)
2501 /* abnormal value. hw problem? */
2502 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2503 else if (pos < 47500 || pos > 48500)
2504 /* not 48000Hz, tuning the clock.. */
2505 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2506 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2507}
2508
2509static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2510 snd_info_buffer_t * buffer)
2511{
2512 intel8x0_t *chip = entry->private_data;
2513 unsigned int tmp;
2514
2515 snd_iprintf(buffer, "Intel8x0\n\n");
2516 if (chip->device_type == DEVICE_ALI)
2517 return;
2518 tmp = igetdword(chip, ICHREG(GLOB_STA));
2519 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2520 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2521 if (chip->device_type == DEVICE_INTEL_ICH4)
2522 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2523 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2524 tmp & ICH_PCR ? " primary" : "",
2525 tmp & ICH_SCR ? " secondary" : "",
2526 tmp & ICH_TCR ? " tertiary" : "",
2527 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2528 if (chip->device_type == DEVICE_INTEL_ICH4)
2529 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2530 chip->ac97_sdin[0],
2531 chip->ac97_sdin[1],
2532 chip->ac97_sdin[2]);
2533}
2534
2535static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2536{
2537 snd_info_entry_t *entry;
2538
2539 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2540 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2541}
2542
2543static int snd_intel8x0_dev_free(snd_device_t *device)
2544{
2545 intel8x0_t *chip = device->device_data;
2546 return snd_intel8x0_free(chip);
2547}
2548
2549struct ich_reg_info {
2550 unsigned int int_sta_mask;
2551 unsigned int offset;
2552};
2553
2554static int __devinit snd_intel8x0_create(snd_card_t * card,
2555 struct pci_dev *pci,
2556 unsigned long device_type,
2557 intel8x0_t ** r_intel8x0)
2558{
2559 intel8x0_t *chip;
2560 int err;
2561 unsigned int i;
2562 unsigned int int_sta_masks;
2563 ichdev_t *ichdev;
2564 static snd_device_ops_t ops = {
2565 .dev_free = snd_intel8x0_dev_free,
2566 };
2567
2568 static unsigned int bdbars[] = {
2569 3, /* DEVICE_INTEL */
2570 6, /* DEVICE_INTEL_ICH4 */
2571 3, /* DEVICE_SIS */
2572 6, /* DEVICE_ALI */
2573 4, /* DEVICE_NFORCE */
2574 };
2575 static struct ich_reg_info intel_regs[6] = {
2576 { ICH_PIINT, 0 },
2577 { ICH_POINT, 0x10 },
2578 { ICH_MCINT, 0x20 },
2579 { ICH_M2INT, 0x40 },
2580 { ICH_P2INT, 0x50 },
2581 { ICH_SPINT, 0x60 },
2582 };
2583 static struct ich_reg_info nforce_regs[4] = {
2584 { ICH_PIINT, 0 },
2585 { ICH_POINT, 0x10 },
2586 { ICH_MCINT, 0x20 },
2587 { ICH_NVSPINT, 0x70 },
2588 };
2589 static struct ich_reg_info ali_regs[6] = {
2590 { ALI_INT_PCMIN, 0x40 },
2591 { ALI_INT_PCMOUT, 0x50 },
2592 { ALI_INT_MICIN, 0x60 },
2593 { ALI_INT_CODECSPDIFOUT, 0x70 },
2594 { ALI_INT_SPDIFIN, 0xa0 },
2595 { ALI_INT_SPDIFOUT, 0xb0 },
2596 };
2597 struct ich_reg_info *tbl;
2598
2599 *r_intel8x0 = NULL;
2600
2601 if ((err = pci_enable_device(pci)) < 0)
2602 return err;
2603
2604 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2605 if (chip == NULL) {
2606 pci_disable_device(pci);
2607 return -ENOMEM;
2608 }
2609 spin_lock_init(&chip->reg_lock);
2610 chip->device_type = device_type;
2611 chip->card = card;
2612 chip->pci = pci;
2613 chip->irq = -1;
2614
2615 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2616 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2617 chip->fix_nocache = 1; /* enable workaround */
2618
2619 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2620 * Needs to return IRQ_HANDLED for unknown irqs.
2621 */
2622 if (device_type == DEVICE_NFORCE)
2623 chip->buggy_irq = 1;
2624
2625 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2626 kfree(chip);
2627 pci_disable_device(pci);
2628 return err;
2629 }
2630
2631 if (device_type == DEVICE_ALI) {
2632 /* ALI5455 has no ac97 region */
2633 chip->bmaddr = pci_resource_start(pci, 0);
2634 goto port_inited;
2635 }
2636
2637 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2638 chip->mmio = 1;
2639 chip->addr = pci_resource_start(pci, 2);
2640 chip->remap_addr = ioremap_nocache(chip->addr,
2641 pci_resource_len(pci, 2));
2642 if (chip->remap_addr == NULL) {
2643 snd_printk("AC'97 space ioremap problem\n");
2644 snd_intel8x0_free(chip);
2645 return -EIO;
2646 }
2647 } else {
2648 chip->addr = pci_resource_start(pci, 0);
2649 }
2650 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2651 chip->bm_mmio = 1;
2652 chip->bmaddr = pci_resource_start(pci, 3);
2653 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2654 pci_resource_len(pci, 3));
2655 if (chip->remap_bmaddr == NULL) {
2656 snd_printk("Controller space ioremap problem\n");
2657 snd_intel8x0_free(chip);
2658 return -EIO;
2659 }
2660 } else {
2661 chip->bmaddr = pci_resource_start(pci, 1);
2662 }
2663
2664 port_inited:
2665 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2666 snd_printk("unable to grab IRQ %d\n", pci->irq);
2667 snd_intel8x0_free(chip);
2668 return -EBUSY;
2669 }
2670 chip->irq = pci->irq;
2671 pci_set_master(pci);
2672 synchronize_irq(chip->irq);
2673
2674 chip->bdbars_count = bdbars[device_type];
2675
2676 /* initialize offsets */
2677 switch (device_type) {
2678 case DEVICE_NFORCE:
2679 tbl = nforce_regs;
2680 break;
2681 case DEVICE_ALI:
2682 tbl = ali_regs;
2683 break;
2684 default:
2685 tbl = intel_regs;
2686 break;
2687 }
2688 for (i = 0; i < chip->bdbars_count; i++) {
2689 ichdev = &chip->ichd[i];
2690 ichdev->ichd = i;
2691 ichdev->reg_offset = tbl[i].offset;
2692 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2693 if (device_type == DEVICE_SIS) {
2694 /* SiS 7012 swaps the registers */
2695 ichdev->roff_sr = ICH_REG_OFF_PICB;
2696 ichdev->roff_picb = ICH_REG_OFF_SR;
2697 } else {
2698 ichdev->roff_sr = ICH_REG_OFF_SR;
2699 ichdev->roff_picb = ICH_REG_OFF_PICB;
2700 }
2701 if (device_type == DEVICE_ALI)
2702 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2703 /* SIS7012 handles the pcm data in bytes, others are in samples */
2704 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2705 }
2706
2707 /* allocate buffer descriptor lists */
2708 /* the start of each lists must be aligned to 8 bytes */
2709 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2710 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2711 &chip->bdbars) < 0) {
2712 snd_intel8x0_free(chip);
2713 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2714 return -ENOMEM;
2715 }
2716 /* tables must be aligned to 8 bytes here, but the kernel pages
2717 are much bigger, so we don't care (on i386) */
2718 /* workaround for 440MX */
2719 if (chip->fix_nocache)
2720 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2721 int_sta_masks = 0;
2722 for (i = 0; i < chip->bdbars_count; i++) {
2723 ichdev = &chip->ichd[i];
2724 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2725 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2726 int_sta_masks |= ichdev->int_sta_mask;
2727 }
2728 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2729 chip->int_sta_mask = int_sta_masks;
2730
2731 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2732 snd_intel8x0_free(chip);
2733 return err;
2734 }
2735
2736 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2737
2738 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2739 snd_intel8x0_free(chip);
2740 return err;
2741 }
2742
2743 snd_card_set_dev(card, &pci->dev);
2744
2745 *r_intel8x0 = chip;
2746 return 0;
2747}
2748
2749static struct shortname_table {
2750 unsigned int id;
2751 const char *s;
2752} shortnames[] __devinitdata = {
2753 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2754 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2755 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2756 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2757 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2758 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2759 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2760 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2761 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2762 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 2763 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4
LT		 2764 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2765 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2766 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2767 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2768 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2769 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2770 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2771 { 0x003a, "NVidia MCP04" },
2772 { 0x746d, "AMD AMD8111" },
2773 { 0x7445, "AMD AMD768" },
2774 { 0x5455, "ALi M5455" },
2775 { 0, NULL },
2776};
2777
2778static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2779 const struct pci_device_id *pci_id)
2780{
2781 static int dev;
2782 snd_card_t *card;
2783 intel8x0_t *chip;
2784 int err;
2785 struct shortname_table *name;
2786
2787 if (dev >= SNDRV_CARDS)
2788 return -ENODEV;
2789 if (!enable[dev]) {
2790 dev++;
2791 return -ENOENT;
2792 }
2793
2794 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2795 if (card == NULL)
2796 return -ENOMEM;
2797
2798 switch (pci_id->driver_data) {
2799 case DEVICE_NFORCE:
2800 strcpy(card->driver, "NFORCE");
2801 break;
2802 case DEVICE_INTEL_ICH4:
2803 strcpy(card->driver, "ICH4");
2804 break;
2805 default:
2806 strcpy(card->driver, "ICH");
2807 break;
2808 }
2809
2810 strcpy(card->shortname, "Intel ICH");
2811 for (name = shortnames; name->id; name++) {
2812 if (pci->device == name->id) {
2813 strcpy(card->shortname, name->s);
2814 break;
2815 }
2816 }
2817
2818 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2819 snd_card_free(card);
2820 return err;
2821 }
2822 if (buggy_irq[dev])
2823 chip->buggy_irq = 1;
2824 if (xbox[dev])
2825 chip->xbox = 1;
2826
2827 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2828 snd_card_free(card);
2829 return err;
2830 }
2831 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2832 snd_card_free(card);
2833 return err;
2834 }
2835
2836 snd_intel8x0_proc_init(chip);
2837
2838 snprintf(card->longname, sizeof(card->longname),
2839 "%s with %s at %#lx, irq %i", card->shortname,
2840 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2841
2842 if (! ac97_clock[dev])
2843 intel8x0_measure_ac97_clock(chip);
2844
2845 if ((err = snd_card_register(card)) < 0) {
2846 snd_card_free(card);
2847 return err;
2848 }
2849 pci_set_drvdata(pci, card);
2850 dev++;
2851 return 0;
2852}
2853
2854static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2855{
2856 snd_card_free(pci_get_drvdata(pci));
2857 pci_set_drvdata(pci, NULL);
2858}
2859
2860static struct pci_driver driver = {
2861 .name = "Intel ICH",
2862 .id_table = snd_intel8x0_ids,
2863 .probe = snd_intel8x0_probe,
2864 .remove = __devexit_p(snd_intel8x0_remove),
2865 SND_PCI_PM_CALLBACKS
2866};
2867
2868
2869static int __init alsa_card_intel8x0_init(void)
2870{
01d25d46 2871 return pci_register_driver(&driver);
1da177e4
LT		 2872}
2873
2874static void __exit alsa_card_intel8x0_exit(void)
2875{
2876 pci_unregister_driver(&driver);
2877}
2878
2879module_init(alsa_card_intel8x0_init)
2880module_exit(alsa_card_intel8x0_exit)
kernel source for telekom puls (alcatel/mediatek)