Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/kernel/irq/manage.c | |
3 | * | |
a34db9b2 IM |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
5 | * Copyright (C) 2005-2006 Thomas Gleixner | |
1da177e4 LT |
6 | * |
7 | * This file contains driver APIs to the irq subsystem. | |
8 | */ | |
9 | ||
97fd75b7 AM |
10 | #define pr_fmt(fmt) "genirq: " fmt |
11 | ||
1da177e4 | 12 | #include <linux/irq.h> |
3aa551c9 | 13 | #include <linux/kthread.h> |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/random.h> | |
16 | #include <linux/interrupt.h> | |
1aeb272c | 17 | #include <linux/slab.h> |
3aa551c9 | 18 | #include <linux/sched.h> |
8bd75c77 | 19 | #include <linux/sched/rt.h> |
4d1d61a6 | 20 | #include <linux/task_work.h> |
1da177e4 LT |
21 | |
22 | #include "internals.h" | |
23 | ||
8d32a307 TG |
24 | #ifdef CONFIG_IRQ_FORCED_THREADING |
25 | __read_mostly bool force_irqthreads; | |
26 | ||
27 | static int __init setup_forced_irqthreads(char *arg) | |
28 | { | |
29 | force_irqthreads = true; | |
30 | return 0; | |
31 | } | |
32 | early_param("threadirqs", setup_forced_irqthreads); | |
33 | #endif | |
34 | ||
1da177e4 LT |
35 | /** |
36 | * synchronize_irq - wait for pending IRQ handlers (on other CPUs) | |
1e5d5331 | 37 | * @irq: interrupt number to wait for |
1da177e4 LT |
38 | * |
39 | * This function waits for any pending IRQ handlers for this interrupt | |
40 | * to complete before returning. If you use this function while | |
41 | * holding a resource the IRQ handler may need you will deadlock. | |
42 | * | |
43 | * This function may be called - with care - from IRQ context. | |
44 | */ | |
45 | void synchronize_irq(unsigned int irq) | |
46 | { | |
cb5bc832 | 47 | struct irq_desc *desc = irq_to_desc(irq); |
32f4125e | 48 | bool inprogress; |
1da177e4 | 49 | |
7d94f7ca | 50 | if (!desc) |
c2b5a251 MW |
51 | return; |
52 | ||
a98ce5c6 HX |
53 | do { |
54 | unsigned long flags; | |
55 | ||
56 | /* | |
57 | * Wait until we're out of the critical section. This might | |
58 | * give the wrong answer due to the lack of memory barriers. | |
59 | */ | |
32f4125e | 60 | while (irqd_irq_inprogress(&desc->irq_data)) |
a98ce5c6 HX |
61 | cpu_relax(); |
62 | ||
63 | /* Ok, that indicated we're done: double-check carefully. */ | |
239007b8 | 64 | raw_spin_lock_irqsave(&desc->lock, flags); |
32f4125e | 65 | inprogress = irqd_irq_inprogress(&desc->irq_data); |
239007b8 | 66 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
a98ce5c6 HX |
67 | |
68 | /* Oops, that failed? */ | |
32f4125e | 69 | } while (inprogress); |
3aa551c9 TG |
70 | |
71 | /* | |
72 | * We made sure that no hardirq handler is running. Now verify | |
73 | * that no threaded handlers are active. | |
74 | */ | |
75 | wait_event(desc->wait_for_threads, !atomic_read(&desc->threads_active)); | |
1da177e4 | 76 | } |
1da177e4 LT |
77 | EXPORT_SYMBOL(synchronize_irq); |
78 | ||
3aa551c9 TG |
79 | #ifdef CONFIG_SMP |
80 | cpumask_var_t irq_default_affinity; | |
81 | ||
771ee3b0 TG |
82 | /** |
83 | * irq_can_set_affinity - Check if the affinity of a given irq can be set | |
84 | * @irq: Interrupt to check | |
85 | * | |
86 | */ | |
87 | int irq_can_set_affinity(unsigned int irq) | |
88 | { | |
08678b08 | 89 | struct irq_desc *desc = irq_to_desc(irq); |
771ee3b0 | 90 | |
bce43032 TG |
91 | if (!desc || !irqd_can_balance(&desc->irq_data) || |
92 | !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) | |
771ee3b0 TG |
93 | return 0; |
94 | ||
95 | return 1; | |
96 | } | |
97 | ||
591d2fb0 TG |
98 | /** |
99 | * irq_set_thread_affinity - Notify irq threads to adjust affinity | |
100 | * @desc: irq descriptor which has affitnity changed | |
101 | * | |
102 | * We just set IRQTF_AFFINITY and delegate the affinity setting | |
103 | * to the interrupt thread itself. We can not call | |
104 | * set_cpus_allowed_ptr() here as we hold desc->lock and this | |
105 | * code can be called from hard interrupt context. | |
106 | */ | |
107 | void irq_set_thread_affinity(struct irq_desc *desc) | |
3aa551c9 TG |
108 | { |
109 | struct irqaction *action = desc->action; | |
110 | ||
111 | while (action) { | |
112 | if (action->thread) | |
591d2fb0 | 113 | set_bit(IRQTF_AFFINITY, &action->thread_flags); |
3aa551c9 TG |
114 | action = action->next; |
115 | } | |
116 | } | |
117 | ||
1fa46f1f | 118 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
0ef5ca1e | 119 | static inline bool irq_can_move_pcntxt(struct irq_data *data) |
1fa46f1f | 120 | { |
0ef5ca1e | 121 | return irqd_can_move_in_process_context(data); |
1fa46f1f | 122 | } |
0ef5ca1e | 123 | static inline bool irq_move_pending(struct irq_data *data) |
1fa46f1f | 124 | { |
0ef5ca1e | 125 | return irqd_is_setaffinity_pending(data); |
1fa46f1f TG |
126 | } |
127 | static inline void | |
128 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) | |
129 | { | |
130 | cpumask_copy(desc->pending_mask, mask); | |
131 | } | |
132 | static inline void | |
133 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) | |
134 | { | |
135 | cpumask_copy(mask, desc->pending_mask); | |
136 | } | |
137 | #else | |
0ef5ca1e | 138 | static inline bool irq_can_move_pcntxt(struct irq_data *data) { return true; } |
cd22c0e4 | 139 | static inline bool irq_move_pending(struct irq_data *data) { return false; } |
1fa46f1f TG |
140 | static inline void |
141 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) { } | |
142 | static inline void | |
143 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) { } | |
144 | #endif | |
145 | ||
818b0f3b JL |
146 | int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, |
147 | bool force) | |
148 | { | |
149 | struct irq_desc *desc = irq_data_to_desc(data); | |
150 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
151 | int ret; | |
152 | ||
73ce7ddb | 153 | ret = chip->irq_set_affinity(data, mask, force); |
818b0f3b JL |
154 | switch (ret) { |
155 | case IRQ_SET_MASK_OK: | |
156 | cpumask_copy(data->affinity, mask); | |
157 | case IRQ_SET_MASK_OK_NOCOPY: | |
158 | irq_set_thread_affinity(desc); | |
159 | ret = 0; | |
160 | } | |
161 | ||
162 | return ret; | |
163 | } | |
164 | ||
73ce7ddb TG |
165 | int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask, |
166 | bool force) | |
771ee3b0 | 167 | { |
c2d0c555 DD |
168 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
169 | struct irq_desc *desc = irq_data_to_desc(data); | |
1fa46f1f | 170 | int ret = 0; |
771ee3b0 | 171 | |
c2d0c555 | 172 | if (!chip || !chip->irq_set_affinity) |
771ee3b0 TG |
173 | return -EINVAL; |
174 | ||
0ef5ca1e | 175 | if (irq_can_move_pcntxt(data)) { |
73ce7ddb | 176 | ret = irq_do_set_affinity(data, mask, force); |
1fa46f1f | 177 | } else { |
c2d0c555 | 178 | irqd_set_move_pending(data); |
1fa46f1f | 179 | irq_copy_pending(desc, mask); |
57b150cc | 180 | } |
1fa46f1f | 181 | |
cd7eab44 BH |
182 | if (desc->affinity_notify) { |
183 | kref_get(&desc->affinity_notify->kref); | |
184 | schedule_work(&desc->affinity_notify->work); | |
185 | } | |
c2d0c555 DD |
186 | irqd_set(data, IRQD_AFFINITY_SET); |
187 | ||
188 | return ret; | |
189 | } | |
190 | ||
73ce7ddb | 191 | int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force) |
c2d0c555 DD |
192 | { |
193 | struct irq_desc *desc = irq_to_desc(irq); | |
194 | unsigned long flags; | |
195 | int ret; | |
196 | ||
197 | if (!desc) | |
198 | return -EINVAL; | |
199 | ||
200 | raw_spin_lock_irqsave(&desc->lock, flags); | |
73ce7ddb | 201 | ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force); |
239007b8 | 202 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1fa46f1f | 203 | return ret; |
771ee3b0 TG |
204 | } |
205 | ||
e7a297b0 PWJ |
206 | int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m) |
207 | { | |
e7a297b0 | 208 | unsigned long flags; |
31d9d9b6 | 209 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
e7a297b0 PWJ |
210 | |
211 | if (!desc) | |
212 | return -EINVAL; | |
e7a297b0 | 213 | desc->affinity_hint = m; |
02725e74 | 214 | irq_put_desc_unlock(desc, flags); |
e7a297b0 PWJ |
215 | return 0; |
216 | } | |
217 | EXPORT_SYMBOL_GPL(irq_set_affinity_hint); | |
218 | ||
cd7eab44 BH |
219 | static void irq_affinity_notify(struct work_struct *work) |
220 | { | |
221 | struct irq_affinity_notify *notify = | |
222 | container_of(work, struct irq_affinity_notify, work); | |
223 | struct irq_desc *desc = irq_to_desc(notify->irq); | |
224 | cpumask_var_t cpumask; | |
225 | unsigned long flags; | |
226 | ||
1fa46f1f | 227 | if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL)) |
cd7eab44 BH |
228 | goto out; |
229 | ||
230 | raw_spin_lock_irqsave(&desc->lock, flags); | |
0ef5ca1e | 231 | if (irq_move_pending(&desc->irq_data)) |
1fa46f1f | 232 | irq_get_pending(cpumask, desc); |
cd7eab44 | 233 | else |
1fb0ef31 | 234 | cpumask_copy(cpumask, desc->irq_data.affinity); |
cd7eab44 BH |
235 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
236 | ||
237 | notify->notify(notify, cpumask); | |
238 | ||
239 | free_cpumask_var(cpumask); | |
240 | out: | |
241 | kref_put(¬ify->kref, notify->release); | |
242 | } | |
243 | ||
244 | /** | |
245 | * irq_set_affinity_notifier - control notification of IRQ affinity changes | |
246 | * @irq: Interrupt for which to enable/disable notification | |
247 | * @notify: Context for notification, or %NULL to disable | |
248 | * notification. Function pointers must be initialised; | |
249 | * the other fields will be initialised by this function. | |
250 | * | |
251 | * Must be called in process context. Notification may only be enabled | |
252 | * after the IRQ is allocated and must be disabled before the IRQ is | |
253 | * freed using free_irq(). | |
254 | */ | |
255 | int | |
256 | irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify) | |
257 | { | |
258 | struct irq_desc *desc = irq_to_desc(irq); | |
259 | struct irq_affinity_notify *old_notify; | |
260 | unsigned long flags; | |
261 | ||
262 | /* The release function is promised process context */ | |
263 | might_sleep(); | |
264 | ||
265 | if (!desc) | |
266 | return -EINVAL; | |
267 | ||
268 | /* Complete initialisation of *notify */ | |
269 | if (notify) { | |
270 | notify->irq = irq; | |
271 | kref_init(¬ify->kref); | |
272 | INIT_WORK(¬ify->work, irq_affinity_notify); | |
273 | } | |
274 | ||
275 | raw_spin_lock_irqsave(&desc->lock, flags); | |
276 | old_notify = desc->affinity_notify; | |
277 | desc->affinity_notify = notify; | |
278 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
279 | ||
280 | if (old_notify) | |
281 | kref_put(&old_notify->kref, old_notify->release); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | EXPORT_SYMBOL_GPL(irq_set_affinity_notifier); | |
286 | ||
18404756 MK |
287 | #ifndef CONFIG_AUTO_IRQ_AFFINITY |
288 | /* | |
289 | * Generic version of the affinity autoselector. | |
290 | */ | |
3b8249e7 TG |
291 | static int |
292 | setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask) | |
18404756 | 293 | { |
569bda8d | 294 | struct cpumask *set = irq_default_affinity; |
818b0f3b | 295 | int node = desc->irq_data.node; |
569bda8d | 296 | |
b008207c | 297 | /* Excludes PER_CPU and NO_BALANCE interrupts */ |
18404756 MK |
298 | if (!irq_can_set_affinity(irq)) |
299 | return 0; | |
300 | ||
f6d87f4b TG |
301 | /* |
302 | * Preserve an userspace affinity setup, but make sure that | |
303 | * one of the targets is online. | |
304 | */ | |
2bdd1055 | 305 | if (irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) { |
569bda8d TG |
306 | if (cpumask_intersects(desc->irq_data.affinity, |
307 | cpu_online_mask)) | |
308 | set = desc->irq_data.affinity; | |
0c6f8a8b | 309 | else |
2bdd1055 | 310 | irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET); |
f6d87f4b | 311 | } |
18404756 | 312 | |
3b8249e7 | 313 | cpumask_and(mask, cpu_online_mask, set); |
241fc640 PB |
314 | if (node != NUMA_NO_NODE) { |
315 | const struct cpumask *nodemask = cpumask_of_node(node); | |
316 | ||
317 | /* make sure at least one of the cpus in nodemask is online */ | |
318 | if (cpumask_intersects(mask, nodemask)) | |
319 | cpumask_and(mask, mask, nodemask); | |
320 | } | |
818b0f3b | 321 | irq_do_set_affinity(&desc->irq_data, mask, false); |
18404756 MK |
322 | return 0; |
323 | } | |
f6d87f4b | 324 | #else |
3b8249e7 TG |
325 | static inline int |
326 | setup_affinity(unsigned int irq, struct irq_desc *d, struct cpumask *mask) | |
f6d87f4b TG |
327 | { |
328 | return irq_select_affinity(irq); | |
329 | } | |
18404756 MK |
330 | #endif |
331 | ||
f6d87f4b TG |
332 | /* |
333 | * Called when affinity is set via /proc/irq | |
334 | */ | |
3b8249e7 | 335 | int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask) |
f6d87f4b TG |
336 | { |
337 | struct irq_desc *desc = irq_to_desc(irq); | |
338 | unsigned long flags; | |
339 | int ret; | |
340 | ||
239007b8 | 341 | raw_spin_lock_irqsave(&desc->lock, flags); |
3b8249e7 | 342 | ret = setup_affinity(irq, desc, mask); |
239007b8 | 343 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
f6d87f4b TG |
344 | return ret; |
345 | } | |
346 | ||
347 | #else | |
3b8249e7 TG |
348 | static inline int |
349 | setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask) | |
f6d87f4b TG |
350 | { |
351 | return 0; | |
352 | } | |
1da177e4 LT |
353 | #endif |
354 | ||
0a0c5168 RW |
355 | void __disable_irq(struct irq_desc *desc, unsigned int irq, bool suspend) |
356 | { | |
357 | if (suspend) { | |
685fd0b4 | 358 | if (!desc->action || (desc->action->flags & IRQF_NO_SUSPEND)) |
0a0c5168 | 359 | return; |
c531e836 | 360 | desc->istate |= IRQS_SUSPENDED; |
0a0c5168 RW |
361 | } |
362 | ||
3aae994f | 363 | if (!desc->depth++) |
87923470 | 364 | irq_disable(desc); |
0a0c5168 RW |
365 | } |
366 | ||
02725e74 TG |
367 | static int __disable_irq_nosync(unsigned int irq) |
368 | { | |
369 | unsigned long flags; | |
31d9d9b6 | 370 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 TG |
371 | |
372 | if (!desc) | |
373 | return -EINVAL; | |
374 | __disable_irq(desc, irq, false); | |
375 | irq_put_desc_busunlock(desc, flags); | |
376 | return 0; | |
377 | } | |
378 | ||
1da177e4 LT |
379 | /** |
380 | * disable_irq_nosync - disable an irq without waiting | |
381 | * @irq: Interrupt to disable | |
382 | * | |
383 | * Disable the selected interrupt line. Disables and Enables are | |
384 | * nested. | |
385 | * Unlike disable_irq(), this function does not ensure existing | |
386 | * instances of the IRQ handler have completed before returning. | |
387 | * | |
388 | * This function may be called from IRQ context. | |
389 | */ | |
390 | void disable_irq_nosync(unsigned int irq) | |
391 | { | |
02725e74 | 392 | __disable_irq_nosync(irq); |
1da177e4 | 393 | } |
1da177e4 LT |
394 | EXPORT_SYMBOL(disable_irq_nosync); |
395 | ||
396 | /** | |
397 | * disable_irq - disable an irq and wait for completion | |
398 | * @irq: Interrupt to disable | |
399 | * | |
400 | * Disable the selected interrupt line. Enables and Disables are | |
401 | * nested. | |
402 | * This function waits for any pending IRQ handlers for this interrupt | |
403 | * to complete before returning. If you use this function while | |
404 | * holding a resource the IRQ handler may need you will deadlock. | |
405 | * | |
406 | * This function may be called - with care - from IRQ context. | |
407 | */ | |
408 | void disable_irq(unsigned int irq) | |
409 | { | |
02725e74 | 410 | if (!__disable_irq_nosync(irq)) |
1da177e4 LT |
411 | synchronize_irq(irq); |
412 | } | |
1da177e4 LT |
413 | EXPORT_SYMBOL(disable_irq); |
414 | ||
0a0c5168 | 415 | void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume) |
1adb0850 | 416 | { |
dc5f219e | 417 | if (resume) { |
c531e836 | 418 | if (!(desc->istate & IRQS_SUSPENDED)) { |
dc5f219e TG |
419 | if (!desc->action) |
420 | return; | |
421 | if (!(desc->action->flags & IRQF_FORCE_RESUME)) | |
422 | return; | |
423 | /* Pretend that it got disabled ! */ | |
424 | desc->depth++; | |
425 | } | |
c531e836 | 426 | desc->istate &= ~IRQS_SUSPENDED; |
dc5f219e | 427 | } |
0a0c5168 | 428 | |
1adb0850 TG |
429 | switch (desc->depth) { |
430 | case 0: | |
0a0c5168 | 431 | err_out: |
b8c512f6 | 432 | WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", irq); |
1adb0850 TG |
433 | break; |
434 | case 1: { | |
c531e836 | 435 | if (desc->istate & IRQS_SUSPENDED) |
0a0c5168 | 436 | goto err_out; |
1adb0850 | 437 | /* Prevent probing on this irq: */ |
1ccb4e61 | 438 | irq_settings_set_noprobe(desc); |
3aae994f | 439 | irq_enable(desc); |
1adb0850 TG |
440 | check_irq_resend(desc, irq); |
441 | /* fall-through */ | |
442 | } | |
443 | default: | |
444 | desc->depth--; | |
445 | } | |
446 | } | |
447 | ||
1da177e4 LT |
448 | /** |
449 | * enable_irq - enable handling of an irq | |
450 | * @irq: Interrupt to enable | |
451 | * | |
452 | * Undoes the effect of one call to disable_irq(). If this | |
453 | * matches the last disable, processing of interrupts on this | |
454 | * IRQ line is re-enabled. | |
455 | * | |
70aedd24 | 456 | * This function may be called from IRQ context only when |
6b8ff312 | 457 | * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL ! |
1da177e4 LT |
458 | */ |
459 | void enable_irq(unsigned int irq) | |
460 | { | |
1da177e4 | 461 | unsigned long flags; |
31d9d9b6 | 462 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
1da177e4 | 463 | |
7d94f7ca | 464 | if (!desc) |
c2b5a251 | 465 | return; |
50f7c032 TG |
466 | if (WARN(!desc->irq_data.chip, |
467 | KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq)) | |
02725e74 | 468 | goto out; |
2656c366 | 469 | |
0a0c5168 | 470 | __enable_irq(desc, irq, false); |
02725e74 TG |
471 | out: |
472 | irq_put_desc_busunlock(desc, flags); | |
1da177e4 | 473 | } |
1da177e4 LT |
474 | EXPORT_SYMBOL(enable_irq); |
475 | ||
0c5d1eb7 | 476 | static int set_irq_wake_real(unsigned int irq, unsigned int on) |
2db87321 | 477 | { |
08678b08 | 478 | struct irq_desc *desc = irq_to_desc(irq); |
2db87321 UKK |
479 | int ret = -ENXIO; |
480 | ||
60f96b41 SS |
481 | if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE) |
482 | return 0; | |
483 | ||
2f7e99bb TG |
484 | if (desc->irq_data.chip->irq_set_wake) |
485 | ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on); | |
2db87321 UKK |
486 | |
487 | return ret; | |
488 | } | |
489 | ||
ba9a2331 | 490 | /** |
a0cd9ca2 | 491 | * irq_set_irq_wake - control irq power management wakeup |
ba9a2331 TG |
492 | * @irq: interrupt to control |
493 | * @on: enable/disable power management wakeup | |
494 | * | |
15a647eb DB |
495 | * Enable/disable power management wakeup mode, which is |
496 | * disabled by default. Enables and disables must match, | |
497 | * just as they match for non-wakeup mode support. | |
498 | * | |
499 | * Wakeup mode lets this IRQ wake the system from sleep | |
500 | * states like "suspend to RAM". | |
ba9a2331 | 501 | */ |
a0cd9ca2 | 502 | int irq_set_irq_wake(unsigned int irq, unsigned int on) |
ba9a2331 | 503 | { |
ba9a2331 | 504 | unsigned long flags; |
31d9d9b6 | 505 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
2db87321 | 506 | int ret = 0; |
ba9a2331 | 507 | |
13863a66 JJ |
508 | if (!desc) |
509 | return -EINVAL; | |
510 | ||
15a647eb DB |
511 | /* wakeup-capable irqs can be shared between drivers that |
512 | * don't need to have the same sleep mode behaviors. | |
513 | */ | |
15a647eb | 514 | if (on) { |
2db87321 UKK |
515 | if (desc->wake_depth++ == 0) { |
516 | ret = set_irq_wake_real(irq, on); | |
517 | if (ret) | |
518 | desc->wake_depth = 0; | |
519 | else | |
7f94226f | 520 | irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 521 | } |
15a647eb DB |
522 | } else { |
523 | if (desc->wake_depth == 0) { | |
7a2c4770 | 524 | WARN(1, "Unbalanced IRQ %d wake disable\n", irq); |
2db87321 UKK |
525 | } else if (--desc->wake_depth == 0) { |
526 | ret = set_irq_wake_real(irq, on); | |
527 | if (ret) | |
528 | desc->wake_depth = 1; | |
529 | else | |
7f94226f | 530 | irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 531 | } |
15a647eb | 532 | } |
02725e74 | 533 | irq_put_desc_busunlock(desc, flags); |
ba9a2331 TG |
534 | return ret; |
535 | } | |
a0cd9ca2 | 536 | EXPORT_SYMBOL(irq_set_irq_wake); |
ba9a2331 | 537 | |
1da177e4 LT |
538 | /* |
539 | * Internal function that tells the architecture code whether a | |
540 | * particular irq has been exclusively allocated or is available | |
541 | * for driver use. | |
542 | */ | |
543 | int can_request_irq(unsigned int irq, unsigned long irqflags) | |
544 | { | |
cc8c3b78 | 545 | unsigned long flags; |
31d9d9b6 | 546 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
02725e74 | 547 | int canrequest = 0; |
1da177e4 | 548 | |
7d94f7ca YL |
549 | if (!desc) |
550 | return 0; | |
551 | ||
02725e74 | 552 | if (irq_settings_can_request(desc)) { |
3dc8601b BH |
553 | if (!desc->action || |
554 | irqflags & desc->action->flags & IRQF_SHARED) | |
555 | canrequest = 1; | |
02725e74 TG |
556 | } |
557 | irq_put_desc_unlock(desc, flags); | |
558 | return canrequest; | |
1da177e4 LT |
559 | } |
560 | ||
0c5d1eb7 | 561 | int __irq_set_trigger(struct irq_desc *desc, unsigned int irq, |
b2ba2c30 | 562 | unsigned long flags) |
82736f4d | 563 | { |
6b8ff312 | 564 | struct irq_chip *chip = desc->irq_data.chip; |
d4d5e089 | 565 | int ret, unmask = 0; |
82736f4d | 566 | |
b2ba2c30 | 567 | if (!chip || !chip->irq_set_type) { |
82736f4d UKK |
568 | /* |
569 | * IRQF_TRIGGER_* but the PIC does not support multiple | |
570 | * flow-types? | |
571 | */ | |
97fd75b7 | 572 | pr_debug("No set_type function for IRQ %d (%s)\n", irq, |
f5d89470 | 573 | chip ? (chip->name ? : "unknown") : "unknown"); |
82736f4d UKK |
574 | return 0; |
575 | } | |
576 | ||
876dbd4c | 577 | flags &= IRQ_TYPE_SENSE_MASK; |
d4d5e089 TG |
578 | |
579 | if (chip->flags & IRQCHIP_SET_TYPE_MASKED) { | |
32f4125e | 580 | if (!irqd_irq_masked(&desc->irq_data)) |
d4d5e089 | 581 | mask_irq(desc); |
32f4125e | 582 | if (!irqd_irq_disabled(&desc->irq_data)) |
d4d5e089 TG |
583 | unmask = 1; |
584 | } | |
585 | ||
f2b662da | 586 | /* caller masked out all except trigger mode flags */ |
b2ba2c30 | 587 | ret = chip->irq_set_type(&desc->irq_data, flags); |
82736f4d | 588 | |
876dbd4c TG |
589 | switch (ret) { |
590 | case IRQ_SET_MASK_OK: | |
591 | irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK); | |
592 | irqd_set(&desc->irq_data, flags); | |
593 | ||
594 | case IRQ_SET_MASK_OK_NOCOPY: | |
595 | flags = irqd_get_trigger_type(&desc->irq_data); | |
596 | irq_settings_set_trigger_mask(desc, flags); | |
597 | irqd_clear(&desc->irq_data, IRQD_LEVEL); | |
598 | irq_settings_clr_level(desc); | |
599 | if (flags & IRQ_TYPE_LEVEL_MASK) { | |
600 | irq_settings_set_level(desc); | |
601 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
602 | } | |
46732475 | 603 | |
d4d5e089 | 604 | ret = 0; |
8fff39e0 | 605 | break; |
876dbd4c | 606 | default: |
97fd75b7 | 607 | pr_err("Setting trigger mode %lu for irq %u failed (%pF)\n", |
876dbd4c | 608 | flags, irq, chip->irq_set_type); |
0c5d1eb7 | 609 | } |
d4d5e089 TG |
610 | if (unmask) |
611 | unmask_irq(desc); | |
82736f4d UKK |
612 | return ret; |
613 | } | |
614 | ||
293a7a0a TG |
615 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
616 | int irq_set_parent(int irq, int parent_irq) | |
617 | { | |
618 | unsigned long flags; | |
619 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
620 | ||
621 | if (!desc) | |
622 | return -EINVAL; | |
623 | ||
624 | desc->parent_irq = parent_irq; | |
625 | ||
626 | irq_put_desc_unlock(desc, flags); | |
627 | return 0; | |
628 | } | |
629 | #endif | |
630 | ||
b25c340c TG |
631 | /* |
632 | * Default primary interrupt handler for threaded interrupts. Is | |
633 | * assigned as primary handler when request_threaded_irq is called | |
634 | * with handler == NULL. Useful for oneshot interrupts. | |
635 | */ | |
636 | static irqreturn_t irq_default_primary_handler(int irq, void *dev_id) | |
637 | { | |
638 | return IRQ_WAKE_THREAD; | |
639 | } | |
640 | ||
399b5da2 TG |
641 | /* |
642 | * Primary handler for nested threaded interrupts. Should never be | |
643 | * called. | |
644 | */ | |
645 | static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id) | |
646 | { | |
647 | WARN(1, "Primary handler called for nested irq %d\n", irq); | |
648 | return IRQ_NONE; | |
649 | } | |
650 | ||
3aa551c9 TG |
651 | static int irq_wait_for_interrupt(struct irqaction *action) |
652 | { | |
550acb19 IY |
653 | set_current_state(TASK_INTERRUPTIBLE); |
654 | ||
3aa551c9 | 655 | while (!kthread_should_stop()) { |
f48fe81e TG |
656 | |
657 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
658 | &action->thread_flags)) { | |
3aa551c9 TG |
659 | __set_current_state(TASK_RUNNING); |
660 | return 0; | |
f48fe81e TG |
661 | } |
662 | schedule(); | |
550acb19 | 663 | set_current_state(TASK_INTERRUPTIBLE); |
3aa551c9 | 664 | } |
550acb19 | 665 | __set_current_state(TASK_RUNNING); |
3aa551c9 TG |
666 | return -1; |
667 | } | |
668 | ||
b25c340c TG |
669 | /* |
670 | * Oneshot interrupts keep the irq line masked until the threaded | |
671 | * handler finished. unmask if the interrupt has not been disabled and | |
672 | * is marked MASKED. | |
673 | */ | |
b5faba21 | 674 | static void irq_finalize_oneshot(struct irq_desc *desc, |
f3f79e38 | 675 | struct irqaction *action) |
b25c340c | 676 | { |
b5faba21 TG |
677 | if (!(desc->istate & IRQS_ONESHOT)) |
678 | return; | |
0b1adaa0 | 679 | again: |
3876ec9e | 680 | chip_bus_lock(desc); |
239007b8 | 681 | raw_spin_lock_irq(&desc->lock); |
0b1adaa0 TG |
682 | |
683 | /* | |
684 | * Implausible though it may be we need to protect us against | |
685 | * the following scenario: | |
686 | * | |
687 | * The thread is faster done than the hard interrupt handler | |
688 | * on the other CPU. If we unmask the irq line then the | |
689 | * interrupt can come in again and masks the line, leaves due | |
009b4c3b | 690 | * to IRQS_INPROGRESS and the irq line is masked forever. |
b5faba21 TG |
691 | * |
692 | * This also serializes the state of shared oneshot handlers | |
693 | * versus "desc->threads_onehsot |= action->thread_mask;" in | |
694 | * irq_wake_thread(). See the comment there which explains the | |
695 | * serialization. | |
0b1adaa0 | 696 | */ |
32f4125e | 697 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0b1adaa0 | 698 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 699 | chip_bus_sync_unlock(desc); |
0b1adaa0 TG |
700 | cpu_relax(); |
701 | goto again; | |
702 | } | |
703 | ||
b5faba21 TG |
704 | /* |
705 | * Now check again, whether the thread should run. Otherwise | |
706 | * we would clear the threads_oneshot bit of this thread which | |
707 | * was just set. | |
708 | */ | |
f3f79e38 | 709 | if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags)) |
b5faba21 TG |
710 | goto out_unlock; |
711 | ||
712 | desc->threads_oneshot &= ~action->thread_mask; | |
713 | ||
32f4125e TG |
714 | if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && |
715 | irqd_irq_masked(&desc->irq_data)) | |
716 | unmask_irq(desc); | |
717 | ||
b5faba21 | 718 | out_unlock: |
239007b8 | 719 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 720 | chip_bus_sync_unlock(desc); |
b25c340c TG |
721 | } |
722 | ||
61f38261 | 723 | #ifdef CONFIG_SMP |
591d2fb0 | 724 | /* |
d4d5e089 | 725 | * Check whether we need to chasnge the affinity of the interrupt thread. |
591d2fb0 TG |
726 | */ |
727 | static void | |
728 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) | |
729 | { | |
730 | cpumask_var_t mask; | |
04aa530e | 731 | bool valid = true; |
591d2fb0 TG |
732 | |
733 | if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags)) | |
734 | return; | |
735 | ||
736 | /* | |
737 | * In case we are out of memory we set IRQTF_AFFINITY again and | |
738 | * try again next time | |
739 | */ | |
740 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { | |
741 | set_bit(IRQTF_AFFINITY, &action->thread_flags); | |
742 | return; | |
743 | } | |
744 | ||
239007b8 | 745 | raw_spin_lock_irq(&desc->lock); |
04aa530e TG |
746 | /* |
747 | * This code is triggered unconditionally. Check the affinity | |
748 | * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out. | |
749 | */ | |
750 | if (desc->irq_data.affinity) | |
751 | cpumask_copy(mask, desc->irq_data.affinity); | |
752 | else | |
753 | valid = false; | |
239007b8 | 754 | raw_spin_unlock_irq(&desc->lock); |
591d2fb0 | 755 | |
04aa530e TG |
756 | if (valid) |
757 | set_cpus_allowed_ptr(current, mask); | |
591d2fb0 TG |
758 | free_cpumask_var(mask); |
759 | } | |
61f38261 BP |
760 | #else |
761 | static inline void | |
762 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { } | |
763 | #endif | |
591d2fb0 | 764 | |
8d32a307 TG |
765 | /* |
766 | * Interrupts which are not explicitely requested as threaded | |
767 | * interrupts rely on the implicit bh/preempt disable of the hard irq | |
768 | * context. So we need to disable bh here to avoid deadlocks and other | |
769 | * side effects. | |
770 | */ | |
3a43e05f | 771 | static irqreturn_t |
8d32a307 TG |
772 | irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action) |
773 | { | |
3a43e05f SAS |
774 | irqreturn_t ret; |
775 | ||
8d32a307 | 776 | local_bh_disable(); |
3a43e05f | 777 | ret = action->thread_fn(action->irq, action->dev_id); |
f3f79e38 | 778 | irq_finalize_oneshot(desc, action); |
8d32a307 | 779 | local_bh_enable(); |
3a43e05f | 780 | return ret; |
8d32a307 TG |
781 | } |
782 | ||
783 | /* | |
784 | * Interrupts explicitely requested as threaded interupts want to be | |
785 | * preemtible - many of them need to sleep and wait for slow busses to | |
786 | * complete. | |
787 | */ | |
3a43e05f SAS |
788 | static irqreturn_t irq_thread_fn(struct irq_desc *desc, |
789 | struct irqaction *action) | |
8d32a307 | 790 | { |
3a43e05f SAS |
791 | irqreturn_t ret; |
792 | ||
793 | ret = action->thread_fn(action->irq, action->dev_id); | |
f3f79e38 | 794 | irq_finalize_oneshot(desc, action); |
3a43e05f | 795 | return ret; |
8d32a307 TG |
796 | } |
797 | ||
7140ea19 IY |
798 | static void wake_threads_waitq(struct irq_desc *desc) |
799 | { | |
56f1c412 | 800 | if (atomic_dec_and_test(&desc->threads_active)) |
7140ea19 IY |
801 | wake_up(&desc->wait_for_threads); |
802 | } | |
803 | ||
67d12145 | 804 | static void irq_thread_dtor(struct callback_head *unused) |
4d1d61a6 ON |
805 | { |
806 | struct task_struct *tsk = current; | |
807 | struct irq_desc *desc; | |
808 | struct irqaction *action; | |
809 | ||
810 | if (WARN_ON_ONCE(!(current->flags & PF_EXITING))) | |
811 | return; | |
812 | ||
813 | action = kthread_data(tsk); | |
814 | ||
fb21affa | 815 | pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n", |
19af395d | 816 | tsk->comm, tsk->pid, action->irq); |
4d1d61a6 ON |
817 | |
818 | ||
819 | desc = irq_to_desc(action->irq); | |
820 | /* | |
821 | * If IRQTF_RUNTHREAD is set, we need to decrement | |
822 | * desc->threads_active and wake possible waiters. | |
823 | */ | |
824 | if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags)) | |
825 | wake_threads_waitq(desc); | |
826 | ||
827 | /* Prevent a stale desc->threads_oneshot */ | |
828 | irq_finalize_oneshot(desc, action); | |
829 | } | |
830 | ||
3aa551c9 TG |
831 | /* |
832 | * Interrupt handler thread | |
833 | */ | |
834 | static int irq_thread(void *data) | |
835 | { | |
67d12145 | 836 | struct callback_head on_exit_work; |
c9b5f501 | 837 | static const struct sched_param param = { |
fe7de49f KM |
838 | .sched_priority = MAX_USER_RT_PRIO/2, |
839 | }; | |
3aa551c9 TG |
840 | struct irqaction *action = data; |
841 | struct irq_desc *desc = irq_to_desc(action->irq); | |
3a43e05f SAS |
842 | irqreturn_t (*handler_fn)(struct irq_desc *desc, |
843 | struct irqaction *action); | |
3aa551c9 | 844 | |
540b60e2 | 845 | if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD, |
8d32a307 TG |
846 | &action->thread_flags)) |
847 | handler_fn = irq_forced_thread_fn; | |
848 | else | |
849 | handler_fn = irq_thread_fn; | |
850 | ||
3aa551c9 | 851 | sched_setscheduler(current, SCHED_FIFO, ¶m); |
4d1d61a6 | 852 | |
41f9d29f | 853 | init_task_work(&on_exit_work, irq_thread_dtor); |
4d1d61a6 | 854 | task_work_add(current, &on_exit_work, false); |
3aa551c9 | 855 | |
f3de44ed SM |
856 | irq_thread_check_affinity(desc, action); |
857 | ||
3aa551c9 | 858 | while (!irq_wait_for_interrupt(action)) { |
7140ea19 | 859 | irqreturn_t action_ret; |
3aa551c9 | 860 | |
591d2fb0 TG |
861 | irq_thread_check_affinity(desc, action); |
862 | ||
7140ea19 | 863 | action_ret = handler_fn(desc, action); |
72aeabd7 TG |
864 | if (action_ret == IRQ_HANDLED) |
865 | atomic_inc(&desc->threads_handled); | |
3aa551c9 | 866 | |
7140ea19 | 867 | wake_threads_waitq(desc); |
3aa551c9 TG |
868 | } |
869 | ||
7140ea19 IY |
870 | /* |
871 | * This is the regular exit path. __free_irq() is stopping the | |
872 | * thread via kthread_stop() after calling | |
873 | * synchronize_irq(). So neither IRQTF_RUNTHREAD nor the | |
e04268b0 TG |
874 | * oneshot mask bit can be set. We cannot verify that as we |
875 | * cannot touch the oneshot mask at this point anymore as | |
876 | * __setup_irq() might have given out currents thread_mask | |
877 | * again. | |
3aa551c9 | 878 | */ |
4d1d61a6 | 879 | task_work_cancel(current, irq_thread_dtor); |
3aa551c9 TG |
880 | return 0; |
881 | } | |
882 | ||
8d32a307 TG |
883 | static void irq_setup_forced_threading(struct irqaction *new) |
884 | { | |
885 | if (!force_irqthreads) | |
886 | return; | |
887 | if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT)) | |
888 | return; | |
889 | ||
890 | new->flags |= IRQF_ONESHOT; | |
891 | ||
892 | if (!new->thread_fn) { | |
893 | set_bit(IRQTF_FORCED_THREAD, &new->thread_flags); | |
894 | new->thread_fn = new->handler; | |
895 | new->handler = irq_default_primary_handler; | |
896 | } | |
897 | } | |
898 | ||
1da177e4 LT |
899 | /* |
900 | * Internal function to register an irqaction - typically used to | |
901 | * allocate special interrupts that are part of the architecture. | |
902 | */ | |
d3c60047 | 903 | static int |
327ec569 | 904 | __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) |
1da177e4 | 905 | { |
f17c7545 | 906 | struct irqaction *old, **old_ptr; |
b5faba21 | 907 | unsigned long flags, thread_mask = 0; |
3b8249e7 TG |
908 | int ret, nested, shared = 0; |
909 | cpumask_var_t mask; | |
1da177e4 | 910 | |
7d94f7ca | 911 | if (!desc) |
c2b5a251 MW |
912 | return -EINVAL; |
913 | ||
6b8ff312 | 914 | if (desc->irq_data.chip == &no_irq_chip) |
1da177e4 | 915 | return -ENOSYS; |
b6873807 SAS |
916 | if (!try_module_get(desc->owner)) |
917 | return -ENODEV; | |
1da177e4 | 918 | |
3aa551c9 | 919 | /* |
399b5da2 TG |
920 | * Check whether the interrupt nests into another interrupt |
921 | * thread. | |
922 | */ | |
1ccb4e61 | 923 | nested = irq_settings_is_nested_thread(desc); |
399b5da2 | 924 | if (nested) { |
b6873807 SAS |
925 | if (!new->thread_fn) { |
926 | ret = -EINVAL; | |
927 | goto out_mput; | |
928 | } | |
399b5da2 TG |
929 | /* |
930 | * Replace the primary handler which was provided from | |
931 | * the driver for non nested interrupt handling by the | |
932 | * dummy function which warns when called. | |
933 | */ | |
934 | new->handler = irq_nested_primary_handler; | |
8d32a307 | 935 | } else { |
7f1b1244 PM |
936 | if (irq_settings_can_thread(desc)) |
937 | irq_setup_forced_threading(new); | |
399b5da2 TG |
938 | } |
939 | ||
3aa551c9 | 940 | /* |
399b5da2 TG |
941 | * Create a handler thread when a thread function is supplied |
942 | * and the interrupt does not nest into another interrupt | |
943 | * thread. | |
3aa551c9 | 944 | */ |
399b5da2 | 945 | if (new->thread_fn && !nested) { |
3aa551c9 TG |
946 | struct task_struct *t; |
947 | ||
948 | t = kthread_create(irq_thread, new, "irq/%d-%s", irq, | |
949 | new->name); | |
b6873807 SAS |
950 | if (IS_ERR(t)) { |
951 | ret = PTR_ERR(t); | |
952 | goto out_mput; | |
953 | } | |
3aa551c9 TG |
954 | /* |
955 | * We keep the reference to the task struct even if | |
956 | * the thread dies to avoid that the interrupt code | |
957 | * references an already freed task_struct. | |
958 | */ | |
959 | get_task_struct(t); | |
960 | new->thread = t; | |
04aa530e TG |
961 | /* |
962 | * Tell the thread to set its affinity. This is | |
963 | * important for shared interrupt handlers as we do | |
964 | * not invoke setup_affinity() for the secondary | |
965 | * handlers as everything is already set up. Even for | |
966 | * interrupts marked with IRQF_NO_BALANCE this is | |
967 | * correct as we want the thread to move to the cpu(s) | |
968 | * on which the requesting code placed the interrupt. | |
969 | */ | |
970 | set_bit(IRQTF_AFFINITY, &new->thread_flags); | |
3aa551c9 TG |
971 | } |
972 | ||
3b8249e7 TG |
973 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { |
974 | ret = -ENOMEM; | |
975 | goto out_thread; | |
976 | } | |
977 | ||
dc9b229a TG |
978 | /* |
979 | * Drivers are often written to work w/o knowledge about the | |
980 | * underlying irq chip implementation, so a request for a | |
981 | * threaded irq without a primary hard irq context handler | |
982 | * requires the ONESHOT flag to be set. Some irq chips like | |
983 | * MSI based interrupts are per se one shot safe. Check the | |
984 | * chip flags, so we can avoid the unmask dance at the end of | |
985 | * the threaded handler for those. | |
986 | */ | |
987 | if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) | |
988 | new->flags &= ~IRQF_ONESHOT; | |
989 | ||
1da177e4 LT |
990 | /* |
991 | * The following block of code has to be executed atomically | |
992 | */ | |
239007b8 | 993 | raw_spin_lock_irqsave(&desc->lock, flags); |
f17c7545 IM |
994 | old_ptr = &desc->action; |
995 | old = *old_ptr; | |
06fcb0c6 | 996 | if (old) { |
e76de9f8 TG |
997 | /* |
998 | * Can't share interrupts unless both agree to and are | |
999 | * the same type (level, edge, polarity). So both flag | |
3cca53b0 | 1000 | * fields must have IRQF_SHARED set and the bits which |
9d591edd TG |
1001 | * set the trigger type must match. Also all must |
1002 | * agree on ONESHOT. | |
e76de9f8 | 1003 | */ |
3cca53b0 | 1004 | if (!((old->flags & new->flags) & IRQF_SHARED) || |
9d591edd | 1005 | ((old->flags ^ new->flags) & IRQF_TRIGGER_MASK) || |
f5d89470 | 1006 | ((old->flags ^ new->flags) & IRQF_ONESHOT)) |
f5163427 DS |
1007 | goto mismatch; |
1008 | ||
f5163427 | 1009 | /* All handlers must agree on per-cpuness */ |
3cca53b0 TG |
1010 | if ((old->flags & IRQF_PERCPU) != |
1011 | (new->flags & IRQF_PERCPU)) | |
f5163427 | 1012 | goto mismatch; |
1da177e4 LT |
1013 | |
1014 | /* add new interrupt at end of irq queue */ | |
1015 | do { | |
52abb700 TG |
1016 | /* |
1017 | * Or all existing action->thread_mask bits, | |
1018 | * so we can find the next zero bit for this | |
1019 | * new action. | |
1020 | */ | |
b5faba21 | 1021 | thread_mask |= old->thread_mask; |
f17c7545 IM |
1022 | old_ptr = &old->next; |
1023 | old = *old_ptr; | |
1da177e4 LT |
1024 | } while (old); |
1025 | shared = 1; | |
1026 | } | |
1027 | ||
b5faba21 | 1028 | /* |
52abb700 TG |
1029 | * Setup the thread mask for this irqaction for ONESHOT. For |
1030 | * !ONESHOT irqs the thread mask is 0 so we can avoid a | |
1031 | * conditional in irq_wake_thread(). | |
b5faba21 | 1032 | */ |
52abb700 TG |
1033 | if (new->flags & IRQF_ONESHOT) { |
1034 | /* | |
1035 | * Unlikely to have 32 resp 64 irqs sharing one line, | |
1036 | * but who knows. | |
1037 | */ | |
1038 | if (thread_mask == ~0UL) { | |
1039 | ret = -EBUSY; | |
1040 | goto out_mask; | |
1041 | } | |
1042 | /* | |
1043 | * The thread_mask for the action is or'ed to | |
1044 | * desc->thread_active to indicate that the | |
1045 | * IRQF_ONESHOT thread handler has been woken, but not | |
1046 | * yet finished. The bit is cleared when a thread | |
1047 | * completes. When all threads of a shared interrupt | |
1048 | * line have completed desc->threads_active becomes | |
1049 | * zero and the interrupt line is unmasked. See | |
1050 | * handle.c:irq_wake_thread() for further information. | |
1051 | * | |
1052 | * If no thread is woken by primary (hard irq context) | |
1053 | * interrupt handlers, then desc->threads_active is | |
1054 | * also checked for zero to unmask the irq line in the | |
1055 | * affected hard irq flow handlers | |
1056 | * (handle_[fasteoi|level]_irq). | |
1057 | * | |
1058 | * The new action gets the first zero bit of | |
1059 | * thread_mask assigned. See the loop above which or's | |
1060 | * all existing action->thread_mask bits. | |
1061 | */ | |
1062 | new->thread_mask = 1 << ffz(thread_mask); | |
1c6c6952 | 1063 | |
dc9b229a TG |
1064 | } else if (new->handler == irq_default_primary_handler && |
1065 | !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) { | |
1c6c6952 TG |
1066 | /* |
1067 | * The interrupt was requested with handler = NULL, so | |
1068 | * we use the default primary handler for it. But it | |
1069 | * does not have the oneshot flag set. In combination | |
1070 | * with level interrupts this is deadly, because the | |
1071 | * default primary handler just wakes the thread, then | |
1072 | * the irq lines is reenabled, but the device still | |
1073 | * has the level irq asserted. Rinse and repeat.... | |
1074 | * | |
1075 | * While this works for edge type interrupts, we play | |
1076 | * it safe and reject unconditionally because we can't | |
1077 | * say for sure which type this interrupt really | |
1078 | * has. The type flags are unreliable as the | |
1079 | * underlying chip implementation can override them. | |
1080 | */ | |
97fd75b7 | 1081 | pr_err("Threaded irq requested with handler=NULL and !ONESHOT for irq %d\n", |
1c6c6952 TG |
1082 | irq); |
1083 | ret = -EINVAL; | |
1084 | goto out_mask; | |
b5faba21 | 1085 | } |
b5faba21 | 1086 | |
1da177e4 | 1087 | if (!shared) { |
3aa551c9 TG |
1088 | init_waitqueue_head(&desc->wait_for_threads); |
1089 | ||
e76de9f8 | 1090 | /* Setup the type (level, edge polarity) if configured: */ |
3cca53b0 | 1091 | if (new->flags & IRQF_TRIGGER_MASK) { |
f2b662da DB |
1092 | ret = __irq_set_trigger(desc, irq, |
1093 | new->flags & IRQF_TRIGGER_MASK); | |
82736f4d | 1094 | |
3aa551c9 | 1095 | if (ret) |
3b8249e7 | 1096 | goto out_mask; |
091738a2 | 1097 | } |
6a6de9ef | 1098 | |
009b4c3b | 1099 | desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \ |
32f4125e TG |
1100 | IRQS_ONESHOT | IRQS_WAITING); |
1101 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
94d39e1f | 1102 | |
a005677b TG |
1103 | if (new->flags & IRQF_PERCPU) { |
1104 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
1105 | irq_settings_set_per_cpu(desc); | |
1106 | } | |
6a58fb3b | 1107 | |
b25c340c | 1108 | if (new->flags & IRQF_ONESHOT) |
3d67baec | 1109 | desc->istate |= IRQS_ONESHOT; |
b25c340c | 1110 | |
1ccb4e61 | 1111 | if (irq_settings_can_autoenable(desc)) |
b4bc724e | 1112 | irq_startup(desc, true); |
46999238 | 1113 | else |
e76de9f8 TG |
1114 | /* Undo nested disables: */ |
1115 | desc->depth = 1; | |
18404756 | 1116 | |
612e3684 | 1117 | /* Exclude IRQ from balancing if requested */ |
a005677b TG |
1118 | if (new->flags & IRQF_NOBALANCING) { |
1119 | irq_settings_set_no_balancing(desc); | |
1120 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
1121 | } | |
612e3684 | 1122 | |
18404756 | 1123 | /* Set default affinity mask once everything is setup */ |
3b8249e7 | 1124 | setup_affinity(irq, desc, mask); |
0c5d1eb7 | 1125 | |
876dbd4c TG |
1126 | } else if (new->flags & IRQF_TRIGGER_MASK) { |
1127 | unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK; | |
1128 | unsigned int omsk = irq_settings_get_trigger_mask(desc); | |
1129 | ||
1130 | if (nmsk != omsk) | |
1131 | /* hope the handler works with current trigger mode */ | |
97fd75b7 | 1132 | pr_warning("irq %d uses trigger mode %u; requested %u\n", |
876dbd4c | 1133 | irq, nmsk, omsk); |
1da177e4 | 1134 | } |
82736f4d | 1135 | |
69ab8494 | 1136 | new->irq = irq; |
f17c7545 | 1137 | *old_ptr = new; |
82736f4d | 1138 | |
8528b0f1 LT |
1139 | /* Reset broken irq detection when installing new handler */ |
1140 | desc->irq_count = 0; | |
1141 | desc->irqs_unhandled = 0; | |
1adb0850 TG |
1142 | |
1143 | /* | |
1144 | * Check whether we disabled the irq via the spurious handler | |
1145 | * before. Reenable it and give it another chance. | |
1146 | */ | |
7acdd53e TG |
1147 | if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) { |
1148 | desc->istate &= ~IRQS_SPURIOUS_DISABLED; | |
0a0c5168 | 1149 | __enable_irq(desc, irq, false); |
1adb0850 TG |
1150 | } |
1151 | ||
239007b8 | 1152 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 | 1153 | |
69ab8494 TG |
1154 | /* |
1155 | * Strictly no need to wake it up, but hung_task complains | |
1156 | * when no hard interrupt wakes the thread up. | |
1157 | */ | |
1158 | if (new->thread) | |
1159 | wake_up_process(new->thread); | |
1160 | ||
2c6927a3 | 1161 | register_irq_proc(irq, desc); |
1da177e4 LT |
1162 | new->dir = NULL; |
1163 | register_handler_proc(irq, new); | |
4f5058c3 | 1164 | free_cpumask_var(mask); |
1da177e4 LT |
1165 | |
1166 | return 0; | |
f5163427 DS |
1167 | |
1168 | mismatch: | |
3cca53b0 | 1169 | if (!(new->flags & IRQF_PROBE_SHARED)) { |
97fd75b7 | 1170 | pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n", |
f5d89470 TG |
1171 | irq, new->flags, new->name, old->flags, old->name); |
1172 | #ifdef CONFIG_DEBUG_SHIRQ | |
13e87ec6 | 1173 | dump_stack(); |
3f050447 | 1174 | #endif |
f5d89470 | 1175 | } |
3aa551c9 TG |
1176 | ret = -EBUSY; |
1177 | ||
3b8249e7 | 1178 | out_mask: |
1c389795 | 1179 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3b8249e7 TG |
1180 | free_cpumask_var(mask); |
1181 | ||
3aa551c9 | 1182 | out_thread: |
3aa551c9 TG |
1183 | if (new->thread) { |
1184 | struct task_struct *t = new->thread; | |
1185 | ||
1186 | new->thread = NULL; | |
05d74efa | 1187 | kthread_stop(t); |
3aa551c9 TG |
1188 | put_task_struct(t); |
1189 | } | |
b6873807 SAS |
1190 | out_mput: |
1191 | module_put(desc->owner); | |
3aa551c9 | 1192 | return ret; |
1da177e4 LT |
1193 | } |
1194 | ||
d3c60047 TG |
1195 | /** |
1196 | * setup_irq - setup an interrupt | |
1197 | * @irq: Interrupt line to setup | |
1198 | * @act: irqaction for the interrupt | |
1199 | * | |
1200 | * Used to statically setup interrupts in the early boot process. | |
1201 | */ | |
1202 | int setup_irq(unsigned int irq, struct irqaction *act) | |
1203 | { | |
986c011d | 1204 | int retval; |
d3c60047 TG |
1205 | struct irq_desc *desc = irq_to_desc(irq); |
1206 | ||
31d9d9b6 MZ |
1207 | if (WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
1208 | return -EINVAL; | |
986c011d DD |
1209 | chip_bus_lock(desc); |
1210 | retval = __setup_irq(irq, desc, act); | |
1211 | chip_bus_sync_unlock(desc); | |
1212 | ||
1213 | return retval; | |
d3c60047 | 1214 | } |
eb53b4e8 | 1215 | EXPORT_SYMBOL_GPL(setup_irq); |
d3c60047 | 1216 | |
31d9d9b6 | 1217 | /* |
cbf94f06 MD |
1218 | * Internal function to unregister an irqaction - used to free |
1219 | * regular and special interrupts that are part of the architecture. | |
1da177e4 | 1220 | */ |
cbf94f06 | 1221 | static struct irqaction *__free_irq(unsigned int irq, void *dev_id) |
1da177e4 | 1222 | { |
d3c60047 | 1223 | struct irq_desc *desc = irq_to_desc(irq); |
f17c7545 | 1224 | struct irqaction *action, **action_ptr; |
1da177e4 LT |
1225 | unsigned long flags; |
1226 | ||
ae88a23b | 1227 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); |
7d94f7ca | 1228 | |
7d94f7ca | 1229 | if (!desc) |
f21cfb25 | 1230 | return NULL; |
1da177e4 | 1231 | |
bf5cd0c6 | 1232 | chip_bus_lock(desc); |
239007b8 | 1233 | raw_spin_lock_irqsave(&desc->lock, flags); |
ae88a23b IM |
1234 | |
1235 | /* | |
1236 | * There can be multiple actions per IRQ descriptor, find the right | |
1237 | * one based on the dev_id: | |
1238 | */ | |
f17c7545 | 1239 | action_ptr = &desc->action; |
1da177e4 | 1240 | for (;;) { |
f17c7545 | 1241 | action = *action_ptr; |
1da177e4 | 1242 | |
ae88a23b IM |
1243 | if (!action) { |
1244 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
239007b8 | 1245 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
bf5cd0c6 | 1246 | chip_bus_sync_unlock(desc); |
f21cfb25 | 1247 | return NULL; |
ae88a23b | 1248 | } |
1da177e4 | 1249 | |
8316e381 IM |
1250 | if (action->dev_id == dev_id) |
1251 | break; | |
f17c7545 | 1252 | action_ptr = &action->next; |
ae88a23b | 1253 | } |
dbce706e | 1254 | |
ae88a23b | 1255 | /* Found it - now remove it from the list of entries: */ |
f17c7545 | 1256 | *action_ptr = action->next; |
ae88a23b | 1257 | |
ae88a23b | 1258 | /* If this was the last handler, shut down the IRQ line: */ |
46999238 TG |
1259 | if (!desc->action) |
1260 | irq_shutdown(desc); | |
3aa551c9 | 1261 | |
e7a297b0 PWJ |
1262 | #ifdef CONFIG_SMP |
1263 | /* make sure affinity_hint is cleaned up */ | |
1264 | if (WARN_ON_ONCE(desc->affinity_hint)) | |
1265 | desc->affinity_hint = NULL; | |
1266 | #endif | |
1267 | ||
239007b8 | 1268 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
bf5cd0c6 | 1269 | chip_bus_sync_unlock(desc); |
ae88a23b IM |
1270 | |
1271 | unregister_handler_proc(irq, action); | |
1272 | ||
1273 | /* Make sure it's not being used on another CPU: */ | |
1274 | synchronize_irq(irq); | |
1da177e4 | 1275 | |
70edcd77 | 1276 | #ifdef CONFIG_DEBUG_SHIRQ |
ae88a23b IM |
1277 | /* |
1278 | * It's a shared IRQ -- the driver ought to be prepared for an IRQ | |
1279 | * event to happen even now it's being freed, so let's make sure that | |
1280 | * is so by doing an extra call to the handler .... | |
1281 | * | |
1282 | * ( We do this after actually deregistering it, to make sure that a | |
1283 | * 'real' IRQ doesn't run in * parallel with our fake. ) | |
1284 | */ | |
1285 | if (action->flags & IRQF_SHARED) { | |
1286 | local_irq_save(flags); | |
1287 | action->handler(irq, dev_id); | |
1288 | local_irq_restore(flags); | |
1da177e4 | 1289 | } |
ae88a23b | 1290 | #endif |
2d860ad7 LT |
1291 | |
1292 | if (action->thread) { | |
05d74efa | 1293 | kthread_stop(action->thread); |
2d860ad7 LT |
1294 | put_task_struct(action->thread); |
1295 | } | |
1296 | ||
b6873807 | 1297 | module_put(desc->owner); |
f21cfb25 MD |
1298 | return action; |
1299 | } | |
1300 | ||
cbf94f06 MD |
1301 | /** |
1302 | * remove_irq - free an interrupt | |
1303 | * @irq: Interrupt line to free | |
1304 | * @act: irqaction for the interrupt | |
1305 | * | |
1306 | * Used to remove interrupts statically setup by the early boot process. | |
1307 | */ | |
1308 | void remove_irq(unsigned int irq, struct irqaction *act) | |
1309 | { | |
31d9d9b6 MZ |
1310 | struct irq_desc *desc = irq_to_desc(irq); |
1311 | ||
1312 | if (desc && !WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1313 | __free_irq(irq, act->dev_id); | |
cbf94f06 | 1314 | } |
eb53b4e8 | 1315 | EXPORT_SYMBOL_GPL(remove_irq); |
cbf94f06 | 1316 | |
f21cfb25 MD |
1317 | /** |
1318 | * free_irq - free an interrupt allocated with request_irq | |
1319 | * @irq: Interrupt line to free | |
1320 | * @dev_id: Device identity to free | |
1321 | * | |
1322 | * Remove an interrupt handler. The handler is removed and if the | |
1323 | * interrupt line is no longer in use by any driver it is disabled. | |
1324 | * On a shared IRQ the caller must ensure the interrupt is disabled | |
1325 | * on the card it drives before calling this function. The function | |
1326 | * does not return until any executing interrupts for this IRQ | |
1327 | * have completed. | |
1328 | * | |
1329 | * This function must not be called from interrupt context. | |
1330 | */ | |
1331 | void free_irq(unsigned int irq, void *dev_id) | |
1332 | { | |
70aedd24 TG |
1333 | struct irq_desc *desc = irq_to_desc(irq); |
1334 | ||
31d9d9b6 | 1335 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
70aedd24 TG |
1336 | return; |
1337 | ||
cd7eab44 BH |
1338 | #ifdef CONFIG_SMP |
1339 | if (WARN_ON(desc->affinity_notify)) | |
1340 | desc->affinity_notify = NULL; | |
1341 | #endif | |
1342 | ||
cbf94f06 | 1343 | kfree(__free_irq(irq, dev_id)); |
1da177e4 | 1344 | } |
1da177e4 LT |
1345 | EXPORT_SYMBOL(free_irq); |
1346 | ||
1347 | /** | |
3aa551c9 | 1348 | * request_threaded_irq - allocate an interrupt line |
1da177e4 | 1349 | * @irq: Interrupt line to allocate |
3aa551c9 TG |
1350 | * @handler: Function to be called when the IRQ occurs. |
1351 | * Primary handler for threaded interrupts | |
b25c340c TG |
1352 | * If NULL and thread_fn != NULL the default |
1353 | * primary handler is installed | |
f48fe81e TG |
1354 | * @thread_fn: Function called from the irq handler thread |
1355 | * If NULL, no irq thread is created | |
1da177e4 LT |
1356 | * @irqflags: Interrupt type flags |
1357 | * @devname: An ascii name for the claiming device | |
1358 | * @dev_id: A cookie passed back to the handler function | |
1359 | * | |
1360 | * This call allocates interrupt resources and enables the | |
1361 | * interrupt line and IRQ handling. From the point this | |
1362 | * call is made your handler function may be invoked. Since | |
1363 | * your handler function must clear any interrupt the board | |
1364 | * raises, you must take care both to initialise your hardware | |
1365 | * and to set up the interrupt handler in the right order. | |
1366 | * | |
3aa551c9 | 1367 | * If you want to set up a threaded irq handler for your device |
6d21af4f | 1368 | * then you need to supply @handler and @thread_fn. @handler is |
3aa551c9 TG |
1369 | * still called in hard interrupt context and has to check |
1370 | * whether the interrupt originates from the device. If yes it | |
1371 | * needs to disable the interrupt on the device and return | |
39a2eddb | 1372 | * IRQ_WAKE_THREAD which will wake up the handler thread and run |
3aa551c9 TG |
1373 | * @thread_fn. This split handler design is necessary to support |
1374 | * shared interrupts. | |
1375 | * | |
1da177e4 LT |
1376 | * Dev_id must be globally unique. Normally the address of the |
1377 | * device data structure is used as the cookie. Since the handler | |
1378 | * receives this value it makes sense to use it. | |
1379 | * | |
1380 | * If your interrupt is shared you must pass a non NULL dev_id | |
1381 | * as this is required when freeing the interrupt. | |
1382 | * | |
1383 | * Flags: | |
1384 | * | |
3cca53b0 | 1385 | * IRQF_SHARED Interrupt is shared |
0c5d1eb7 | 1386 | * IRQF_TRIGGER_* Specify active edge(s) or level |
1da177e4 LT |
1387 | * |
1388 | */ | |
3aa551c9 TG |
1389 | int request_threaded_irq(unsigned int irq, irq_handler_t handler, |
1390 | irq_handler_t thread_fn, unsigned long irqflags, | |
1391 | const char *devname, void *dev_id) | |
1da177e4 | 1392 | { |
06fcb0c6 | 1393 | struct irqaction *action; |
08678b08 | 1394 | struct irq_desc *desc; |
d3c60047 | 1395 | int retval; |
1da177e4 LT |
1396 | |
1397 | /* | |
1398 | * Sanity-check: shared interrupts must pass in a real dev-ID, | |
1399 | * otherwise we'll have trouble later trying to figure out | |
1400 | * which interrupt is which (messes up the interrupt freeing | |
1401 | * logic etc). | |
1402 | */ | |
3cca53b0 | 1403 | if ((irqflags & IRQF_SHARED) && !dev_id) |
1da177e4 | 1404 | return -EINVAL; |
7d94f7ca | 1405 | |
cb5bc832 | 1406 | desc = irq_to_desc(irq); |
7d94f7ca | 1407 | if (!desc) |
1da177e4 | 1408 | return -EINVAL; |
7d94f7ca | 1409 | |
31d9d9b6 MZ |
1410 | if (!irq_settings_can_request(desc) || |
1411 | WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
6550c775 | 1412 | return -EINVAL; |
b25c340c TG |
1413 | |
1414 | if (!handler) { | |
1415 | if (!thread_fn) | |
1416 | return -EINVAL; | |
1417 | handler = irq_default_primary_handler; | |
1418 | } | |
1da177e4 | 1419 | |
45535732 | 1420 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
1da177e4 LT |
1421 | if (!action) |
1422 | return -ENOMEM; | |
1423 | ||
1424 | action->handler = handler; | |
3aa551c9 | 1425 | action->thread_fn = thread_fn; |
1da177e4 | 1426 | action->flags = irqflags; |
1da177e4 | 1427 | action->name = devname; |
1da177e4 LT |
1428 | action->dev_id = dev_id; |
1429 | ||
3876ec9e | 1430 | chip_bus_lock(desc); |
d3c60047 | 1431 | retval = __setup_irq(irq, desc, action); |
3876ec9e | 1432 | chip_bus_sync_unlock(desc); |
70aedd24 | 1433 | |
377bf1e4 AV |
1434 | if (retval) |
1435 | kfree(action); | |
1436 | ||
6d83f94d | 1437 | #ifdef CONFIG_DEBUG_SHIRQ_FIXME |
6ce51c43 | 1438 | if (!retval && (irqflags & IRQF_SHARED)) { |
a304e1b8 DW |
1439 | /* |
1440 | * It's a shared IRQ -- the driver ought to be prepared for it | |
1441 | * to happen immediately, so let's make sure.... | |
377bf1e4 AV |
1442 | * We disable the irq to make sure that a 'real' IRQ doesn't |
1443 | * run in parallel with our fake. | |
a304e1b8 | 1444 | */ |
59845b1f | 1445 | unsigned long flags; |
a304e1b8 | 1446 | |
377bf1e4 | 1447 | disable_irq(irq); |
59845b1f | 1448 | local_irq_save(flags); |
377bf1e4 | 1449 | |
59845b1f | 1450 | handler(irq, dev_id); |
377bf1e4 | 1451 | |
59845b1f | 1452 | local_irq_restore(flags); |
377bf1e4 | 1453 | enable_irq(irq); |
a304e1b8 DW |
1454 | } |
1455 | #endif | |
1da177e4 LT |
1456 | return retval; |
1457 | } | |
3aa551c9 | 1458 | EXPORT_SYMBOL(request_threaded_irq); |
ae731f8d MZ |
1459 | |
1460 | /** | |
1461 | * request_any_context_irq - allocate an interrupt line | |
1462 | * @irq: Interrupt line to allocate | |
1463 | * @handler: Function to be called when the IRQ occurs. | |
1464 | * Threaded handler for threaded interrupts. | |
1465 | * @flags: Interrupt type flags | |
1466 | * @name: An ascii name for the claiming device | |
1467 | * @dev_id: A cookie passed back to the handler function | |
1468 | * | |
1469 | * This call allocates interrupt resources and enables the | |
1470 | * interrupt line and IRQ handling. It selects either a | |
1471 | * hardirq or threaded handling method depending on the | |
1472 | * context. | |
1473 | * | |
1474 | * On failure, it returns a negative value. On success, | |
1475 | * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED. | |
1476 | */ | |
1477 | int request_any_context_irq(unsigned int irq, irq_handler_t handler, | |
1478 | unsigned long flags, const char *name, void *dev_id) | |
1479 | { | |
1480 | struct irq_desc *desc = irq_to_desc(irq); | |
1481 | int ret; | |
1482 | ||
1483 | if (!desc) | |
1484 | return -EINVAL; | |
1485 | ||
1ccb4e61 | 1486 | if (irq_settings_is_nested_thread(desc)) { |
ae731f8d MZ |
1487 | ret = request_threaded_irq(irq, NULL, handler, |
1488 | flags, name, dev_id); | |
1489 | return !ret ? IRQC_IS_NESTED : ret; | |
1490 | } | |
1491 | ||
1492 | ret = request_irq(irq, handler, flags, name, dev_id); | |
1493 | return !ret ? IRQC_IS_HARDIRQ : ret; | |
1494 | } | |
1495 | EXPORT_SYMBOL_GPL(request_any_context_irq); | |
31d9d9b6 | 1496 | |
1e7c5fd2 | 1497 | void enable_percpu_irq(unsigned int irq, unsigned int type) |
31d9d9b6 MZ |
1498 | { |
1499 | unsigned int cpu = smp_processor_id(); | |
1500 | unsigned long flags; | |
1501 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1502 | ||
1503 | if (!desc) | |
1504 | return; | |
1505 | ||
1e7c5fd2 MZ |
1506 | type &= IRQ_TYPE_SENSE_MASK; |
1507 | if (type != IRQ_TYPE_NONE) { | |
1508 | int ret; | |
1509 | ||
1510 | ret = __irq_set_trigger(desc, irq, type); | |
1511 | ||
1512 | if (ret) { | |
32cffdde | 1513 | WARN(1, "failed to set type for IRQ%d\n", irq); |
1e7c5fd2 MZ |
1514 | goto out; |
1515 | } | |
1516 | } | |
1517 | ||
31d9d9b6 | 1518 | irq_percpu_enable(desc, cpu); |
1e7c5fd2 | 1519 | out: |
31d9d9b6 MZ |
1520 | irq_put_desc_unlock(desc, flags); |
1521 | } | |
36a5df85 | 1522 | EXPORT_SYMBOL_GPL(enable_percpu_irq); |
31d9d9b6 MZ |
1523 | |
1524 | void disable_percpu_irq(unsigned int irq) | |
1525 | { | |
1526 | unsigned int cpu = smp_processor_id(); | |
1527 | unsigned long flags; | |
1528 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1529 | ||
1530 | if (!desc) | |
1531 | return; | |
1532 | ||
1533 | irq_percpu_disable(desc, cpu); | |
1534 | irq_put_desc_unlock(desc, flags); | |
1535 | } | |
36a5df85 | 1536 | EXPORT_SYMBOL_GPL(disable_percpu_irq); |
31d9d9b6 MZ |
1537 | |
1538 | /* | |
1539 | * Internal function to unregister a percpu irqaction. | |
1540 | */ | |
1541 | static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1542 | { | |
1543 | struct irq_desc *desc = irq_to_desc(irq); | |
1544 | struct irqaction *action; | |
1545 | unsigned long flags; | |
1546 | ||
1547 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); | |
1548 | ||
1549 | if (!desc) | |
1550 | return NULL; | |
1551 | ||
1552 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1553 | ||
1554 | action = desc->action; | |
1555 | if (!action || action->percpu_dev_id != dev_id) { | |
1556 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
1557 | goto bad; | |
1558 | } | |
1559 | ||
1560 | if (!cpumask_empty(desc->percpu_enabled)) { | |
1561 | WARN(1, "percpu IRQ %d still enabled on CPU%d!\n", | |
1562 | irq, cpumask_first(desc->percpu_enabled)); | |
1563 | goto bad; | |
1564 | } | |
1565 | ||
1566 | /* Found it - now remove it from the list of entries: */ | |
1567 | desc->action = NULL; | |
1568 | ||
1569 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1570 | ||
1571 | unregister_handler_proc(irq, action); | |
1572 | ||
1573 | module_put(desc->owner); | |
1574 | return action; | |
1575 | ||
1576 | bad: | |
1577 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1578 | return NULL; | |
1579 | } | |
1580 | ||
1581 | /** | |
1582 | * remove_percpu_irq - free a per-cpu interrupt | |
1583 | * @irq: Interrupt line to free | |
1584 | * @act: irqaction for the interrupt | |
1585 | * | |
1586 | * Used to remove interrupts statically setup by the early boot process. | |
1587 | */ | |
1588 | void remove_percpu_irq(unsigned int irq, struct irqaction *act) | |
1589 | { | |
1590 | struct irq_desc *desc = irq_to_desc(irq); | |
1591 | ||
1592 | if (desc && irq_settings_is_per_cpu_devid(desc)) | |
1593 | __free_percpu_irq(irq, act->percpu_dev_id); | |
1594 | } | |
1595 | ||
1596 | /** | |
1597 | * free_percpu_irq - free an interrupt allocated with request_percpu_irq | |
1598 | * @irq: Interrupt line to free | |
1599 | * @dev_id: Device identity to free | |
1600 | * | |
1601 | * Remove a percpu interrupt handler. The handler is removed, but | |
1602 | * the interrupt line is not disabled. This must be done on each | |
1603 | * CPU before calling this function. The function does not return | |
1604 | * until any executing interrupts for this IRQ have completed. | |
1605 | * | |
1606 | * This function must not be called from interrupt context. | |
1607 | */ | |
1608 | void free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1609 | { | |
1610 | struct irq_desc *desc = irq_to_desc(irq); | |
1611 | ||
1612 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1613 | return; | |
1614 | ||
1615 | chip_bus_lock(desc); | |
1616 | kfree(__free_percpu_irq(irq, dev_id)); | |
1617 | chip_bus_sync_unlock(desc); | |
1618 | } | |
1619 | ||
1620 | /** | |
1621 | * setup_percpu_irq - setup a per-cpu interrupt | |
1622 | * @irq: Interrupt line to setup | |
1623 | * @act: irqaction for the interrupt | |
1624 | * | |
1625 | * Used to statically setup per-cpu interrupts in the early boot process. | |
1626 | */ | |
1627 | int setup_percpu_irq(unsigned int irq, struct irqaction *act) | |
1628 | { | |
1629 | struct irq_desc *desc = irq_to_desc(irq); | |
1630 | int retval; | |
1631 | ||
1632 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1633 | return -EINVAL; | |
1634 | chip_bus_lock(desc); | |
1635 | retval = __setup_irq(irq, desc, act); | |
1636 | chip_bus_sync_unlock(desc); | |
1637 | ||
1638 | return retval; | |
1639 | } | |
1640 | ||
1641 | /** | |
1642 | * request_percpu_irq - allocate a percpu interrupt line | |
1643 | * @irq: Interrupt line to allocate | |
1644 | * @handler: Function to be called when the IRQ occurs. | |
1645 | * @devname: An ascii name for the claiming device | |
1646 | * @dev_id: A percpu cookie passed back to the handler function | |
1647 | * | |
1648 | * This call allocates interrupt resources, but doesn't | |
1649 | * automatically enable the interrupt. It has to be done on each | |
1650 | * CPU using enable_percpu_irq(). | |
1651 | * | |
1652 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
1653 | * the handler gets called with the interrupted CPU's instance of | |
1654 | * that variable. | |
1655 | */ | |
1656 | int request_percpu_irq(unsigned int irq, irq_handler_t handler, | |
1657 | const char *devname, void __percpu *dev_id) | |
1658 | { | |
1659 | struct irqaction *action; | |
1660 | struct irq_desc *desc; | |
1661 | int retval; | |
1662 | ||
1663 | if (!dev_id) | |
1664 | return -EINVAL; | |
1665 | ||
1666 | desc = irq_to_desc(irq); | |
1667 | if (!desc || !irq_settings_can_request(desc) || | |
1668 | !irq_settings_is_per_cpu_devid(desc)) | |
1669 | return -EINVAL; | |
1670 | ||
1671 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
1672 | if (!action) | |
1673 | return -ENOMEM; | |
1674 | ||
1675 | action->handler = handler; | |
2ed0e645 | 1676 | action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND; |
31d9d9b6 MZ |
1677 | action->name = devname; |
1678 | action->percpu_dev_id = dev_id; | |
1679 | ||
1680 | chip_bus_lock(desc); | |
1681 | retval = __setup_irq(irq, desc, action); | |
1682 | chip_bus_sync_unlock(desc); | |
1683 | ||
1684 | if (retval) | |
1685 | kfree(action); | |
1686 | ||
1687 | return retval; | |
1688 | } |