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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pvr2fb.c
CommitLineData
fcb1fec7
PM		 1/*
2 * drivers/video/pvr2fb.c
1da177e4
LT		 3 *
4 * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
5 * Dreamcast.
6 *
7 * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org>
fcb1fec7 8 * Copyright (c) 2001 - 2008 Paul Mundt <lethal@linux-sh.org>
1da177e4 9 *
1da177e4
LT		 10 * This driver is mostly based on the excellent amifb and vfb sources. It uses
11 * an odd scheme for converting hardware values to/from framebuffer values,
12 * here are some hacked-up formulas:
13 *
14 * The Dreamcast has screen offsets from each side of its four borders and
15 * the start offsets of the display window. I used these values to calculate
16 * 'pseudo' values (think of them as placeholders) for the fb video mode, so
17 * that when it came time to convert these values back into their hardware
18 * values, I could just add mode- specific offsets to get the correct mode
19 * settings:
20 *
21 * left_margin = diwstart_h - borderstart_h;
22 * right_margin = borderstop_h - (diwstart_h + xres);
23 * upper_margin = diwstart_v - borderstart_v;
24 * lower_margin = borderstop_v - (diwstart_h + yres);
25 *
26 * hsync_len = borderstart_h + (hsync_total - borderstop_h);
27 * vsync_len = borderstart_v + (vsync_total - borderstop_v);
28 *
29 * Then, when it's time to convert back to hardware settings, the only
30 * constants are the borderstart_* offsets, all other values are derived from
31 * the fb video mode:
32 *
33 * // PAL
34 * borderstart_h = 116;
35 * borderstart_v = 44;
36 * ...
37 * borderstop_h = borderstart_h + hsync_total - hsync_len;
38 * ...
39 * diwstart_v = borderstart_v - upper_margin;
40 *
41 * However, in the current implementation, the borderstart values haven't had
42 * the benefit of being fully researched, so some modes may be broken.
43 */
44
45#undef DEBUG
46
47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/errno.h>
50#include <linux/string.h>
51#include <linux/mm.h>
1da177e4
LT		 52#include <linux/slab.h>
53#include <linux/delay.h>
1da177e4
LT		 54#include <linux/interrupt.h>
55#include <linux/fb.h>
56#include <linux/init.h>
57#include <linux/pci.h>
58
59#ifdef CONFIG_SH_DREAMCAST
60#include <asm/machvec.h>
0764bff4 61#include <mach-dreamcast/mach/sysasic.h>
1da177e4
LT		 62#endif
63
da62e71d 64#ifdef CONFIG_PVR2_DMA
1da177e4 65#include <linux/pagemap.h>
0764bff4 66#include <mach/dma.h>
1da177e4
LT		 67#include <asm/dma.h>
68#endif
69
70#ifdef CONFIG_SH_STORE_QUEUES
84902b7a 71#include <linux/uaccess.h>
0764bff4 72#include <cpu/sq.h>
1da177e4
LT		 73#endif
74
75#ifndef PCI_DEVICE_ID_NEC_NEON250
76# define PCI_DEVICE_ID_NEC_NEON250 0x0067
77#endif
78
79/* 2D video registers */
80#define DISP_BASE par->mmio_base
81#define DISP_BRDRCOLR (DISP_BASE + 0x40)
82#define DISP_DIWMODE (DISP_BASE + 0x44)
83#define DISP_DIWADDRL (DISP_BASE + 0x50)
84#define DISP_DIWADDRS (DISP_BASE + 0x54)
85#define DISP_DIWSIZE (DISP_BASE + 0x5c)
86#define DISP_SYNCCONF (DISP_BASE + 0xd0)
87#define DISP_BRDRHORZ (DISP_BASE + 0xd4)
88#define DISP_SYNCSIZE (DISP_BASE + 0xd8)
89#define DISP_BRDRVERT (DISP_BASE + 0xdc)
90#define DISP_DIWCONF (DISP_BASE + 0xe8)
91#define DISP_DIWHSTRT (DISP_BASE + 0xec)
92#define DISP_DIWVSTRT (DISP_BASE + 0xf0)
306c869c 93#define DISP_PIXDEPTH (DISP_BASE + 0x108)
1da177e4
LT		 94
95/* Pixel clocks, one for TV output, doubled for VGA output */
96#define TV_CLK 74239
97#define VGA_CLK 37119
98
99/* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
100#define PAL_HTOTAL 863
101#define PAL_VTOTAL 312
102#define NTSC_HTOTAL 857
103#define NTSC_VTOTAL 262
104
105/* Supported cable types */
106enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
107
108/* Supported video output types */
109enum { VO_PAL, VO_NTSC, VO_VGA };
110
111/* Supported palette types */
112enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
113
114struct pvr2_params { unsigned int val; char *name; };
48c68c4f 115static struct pvr2_params cables[] = {
1da177e4
LT		 116 { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
117};
118
48c68c4f 119static struct pvr2_params outputs[] = {
1da177e4
LT		 120 { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
121};
122
123/*
124 * This describes the current video mode
125 */
126
127static struct pvr2fb_par {
128 unsigned int hsync_total; /* Clocks/line */
129 unsigned int vsync_total; /* Lines/field */
130 unsigned int borderstart_h;
131 unsigned int borderstop_h;
132 unsigned int borderstart_v;
133 unsigned int borderstop_v;
134 unsigned int diwstart_h; /* Horizontal offset of the display field */
135 unsigned int diwstart_v; /* Vertical offset of the display field, for
136 interlaced modes, this is the long field */
137 unsigned long disp_start; /* Address of image within VRAM */
138 unsigned char is_interlaced; /* Is the display interlaced? */
139 unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
140 unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
141
142 unsigned long mmio_base; /* MMIO base */
9cd1c674 143 u32 palette[16];
1da177e4
LT		 144} *currentpar;
145
146static struct fb_info *fb_info;
147
48c68c4f 148static struct fb_fix_screeninfo pvr2_fix = {
1da177e4 149 .id = "NEC PowerVR2",
e9705a77
PM		 150 .type = FB_TYPE_PACKED_PIXELS,
151 .visual = FB_VISUAL_TRUECOLOR,
1da177e4
LT		 152 .ypanstep = 1,
153 .ywrapstep = 1,
e9705a77 154 .accel = FB_ACCEL_NONE,
1da177e4
LT		 155};
156
48c68c4f 157static struct fb_var_screeninfo pvr2_var = {
1da177e4
LT		 158 .xres = 640,
159 .yres = 480,
160 .xres_virtual = 640,
161 .yres_virtual = 480,
162 .bits_per_pixel =16,
163 .red = { 11, 5, 0 },
164 .green = { 5, 6, 0 },
165 .blue = { 0, 5, 0 },
166 .activate = FB_ACTIVATE_NOW,
167 .height = -1,
168 .width = -1,
169 .vmode = FB_VMODE_NONINTERLACED,
170};
171
172static int cable_type = CT_VGA;
173static int video_output = VO_VGA;
174
175static int nopan = 0;
176static int nowrap = 1;
177
178/*
179 * We do all updating, blanking, etc. during the vertical retrace period
180 */
181static unsigned int do_vmode_full = 0; /* Change the video mode */
182static unsigned int do_vmode_pan = 0; /* Update the video mode */
183static short do_blank = 0; /* (Un)Blank the screen */
184
185static unsigned int is_blanked = 0; /* Is the screen blanked? */
186
187#ifdef CONFIG_SH_STORE_QUEUES
d2b06a8b 188static unsigned long pvr2fb_map;
1da177e4
LT		 189#endif
190
da62e71d 191#ifdef CONFIG_PVR2_DMA
1da177e4
LT		 192static unsigned int shdma = PVR2_CASCADE_CHAN;
193static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
194#endif
195
1da177e4
LT		 196static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue,
197 unsigned int transp, struct fb_info *info);
198static int pvr2fb_blank(int blank, struct fb_info *info);
199static unsigned long get_line_length(int xres_virtual, int bpp);
200static void set_color_bitfields(struct fb_var_screeninfo *var);
201static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
202static int pvr2fb_set_par(struct fb_info *info);
203static void pvr2_update_display(struct fb_info *info);
204static void pvr2_init_display(struct fb_info *info);
205static void pvr2_do_blank(void);
7d12e780 206static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id);
1da177e4
LT		 207static int pvr2_init_cable(void);
208static int pvr2_get_param(const struct pvr2_params *p, const char *s,
209 int val, int size);
da62e71d 210#ifdef CONFIG_PVR2_DMA
3f9b0880 211static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
1da177e4 212 size_t count, loff_t *ppos);
d2b06a8b 213#endif
1da177e4
LT		 214
215static struct fb_ops pvr2fb_ops = {
d2b06a8b
PM		 216 .owner = THIS_MODULE,
217 .fb_setcolreg = pvr2fb_setcolreg,
218 .fb_blank = pvr2fb_blank,
219 .fb_check_var = pvr2fb_check_var,
220 .fb_set_par = pvr2fb_set_par,
da62e71d 221#ifdef CONFIG_PVR2_DMA
1da177e4
LT		 222 .fb_write = pvr2fb_write,
223#endif
e9705a77 224 .fb_fillrect = cfb_fillrect,
1da177e4
LT		 225 .fb_copyarea = cfb_copyarea,
226 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 227};
228
48c68c4f 229static struct fb_videomode pvr2_modedb[] = {
1da177e4
LT		 230 /*
231 * Broadcast video modes (PAL and NTSC). I'm unfamiliar with
232 * PAL-M and PAL-N, but from what I've read both modes parallel PAL and
233 * NTSC, so it shouldn't be a problem (I hope).
234 */
235
236 {
237 /* 640x480 @ 60Hz interlaced (NTSC) */
238 "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
239 FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
240 }, {
241 /* 640x240 @ 60Hz (NTSC) */
242 /* XXX: Broken! Don't use... */
243 "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
244 FB_SYNC_BROADCAST, FB_VMODE_YWRAP
245 }, {
246 /* 640x480 @ 60hz (VGA) */
247 "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
248 0, FB_VMODE_YWRAP
e9705a77 249 },
1da177e4
LT		 250};
251
252#define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
253
254#define DEFMODE_NTSC 0
255#define DEFMODE_PAL 0
256#define DEFMODE_VGA 2
257
258static int defmode = DEFMODE_NTSC;
48c68c4f 259static char *mode_option = NULL;
1da177e4
LT		 260
261static inline void pvr2fb_set_pal_type(unsigned int type)
262{
263 struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
264
265 fb_writel(type, par->mmio_base + 0x108);
266}
267
268static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
269 unsigned int regno,
270 unsigned int val)
271{
272 fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
273}
274
275static int pvr2fb_blank(int blank, struct fb_info *info)
276{
277 do_blank = blank ? blank : -1;
278 return 0;
279}
280
281static inline unsigned long get_line_length(int xres_virtual, int bpp)
282{
283 return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
284}
285
286static void set_color_bitfields(struct fb_var_screeninfo *var)
287{
288 switch (var->bits_per_pixel) {
289 case 16: /* RGB 565 */
e9705a77 290 pvr2fb_set_pal_type(PAL_RGB565);
1da177e4
LT		 291 var->red.offset = 11; var->red.length = 5;
292 var->green.offset = 5; var->green.length = 6;
293 var->blue.offset = 0; var->blue.length = 5;
294 var->transp.offset = 0; var->transp.length = 0;
295 break;
296 case 24: /* RGB 888 */
297 var->red.offset = 16; var->red.length = 8;
298 var->green.offset = 8; var->green.length = 8;
299 var->blue.offset = 0; var->blue.length = 8;
300 var->transp.offset = 0; var->transp.length = 0;
301 break;
302 case 32: /* ARGB 8888 */
e9705a77 303 pvr2fb_set_pal_type(PAL_ARGB8888);
1da177e4
LT		 304 var->red.offset = 16; var->red.length = 8;
305 var->green.offset = 8; var->green.length = 8;
306 var->blue.offset = 0; var->blue.length = 8;
307 var->transp.offset = 24; var->transp.length = 8;
308 break;
309 }
310}
311
312static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
313 unsigned int green, unsigned int blue,
314 unsigned int transp, struct fb_info *info)
315{
316 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
317 unsigned int tmp;
318
319 if (regno > info->cmap.len)
320 return 1;
321
322 /*
323 * We only support the hardware palette for 16 and 32bpp. It's also
324 * expected that the palette format has been set by the time we get
325 * here, so we don't waste time setting it again.
326 */
327 switch (info->var.bits_per_pixel) {
328 case 16: /* RGB 565 */
329 tmp = (red & 0xf800) |
330 ((green & 0xfc00) >> 5) |
331 ((blue & 0xf800) >> 11);
332
333 pvr2fb_set_pal_entry(par, regno, tmp);
1da177e4
LT		 334 break;
335 case 24: /* RGB 888 */
336 red >>= 8; green >>= 8; blue >>= 8;
a66ad56e 337 tmp = (red << 16) | (green << 8) | blue;
1da177e4
LT		 338 break;
339 case 32: /* ARGB 8888 */
340 red >>= 8; green >>= 8; blue >>= 8;
341 tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
342
343 pvr2fb_set_pal_entry(par, regno, tmp);
1da177e4
LT		 344 break;
345 default:
346 pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
347 return 1;
348 }
349
a66ad56e
AD		 350 if (regno < 16)
351 ((u32*)(info->pseudo_palette))[regno] = tmp;
352
1da177e4
LT		 353 return 0;
354}
355
356static int pvr2fb_set_par(struct fb_info *info)
357{
358 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
359 struct fb_var_screeninfo *var = &info->var;
360 unsigned long line_length;
361 unsigned int vtotal;
362
363 /*
364 * XXX: It's possible that a user could use a VGA box, change the cable
365 * type in hardware (i.e. switch from VGA<->composite), then change
366 * modes (i.e. switching to another VT). If that happens we should
367 * automagically change the output format to cope, but currently I
368 * don't have a VGA box to make sure this works properly.
369 */
370 cable_type = pvr2_init_cable();
371 if (cable_type == CT_VGA && video_output != VO_VGA)
372 video_output = VO_VGA;
373
374 var->vmode &= FB_VMODE_MASK;
375 if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
376 par->is_interlaced = 1;
e9705a77 377 /*
1da177e4
LT		 378 * XXX: Need to be more creative with this (i.e. allow doublecan for
379 * PAL/NTSC output).
380 */
381 if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
382 par->is_doublescan = 1;
e9705a77 383
1da177e4
LT		 384 par->hsync_total = var->left_margin + var->xres + var->right_margin +
385 var->hsync_len;
386 par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
387 var->vsync_len;
388
389 if (var->sync & FB_SYNC_BROADCAST) {
390 vtotal = par->vsync_total;
391 if (par->is_interlaced)
392 vtotal /= 2;
393 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
394 /* XXX: Check for start values here... */
395 /* XXX: Check hardware for PAL-compatibility */
396 par->borderstart_h = 116;
397 par->borderstart_v = 44;
398 } else {
399 /* NTSC video output */
400 par->borderstart_h = 126;
401 par->borderstart_v = 18;
402 }
403 } else {
404 /* VGA mode */
405 /* XXX: What else needs to be checked? */
e9705a77 406 /*
1da177e4
LT		 407 * XXX: We have a little freedom in VGA modes, what ranges
408 * should be here (i.e. hsync/vsync totals, etc.)?
409 */
410 par->borderstart_h = 126;
411 par->borderstart_v = 40;
412 }
413
414 /* Calculate the remainding offsets */
415 par->diwstart_h = par->borderstart_h + var->left_margin;
416 par->diwstart_v = par->borderstart_v + var->upper_margin;
e9705a77
PM		 417 par->borderstop_h = par->diwstart_h + var->xres +
418 var->right_margin;
1da177e4
LT		 419 par->borderstop_v = par->diwstart_v + var->yres +
420 var->lower_margin;
421
422 if (!par->is_interlaced)
423 par->borderstop_v /= 2;
424 if (info->var.xres < 640)
425 par->is_lowres = 1;
426
427 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
428 par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
429 info->fix.line_length = line_length;
430 return 0;
431}
432
433static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
434{
435 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
436 unsigned int vtotal, hsync_total;
437 unsigned long line_length;
438
439 if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
440 pr_debug("Invalid pixclock value %d\n", var->pixclock);
441 return -EINVAL;
442 }
443
444 if (var->xres < 320)
445 var->xres = 320;
446 if (var->yres < 240)
447 var->yres = 240;
448 if (var->xres_virtual < var->xres)
449 var->xres_virtual = var->xres;
450 if (var->yres_virtual < var->yres)
451 var->yres_virtual = var->yres;
452
453 if (var->bits_per_pixel <= 16)
454 var->bits_per_pixel = 16;
455 else if (var->bits_per_pixel <= 24)
456 var->bits_per_pixel = 24;
457 else if (var->bits_per_pixel <= 32)
458 var->bits_per_pixel = 32;
459
460 set_color_bitfields(var);
461
462 if (var->vmode & FB_VMODE_YWRAP) {
e9705a77 463 if (var->xoffset || var->yoffset < 0 ||
1da177e4
LT		 464 var->yoffset >= var->yres_virtual) {
465 var->xoffset = var->yoffset = 0;
466 } else {
467 if (var->xoffset > var->xres_virtual - var->xres ||
e9705a77 468 var->yoffset > var->yres_virtual - var->yres ||
1da177e4
LT		 469 var->xoffset < 0 || var->yoffset < 0)
470 var->xoffset = var->yoffset = 0;
471 }
472 } else {
473 var->xoffset = var->yoffset = 0;
474 }
475
e9705a77 476 /*
1da177e4
LT		 477 * XXX: Need to be more creative with this (i.e. allow doublecan for
478 * PAL/NTSC output).
479 */
480 if (var->yres < 480 && video_output == VO_VGA)
481 var->vmode |= FB_VMODE_DOUBLE;
482
483 if (video_output != VO_VGA) {
484 var->sync |= FB_SYNC_BROADCAST;
485 var->vmode |= FB_VMODE_INTERLACED;
486 } else {
487 var->sync &= ~FB_SYNC_BROADCAST;
488 var->vmode &= ~FB_VMODE_INTERLACED;
fcb1fec7 489 var->vmode |= FB_VMODE_NONINTERLACED;
1da177e4
LT		 490 }
491
492 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
493 var->right_margin = par->borderstop_h -
494 (par->diwstart_h + var->xres);
495 var->left_margin = par->diwstart_h - par->borderstart_h;
496 var->hsync_len = par->borderstart_h +
497 (par->hsync_total - par->borderstop_h);
498
499 var->upper_margin = par->diwstart_v - par->borderstart_v;
500 var->lower_margin = par->borderstop_v -
501 (par->diwstart_v + var->yres);
502 var->vsync_len = par->borderstop_v +
503 (par->vsync_total - par->borderstop_v);
504 }
e9705a77 505
1da177e4
LT		 506 hsync_total = var->left_margin + var->xres + var->right_margin +
507 var->hsync_len;
508 vtotal = var->upper_margin + var->yres + var->lower_margin +
509 var->vsync_len;
510
511 if (var->sync & FB_SYNC_BROADCAST) {
512 if (var->vmode & FB_VMODE_INTERLACED)
513 vtotal /= 2;
514 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
515 /* PAL video output */
516 /* XXX: Should be using a range here ... ? */
517 if (hsync_total != PAL_HTOTAL) {
518 pr_debug("invalid hsync total for PAL\n");
519 return -EINVAL;
520 }
521 } else {
522 /* NTSC video output */
523 if (hsync_total != NTSC_HTOTAL) {
524 pr_debug("invalid hsync total for NTSC\n");
525 return -EINVAL;
526 }
527 }
528 }
e9705a77 529
1da177e4
LT		 530 /* Check memory sizes */
531 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
532 if (line_length * var->yres_virtual > info->fix.smem_len)
533 return -ENOMEM;
534
535 return 0;
536}
537
538static void pvr2_update_display(struct fb_info *info)
539{
540 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
541 struct fb_var_screeninfo *var = &info->var;
542
543 /* Update the start address of the display image */
544 fb_writel(par->disp_start, DISP_DIWADDRL);
545 fb_writel(par->disp_start +
546 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
547 DISP_DIWADDRS);
548}
549
e9705a77 550/*
1da177e4
LT		 551 * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
552 * very stable. It's probably due to the fact that a lot of the 2D video
553 * registers are still undocumented.
554 */
555
556static void pvr2_init_display(struct fb_info *info)
557{
558 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
559 struct fb_var_screeninfo *var = &info->var;
560 unsigned int diw_height, diw_width, diw_modulo = 1;
561 unsigned int bytesperpixel = var->bits_per_pixel >> 3;
562
563 /* hsync and vsync totals */
564 fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
565
566 /* column height, modulo, row width */
567 /* since we're "panning" within vram, we need to offset things based
568 * on the offset from the virtual x start to our real gfx. */
569 if (video_output != VO_VGA && par->is_interlaced)
570 diw_modulo += info->fix.line_length / 4;
571 diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
572 diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
573 fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
574 DISP_DIWSIZE);
575
576 /* display address, long and short fields */
577 fb_writel(par->disp_start, DISP_DIWADDRL);
578 fb_writel(par->disp_start +
579 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
580 DISP_DIWADDRS);
581
582 /* border horizontal, border vertical, border color */
583 fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
584 fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
585 fb_writel(0, DISP_BRDRCOLR);
586
587 /* display window start position */
588 fb_writel(par->diwstart_h, DISP_DIWHSTRT);
589 fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
e9705a77 590
1da177e4
LT		 591 /* misc. settings */
592 fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
593
594 /* clock doubler (for VGA), scan doubler, display enable */
e9705a77 595 fb_writel(((video_output == VO_VGA) << 23) |
1da177e4
LT		 596 (par->is_doublescan << 1) | 1, DISP_DIWMODE);
597
598 /* bits per pixel */
599 fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
306c869c 600 fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);
1da177e4 601
e9705a77 602 /* video enable, color sync, interlace,
1da177e4
LT		 603 * hsync and vsync polarity (currently unused) */
604 fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
605}
606
607/* Simulate blanking by making the border cover the entire screen */
608
609#define BLANK_BIT (1<<3)
610
611static void pvr2_do_blank(void)
612{
613 struct pvr2fb_par *par = currentpar;
614 unsigned long diwconf;
615
616 diwconf = fb_readl(DISP_DIWCONF);
617 if (do_blank > 0)
618 fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
619 else
620 fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
621
622 is_blanked = do_blank > 0 ? do_blank : 0;
623}
624
7d12e780 625static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id)
1da177e4
LT		 626{
627 struct fb_info *info = dev_id;
628
629 if (do_vmode_pan || do_vmode_full)
630 pvr2_update_display(info);
631 if (do_vmode_full)
632 pvr2_init_display(info);
633 if (do_vmode_pan)
634 do_vmode_pan = 0;
635 if (do_vmode_full)
636 do_vmode_full = 0;
637 if (do_blank) {
638 pvr2_do_blank();
639 do_blank = 0;
640 }
641 return IRQ_HANDLED;
642}
643
644/*
645 * Determine the cable type and initialize the cable output format. Don't do
646 * anything if the cable type has been overidden (via "cable:XX").
647 */
648
649#define PCTRA 0xff80002c
650#define PDTRA 0xff800030
651#define VOUTC 0xa0702c00
652
653static int pvr2_init_cable(void)
654{
655 if (cable_type < 0) {
e9705a77 656 fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
1da177e4
LT		 657 PCTRA);
658 cable_type = (fb_readw(PDTRA) >> 8) & 3;
659 }
660
661 /* Now select the output format (either composite or other) */
662 /* XXX: Save the previous val first, as this reg is also AICA
663 related */
664 if (cable_type == CT_COMPOSITE)
665 fb_writel(3 << 8, VOUTC);
78d7e0e5
AM		 666 else if (cable_type == CT_RGB)
667 fb_writel(1 << 9, VOUTC);
1da177e4
LT		 668 else
669 fb_writel(0, VOUTC);
670
671 return cable_type;
672}
673
da62e71d 674#ifdef CONFIG_PVR2_DMA
3f9b0880 675static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
1da177e4
LT		 676 size_t count, loff_t *ppos)
677{
678 unsigned long dst, start, end, len;
679 unsigned int nr_pages;
680 struct page **pages;
681 int ret, i;
682
683 nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
684
685 pages = kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
686 if (!pages)
687 return -ENOMEM;
e9705a77 688
1da177e4
LT		 689 down_read(&current->mm->mmap_sem);
690 ret = get_user_pages(current, current->mm, (unsigned long)buf,
691 nr_pages, WRITE, 0, pages, NULL);
692 up_read(&current->mm->mmap_sem);
693
694 if (ret < nr_pages) {
695 nr_pages = ret;
696 ret = -EINVAL;
697 goto out_unmap;
698 }
699
700 dma_configure_channel(shdma, 0x12c1);
e9705a77 701
1da177e4
LT		 702 dst = (unsigned long)fb_info->screen_base + *ppos;
703 start = (unsigned long)page_address(pages[0]);
704 end = (unsigned long)page_address(pages[nr_pages]);
705 len = nr_pages << PAGE_SHIFT;
706
707 /* Half-assed contig check */
708 if (start + len == end) {
709 /* As we do this in one shot, it's either all or nothing.. */
710 if ((*ppos + len) > fb_info->fix.smem_len) {
711 ret = -ENOSPC;
712 goto out_unmap;
713 }
714
715 dma_write(shdma, start, 0, len);
716 dma_write(pvr2dma, 0, dst, len);
717 dma_wait_for_completion(pvr2dma);
718
719 goto out;
720 }
721
722 /* Not contiguous, writeout per-page instead.. */
723 for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
724 if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
725 ret = -ENOSPC;
726 goto out_unmap;
727 }
728
729 dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
730 dma_write_page(pvr2dma, 0, dst);
731 dma_wait_for_completion(pvr2dma);
732 }
733
734out:
735 *ppos += count;
736 ret = count;
737
738out_unmap:
739 for (i = 0; i < nr_pages; i++)
740 page_cache_release(pages[i]);
741
742 kfree(pages);
743
744 return ret;
e9705a77 745}
da62e71d 746#endif /* CONFIG_PVR2_DMA */
1da177e4
LT		 747
748/**
749 * pvr2fb_common_init
750 *
751 * Common init code for the PVR2 chips.
752 *
753 * This mostly takes care of the common aspects of the fb setup and
754 * registration. It's expected that the board-specific init code has
755 * already setup pvr2_fix with something meaningful at this point.
756 *
757 * Device info reporting is also done here, as well as picking a sane
758 * default from the modedb. For board-specific modelines, simply define
759 * a per-board modedb.
760 *
761 * Also worth noting is that the cable and video output types are likely
762 * always going to be VGA for the PCI-based PVR2 boards, but we leave this
763 * in for flexibility anyways. Who knows, maybe someone has tv-out on a
764 * PCI-based version of these things ;-)
765 */
48c68c4f 766static int pvr2fb_common_init(void)
1da177e4
LT		 767{
768 struct pvr2fb_par *par = currentpar;
769 unsigned long modememused, rev;
770
771 fb_info->screen_base = ioremap_nocache(pvr2_fix.smem_start,
772 pvr2_fix.smem_len);
e9705a77 773
1da177e4
LT		 774 if (!fb_info->screen_base) {
775 printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
776 goto out_err;
777 }
778
779 par->mmio_base = (unsigned long)ioremap_nocache(pvr2_fix.mmio_start,
e9705a77 780 pvr2_fix.mmio_len);
1da177e4
LT		 781 if (!par->mmio_base) {
782 printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
783 goto out_err;
784 }
785
d2b06a8b 786 fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
1da177e4
LT		 787
788 pvr2_fix.ypanstep = nopan ? 0 : 1;
789 pvr2_fix.ywrapstep = nowrap ? 0 : 1;
790
791 fb_info->fbops = &pvr2fb_ops;
792 fb_info->fix = pvr2_fix;
793 fb_info->par = currentpar;
9cd1c674 794 fb_info->pseudo_palette = currentpar->palette;
1da177e4
LT		 795 fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
796
797 if (video_output == VO_VGA)
798 defmode = DEFMODE_VGA;
799
800 if (!mode_option)
801 mode_option = "640x480@60";
802
803 if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
804 NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
805 fb_info->var = pvr2_var;
806
807 fb_alloc_cmap(&fb_info->cmap, 256, 0);
808
809 if (register_framebuffer(fb_info) < 0)
810 goto out_err;
306c869c
AM		 811 /*Must write PIXDEPTH to register before anything is displayed - so force init */
812 pvr2_init_display(fb_info);
1da177e4
LT		 813
814 modememused = get_line_length(fb_info->var.xres_virtual,
815 fb_info->var.bits_per_pixel);
816 modememused *= fb_info->var.yres_virtual;
817
818 rev = fb_readl(par->mmio_base + 0x04);
819
820 printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
821 fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
822 modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10));
e9705a77 823 printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
1da177e4 824 fb_info->node, fb_info->var.xres, fb_info->var.yres,
d2b06a8b 825 fb_info->var.bits_per_pixel,
1da177e4
LT		 826 get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
827 (char *)pvr2_get_param(cables, NULL, cable_type, 3),
828 (char *)pvr2_get_param(outputs, NULL, video_output, 3));
829
830#ifdef CONFIG_SH_STORE_QUEUES
831 printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node);
832
833 pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
7bdda620 834 fb_info->fix.id, PAGE_SHARED);
1da177e4
LT		 835
836 printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n",
d2b06a8b 837 fb_info->node, pvr2fb_map);
1da177e4
LT		 838#endif
839
840 return 0;
841
842out_err:
843 if (fb_info->screen_base)
844 iounmap(fb_info->screen_base);
845 if (par->mmio_base)
846 iounmap((void *)par->mmio_base);
847
848 return -ENXIO;
849}
850
851#ifdef CONFIG_SH_DREAMCAST
852static int __init pvr2fb_dc_init(void)
853{
854 if (!mach_is_dreamcast())
855 return -ENXIO;
856
857 /* Make a guess at the monitor based on the attached cable */
858 if (pvr2_init_cable() == CT_VGA) {
859 fb_info->monspecs.hfmin = 30000;
860 fb_info->monspecs.hfmax = 70000;
861 fb_info->monspecs.vfmin = 60;
862 fb_info->monspecs.vfmax = 60;
863 } else {
864 /* Not VGA, using a TV (taken from acornfb) */
865 fb_info->monspecs.hfmin = 15469;
866 fb_info->monspecs.hfmax = 15781;
867 fb_info->monspecs.vfmin = 49;
868 fb_info->monspecs.vfmax = 51;
869 }
870
871 /*
872 * XXX: This needs to pull default video output via BIOS or other means
873 */
874 if (video_output < 0) {
875 if (cable_type == CT_VGA) {
876 video_output = VO_VGA;
877 } else {
878 video_output = VO_NTSC;
879 }
880 }
e9705a77
PM		 881
882 /*
1da177e4
LT		 883 * Nothing exciting about the DC PVR2 .. only a measly 8MiB.
884 */
885 pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
886 pvr2_fix.smem_len = 8 << 20;
887
888 pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
889 pvr2_fix.mmio_len = 0x2000;
890
123f5f18 891 if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, IRQF_SHARED,
1da177e4
LT		 892 "pvr2 VBL handler", fb_info)) {
893 return -EBUSY;
894 }
895
da62e71d 896#ifdef CONFIG_PVR2_DMA
1da177e4 897 if (request_dma(pvr2dma, "pvr2") != 0) {
afb0499b 898 free_irq(HW_EVENT_VSYNC, fb_info);
1da177e4
LT		 899 return -EBUSY;
900 }
901#endif
902
903 return pvr2fb_common_init();
904}
905
e9705a77 906static void __exit pvr2fb_dc_exit(void)
1da177e4 907{
295a1b47
AL		 908 if (fb_info->screen_base) {
909 iounmap(fb_info->screen_base);
910 fb_info->screen_base = NULL;
911 }
912 if (currentpar->mmio_base) {
913 iounmap((void *)currentpar->mmio_base);
914 currentpar->mmio_base = 0;
915 }
916
afb0499b 917 free_irq(HW_EVENT_VSYNC, fb_info);
da62e71d 918#ifdef CONFIG_PVR2_DMA
1da177e4
LT		 919 free_dma(pvr2dma);
920#endif
921}
922#endif /* CONFIG_SH_DREAMCAST */
923
924#ifdef CONFIG_PCI
48c68c4f
GKH		 925static int pvr2fb_pci_probe(struct pci_dev *pdev,
926 const struct pci_device_id *ent)
1da177e4
LT		 927{
928 int ret;
929
930 ret = pci_enable_device(pdev);
931 if (ret) {
932 printk(KERN_ERR "pvr2fb: PCI enable failed\n");
933 return ret;
934 }
935
936 ret = pci_request_regions(pdev, "pvr2fb");
937 if (ret) {
938 printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
939 return ret;
940 }
941
942 /*
943 * Slightly more exciting than the DC PVR2 .. 16MiB!
944 */
945 pvr2_fix.smem_start = pci_resource_start(pdev, 0);
946 pvr2_fix.smem_len = pci_resource_len(pdev, 0);
947
948 pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
949 pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
950
951 fb_info->device = &pdev->dev;
952
953 return pvr2fb_common_init();
954}
955
48c68c4f 956static void pvr2fb_pci_remove(struct pci_dev *pdev)
1da177e4 957{
295a1b47
AL		 958 if (fb_info->screen_base) {
959 iounmap(fb_info->screen_base);
960 fb_info->screen_base = NULL;
961 }
962 if (currentpar->mmio_base) {
963 iounmap((void *)currentpar->mmio_base);
964 currentpar->mmio_base = 0;
965 }
966
1da177e4
LT		 967 pci_release_regions(pdev);
968}
969
48c68c4f 970static struct pci_device_id pvr2fb_pci_tbl[] = {
1da177e4
LT		 971 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
973 { 0, },
974};
975
976MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
977
978static struct pci_driver pvr2fb_pci_driver = {
979 .name = "pvr2fb",
980 .id_table = pvr2fb_pci_tbl,
981 .probe = pvr2fb_pci_probe,
48c68c4f 982 .remove = pvr2fb_pci_remove,
1da177e4
LT		 983};
984
985static int __init pvr2fb_pci_init(void)
986{
987 return pci_register_driver(&pvr2fb_pci_driver);
988}
989
e9705a77 990static void __exit pvr2fb_pci_exit(void)
1da177e4
LT		 991{
992 pci_unregister_driver(&pvr2fb_pci_driver);
993}
994#endif /* CONFIG_PCI */
995
48c68c4f
GKH		 996static int pvr2_get_param(const struct pvr2_params *p, const char *s, int val,
997 int size)
1da177e4
LT		 998{
999 int i;
1000
1001 for (i = 0 ; i < size ; i++ ) {
1002 if (s != NULL) {
1003 if (!strnicmp(p[i].name, s, strlen(s)))
1004 return p[i].val;
1005 } else {
1006 if (p[i].val == val)
1007 return (int)p[i].name;
1008 }
1009 }
1010 return -1;
1011}
1012
1013/*
1014 * Parse command arguments. Supported arguments are:
1015 * inverse Use inverse color maps
1016 * cable:composite|rgb|vga Override the video cable type
1017 * output:NTSC|PAL|VGA Override the video output format
1018 *
1019 * <xres>x<yres>[-<bpp>][@<refresh>] or,
1020 * <name>[-<bpp>][@<refresh>] Startup using this video mode
1021 */
1022
1023#ifndef MODULE
e9705a77 1024static int __init pvr2fb_setup(char *options)
1da177e4
LT		 1025{
1026 char *this_opt;
1027 char cable_arg[80];
1028 char output_arg[80];
1029
1030 if (!options || !*options)
1031 return 0;
1032
1033 while ((this_opt = strsep(&options, ","))) {
1034 if (!*this_opt)
1035 continue;
1036 if (!strcmp(this_opt, "inverse")) {
1037 fb_invert_cmaps();
1038 } else if (!strncmp(this_opt, "cable:", 6)) {
1039 strcpy(cable_arg, this_opt + 6);
1040 } else if (!strncmp(this_opt, "output:", 7)) {
1041 strcpy(output_arg, this_opt + 7);
1042 } else if (!strncmp(this_opt, "nopan", 5)) {
1043 nopan = 1;
1044 } else if (!strncmp(this_opt, "nowrap", 6)) {
1045 nowrap = 1;
1046 } else {
1047 mode_option = this_opt;
1048 }
1049 }
1050
1051 if (*cable_arg)
1052 cable_type = pvr2_get_param(cables, cable_arg, 0, 3);
1053 if (*output_arg)
1054 video_output = pvr2_get_param(outputs, output_arg, 0, 3);
1055
1056 return 0;
1057}
1058#endif
1059
1060static struct pvr2_board {
1061 int (*init)(void);
1062 void (*exit)(void);
1063 char name[16];
6d7120a7 1064} board_driver[] __refdata = {
1da177e4
LT		 1065#ifdef CONFIG_SH_DREAMCAST
1066 { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
1067#endif
1068#ifdef CONFIG_PCI
1069 { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
1070#endif
1071 { 0, },
1072};
1073
e9705a77 1074static int __init pvr2fb_init(void)
1da177e4
LT		 1075{
1076 int i, ret = -ENODEV;
1077 int size;
1078
1079#ifndef MODULE
1080 char *option = NULL;
1081
1082 if (fb_get_options("pvr2fb", &option))
1083 return -ENODEV;
1084 pvr2fb_setup(option);
1085#endif
1086 size = sizeof(struct fb_info) + sizeof(struct pvr2fb_par) + 16 * sizeof(u32);
1087
9cd1c674
AD		 1088 fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
1089
1da177e4
LT		 1090 if (!fb_info) {
1091 printk(KERN_ERR "Failed to allocate memory for fb_info\n");
1092 return -ENOMEM;
1093 }
1094
1da177e4 1095
9cd1c674 1096 currentpar = fb_info->par;
1da177e4 1097
e9705a77
PM		 1098 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1099 struct pvr2_board *pvr_board = board_driver + i;
1da177e4
LT		 1100
1101 if (!pvr_board->init)
1102 continue;
1103
1104 ret = pvr_board->init();
1105
1106 if (ret != 0) {
1107 printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
1108 pvr_board->name);
9cd1c674 1109 framebuffer_release(fb_info);
1da177e4
LT		 1110 break;
1111 }
1112 }
1113
1114 return ret;
1115}
1116
1117static void __exit pvr2fb_exit(void)
1118{
1119 int i;
1120
e9705a77
PM		 1121 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1122 struct pvr2_board *pvr_board = board_driver + i;
1da177e4
LT		 1123
1124 if (pvr_board->exit)
1125 pvr_board->exit();
1126 }
e9705a77 1127
1da177e4
LT		 1128#ifdef CONFIG_SH_STORE_QUEUES
1129 sq_unmap(pvr2fb_map);
1130#endif
1131
1132 unregister_framebuffer(fb_info);
9cd1c674 1133 framebuffer_release(fb_info);
1da177e4
LT		 1134}
1135
1136module_init(pvr2fb_init);
1137module_exit(pvr2fb_exit);
1138
1139MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
1140MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
1141MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)