projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
vt: Fix warnings in selection.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pvr2fb.c
CommitLineData
1da177e4
LT		 1/* drivers/video/pvr2fb.c
2 *
3 * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
4 * Dreamcast.
5 *
6 * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org>
7 * Copyright (c) 2001, 2002, 2003, 2004, 2005 Paul Mundt <lethal@linux-sh.org>
8 *
9 * This file is part of the LinuxDC project (linuxdc.sourceforge.net).
10 *
11 */
12
13/*
14 * This driver is mostly based on the excellent amifb and vfb sources. It uses
15 * an odd scheme for converting hardware values to/from framebuffer values,
16 * here are some hacked-up formulas:
17 *
18 * The Dreamcast has screen offsets from each side of its four borders and
19 * the start offsets of the display window. I used these values to calculate
20 * 'pseudo' values (think of them as placeholders) for the fb video mode, so
21 * that when it came time to convert these values back into their hardware
22 * values, I could just add mode- specific offsets to get the correct mode
23 * settings:
24 *
25 * left_margin = diwstart_h - borderstart_h;
26 * right_margin = borderstop_h - (diwstart_h + xres);
27 * upper_margin = diwstart_v - borderstart_v;
28 * lower_margin = borderstop_v - (diwstart_h + yres);
29 *
30 * hsync_len = borderstart_h + (hsync_total - borderstop_h);
31 * vsync_len = borderstart_v + (vsync_total - borderstop_v);
32 *
33 * Then, when it's time to convert back to hardware settings, the only
34 * constants are the borderstart_* offsets, all other values are derived from
35 * the fb video mode:
36 *
37 * // PAL
38 * borderstart_h = 116;
39 * borderstart_v = 44;
40 * ...
41 * borderstop_h = borderstart_h + hsync_total - hsync_len;
42 * ...
43 * diwstart_v = borderstart_v - upper_margin;
44 *
45 * However, in the current implementation, the borderstart values haven't had
46 * the benefit of being fully researched, so some modes may be broken.
47 */
48
49#undef DEBUG
50
51#include <linux/module.h>
52#include <linux/kernel.h>
53#include <linux/errno.h>
54#include <linux/string.h>
55#include <linux/mm.h>
1da177e4
LT		 56#include <linux/slab.h>
57#include <linux/delay.h>
1da177e4
LT		 58#include <linux/interrupt.h>
59#include <linux/fb.h>
60#include <linux/init.h>
61#include <linux/pci.h>
62
63#ifdef CONFIG_SH_DREAMCAST
64#include <asm/machvec.h>
65#include <asm/mach/sysasic.h>
66#endif
67
68#ifdef CONFIG_SH_DMA
69#include <linux/pagemap.h>
70#include <asm/mach/dma.h>
71#include <asm/dma.h>
72#endif
73
74#ifdef CONFIG_SH_STORE_QUEUES
75#include <asm/uaccess.h>
76#include <asm/cpu/sq.h>
77#endif
78
79#ifndef PCI_DEVICE_ID_NEC_NEON250
80# define PCI_DEVICE_ID_NEC_NEON250 0x0067
81#endif
82
83/* 2D video registers */
84#define DISP_BASE par->mmio_base
85#define DISP_BRDRCOLR (DISP_BASE + 0x40)
86#define DISP_DIWMODE (DISP_BASE + 0x44)
87#define DISP_DIWADDRL (DISP_BASE + 0x50)
88#define DISP_DIWADDRS (DISP_BASE + 0x54)
89#define DISP_DIWSIZE (DISP_BASE + 0x5c)
90#define DISP_SYNCCONF (DISP_BASE + 0xd0)
91#define DISP_BRDRHORZ (DISP_BASE + 0xd4)
92#define DISP_SYNCSIZE (DISP_BASE + 0xd8)
93#define DISP_BRDRVERT (DISP_BASE + 0xdc)
94#define DISP_DIWCONF (DISP_BASE + 0xe8)
95#define DISP_DIWHSTRT (DISP_BASE + 0xec)
96#define DISP_DIWVSTRT (DISP_BASE + 0xf0)
306c869c 97#define DISP_PIXDEPTH (DISP_BASE + 0x108)
1da177e4
LT		 98
99/* Pixel clocks, one for TV output, doubled for VGA output */
100#define TV_CLK 74239
101#define VGA_CLK 37119
102
103/* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
104#define PAL_HTOTAL 863
105#define PAL_VTOTAL 312
106#define NTSC_HTOTAL 857
107#define NTSC_VTOTAL 262
108
109/* Supported cable types */
110enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
111
112/* Supported video output types */
113enum { VO_PAL, VO_NTSC, VO_VGA };
114
115/* Supported palette types */
116enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
117
118struct pvr2_params { unsigned int val; char *name; };
7e7ec0d4 119static struct pvr2_params cables[] __devinitdata = {
1da177e4
LT		 120 { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
121};
122
7e7ec0d4 123static struct pvr2_params outputs[] __devinitdata = {
1da177e4
LT		 124 { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
125};
126
127/*
128 * This describes the current video mode
129 */
130
131static struct pvr2fb_par {
132 unsigned int hsync_total; /* Clocks/line */
133 unsigned int vsync_total; /* Lines/field */
134 unsigned int borderstart_h;
135 unsigned int borderstop_h;
136 unsigned int borderstart_v;
137 unsigned int borderstop_v;
138 unsigned int diwstart_h; /* Horizontal offset of the display field */
139 unsigned int diwstart_v; /* Vertical offset of the display field, for
140 interlaced modes, this is the long field */
141 unsigned long disp_start; /* Address of image within VRAM */
142 unsigned char is_interlaced; /* Is the display interlaced? */
143 unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
144 unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
145
146 unsigned long mmio_base; /* MMIO base */
9cd1c674 147 u32 palette[16];
1da177e4
LT		 148} *currentpar;
149
150static struct fb_info *fb_info;
151
e9705a77 152static struct fb_fix_screeninfo pvr2_fix __devinitdata = {
1da177e4 153 .id = "NEC PowerVR2",
e9705a77
PM		 154 .type = FB_TYPE_PACKED_PIXELS,
155 .visual = FB_VISUAL_TRUECOLOR,
1da177e4
LT		 156 .ypanstep = 1,
157 .ywrapstep = 1,
e9705a77 158 .accel = FB_ACCEL_NONE,
1da177e4
LT		 159};
160
e9705a77 161static struct fb_var_screeninfo pvr2_var __devinitdata = {
1da177e4
LT		 162 .xres = 640,
163 .yres = 480,
164 .xres_virtual = 640,
165 .yres_virtual = 480,
166 .bits_per_pixel =16,
167 .red = { 11, 5, 0 },
168 .green = { 5, 6, 0 },
169 .blue = { 0, 5, 0 },
170 .activate = FB_ACTIVATE_NOW,
171 .height = -1,
172 .width = -1,
173 .vmode = FB_VMODE_NONINTERLACED,
174};
175
176static int cable_type = CT_VGA;
177static int video_output = VO_VGA;
178
179static int nopan = 0;
180static int nowrap = 1;
181
182/*
183 * We do all updating, blanking, etc. during the vertical retrace period
184 */
185static unsigned int do_vmode_full = 0; /* Change the video mode */
186static unsigned int do_vmode_pan = 0; /* Update the video mode */
187static short do_blank = 0; /* (Un)Blank the screen */
188
189static unsigned int is_blanked = 0; /* Is the screen blanked? */
190
191#ifdef CONFIG_SH_STORE_QUEUES
d2b06a8b 192static unsigned long pvr2fb_map;
1da177e4
LT		 193#endif
194
195#ifdef CONFIG_SH_DMA
196static unsigned int shdma = PVR2_CASCADE_CHAN;
197static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
198#endif
199
1da177e4
LT		 200static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue,
201 unsigned int transp, struct fb_info *info);
202static int pvr2fb_blank(int blank, struct fb_info *info);
203static unsigned long get_line_length(int xres_virtual, int bpp);
204static void set_color_bitfields(struct fb_var_screeninfo *var);
205static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
206static int pvr2fb_set_par(struct fb_info *info);
207static void pvr2_update_display(struct fb_info *info);
208static void pvr2_init_display(struct fb_info *info);
209static void pvr2_do_blank(void);
7d12e780 210static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id);
1da177e4
LT		 211static int pvr2_init_cable(void);
212static int pvr2_get_param(const struct pvr2_params *p, const char *s,
213 int val, int size);
d2b06a8b 214#ifdef CONFIG_SH_DMA
3f9b0880 215static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
1da177e4 216 size_t count, loff_t *ppos);
d2b06a8b 217#endif
1da177e4
LT		 218
219static struct fb_ops pvr2fb_ops = {
d2b06a8b
PM		 220 .owner = THIS_MODULE,
221 .fb_setcolreg = pvr2fb_setcolreg,
222 .fb_blank = pvr2fb_blank,
223 .fb_check_var = pvr2fb_check_var,
224 .fb_set_par = pvr2fb_set_par,
1da177e4
LT		 225#ifdef CONFIG_SH_DMA
226 .fb_write = pvr2fb_write,
227#endif
e9705a77 228 .fb_fillrect = cfb_fillrect,
1da177e4
LT		 229 .fb_copyarea = cfb_copyarea,
230 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 231};
232
7e7ec0d4 233static struct fb_videomode pvr2_modedb[] __devinitdata = {
1da177e4
LT		 234 /*
235 * Broadcast video modes (PAL and NTSC). I'm unfamiliar with
236 * PAL-M and PAL-N, but from what I've read both modes parallel PAL and
237 * NTSC, so it shouldn't be a problem (I hope).
238 */
239
240 {
241 /* 640x480 @ 60Hz interlaced (NTSC) */
242 "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
243 FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
244 }, {
245 /* 640x240 @ 60Hz (NTSC) */
246 /* XXX: Broken! Don't use... */
247 "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
248 FB_SYNC_BROADCAST, FB_VMODE_YWRAP
249 }, {
250 /* 640x480 @ 60hz (VGA) */
251 "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
252 0, FB_VMODE_YWRAP
e9705a77 253 },
1da177e4
LT		 254};
255
256#define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
257
258#define DEFMODE_NTSC 0
259#define DEFMODE_PAL 0
260#define DEFMODE_VGA 2
261
262static int defmode = DEFMODE_NTSC;
7e7ec0d4 263static char *mode_option __devinitdata = NULL;
1da177e4
LT		 264
265static inline void pvr2fb_set_pal_type(unsigned int type)
266{
267 struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
268
269 fb_writel(type, par->mmio_base + 0x108);
270}
271
272static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
273 unsigned int regno,
274 unsigned int val)
275{
276 fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
277}
278
279static int pvr2fb_blank(int blank, struct fb_info *info)
280{
281 do_blank = blank ? blank : -1;
282 return 0;
283}
284
285static inline unsigned long get_line_length(int xres_virtual, int bpp)
286{
287 return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
288}
289
290static void set_color_bitfields(struct fb_var_screeninfo *var)
291{
292 switch (var->bits_per_pixel) {
293 case 16: /* RGB 565 */
e9705a77 294 pvr2fb_set_pal_type(PAL_RGB565);
1da177e4
LT		 295 var->red.offset = 11; var->red.length = 5;
296 var->green.offset = 5; var->green.length = 6;
297 var->blue.offset = 0; var->blue.length = 5;
298 var->transp.offset = 0; var->transp.length = 0;
299 break;
300 case 24: /* RGB 888 */
301 var->red.offset = 16; var->red.length = 8;
302 var->green.offset = 8; var->green.length = 8;
303 var->blue.offset = 0; var->blue.length = 8;
304 var->transp.offset = 0; var->transp.length = 0;
305 break;
306 case 32: /* ARGB 8888 */
e9705a77 307 pvr2fb_set_pal_type(PAL_ARGB8888);
1da177e4
LT		 308 var->red.offset = 16; var->red.length = 8;
309 var->green.offset = 8; var->green.length = 8;
310 var->blue.offset = 0; var->blue.length = 8;
311 var->transp.offset = 24; var->transp.length = 8;
312 break;
313 }
314}
315
316static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
317 unsigned int green, unsigned int blue,
318 unsigned int transp, struct fb_info *info)
319{
320 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
321 unsigned int tmp;
322
323 if (regno > info->cmap.len)
324 return 1;
325
326 /*
327 * We only support the hardware palette for 16 and 32bpp. It's also
328 * expected that the palette format has been set by the time we get
329 * here, so we don't waste time setting it again.
330 */
331 switch (info->var.bits_per_pixel) {
332 case 16: /* RGB 565 */
333 tmp = (red & 0xf800) |
334 ((green & 0xfc00) >> 5) |
335 ((blue & 0xf800) >> 11);
336
337 pvr2fb_set_pal_entry(par, regno, tmp);
1da177e4
LT		 338 break;
339 case 24: /* RGB 888 */
340 red >>= 8; green >>= 8; blue >>= 8;
a66ad56e 341 tmp = (red << 16) | (green << 8) | blue;
1da177e4
LT		 342 break;
343 case 32: /* ARGB 8888 */
344 red >>= 8; green >>= 8; blue >>= 8;
345 tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
346
347 pvr2fb_set_pal_entry(par, regno, tmp);
1da177e4
LT		 348 break;
349 default:
350 pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
351 return 1;
352 }
353
a66ad56e
AD		 354 if (regno < 16)
355 ((u32*)(info->pseudo_palette))[regno] = tmp;
356
1da177e4
LT		 357 return 0;
358}
359
360static int pvr2fb_set_par(struct fb_info *info)
361{
362 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
363 struct fb_var_screeninfo *var = &info->var;
364 unsigned long line_length;
365 unsigned int vtotal;
366
367 /*
368 * XXX: It's possible that a user could use a VGA box, change the cable
369 * type in hardware (i.e. switch from VGA<->composite), then change
370 * modes (i.e. switching to another VT). If that happens we should
371 * automagically change the output format to cope, but currently I
372 * don't have a VGA box to make sure this works properly.
373 */
374 cable_type = pvr2_init_cable();
375 if (cable_type == CT_VGA && video_output != VO_VGA)
376 video_output = VO_VGA;
377
378 var->vmode &= FB_VMODE_MASK;
379 if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
380 par->is_interlaced = 1;
e9705a77 381 /*
1da177e4
LT		 382 * XXX: Need to be more creative with this (i.e. allow doublecan for
383 * PAL/NTSC output).
384 */
385 if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
386 par->is_doublescan = 1;
e9705a77 387
1da177e4
LT		 388 par->hsync_total = var->left_margin + var->xres + var->right_margin +
389 var->hsync_len;
390 par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
391 var->vsync_len;
392
393 if (var->sync & FB_SYNC_BROADCAST) {
394 vtotal = par->vsync_total;
395 if (par->is_interlaced)
396 vtotal /= 2;
397 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
398 /* XXX: Check for start values here... */
399 /* XXX: Check hardware for PAL-compatibility */
400 par->borderstart_h = 116;
401 par->borderstart_v = 44;
402 } else {
403 /* NTSC video output */
404 par->borderstart_h = 126;
405 par->borderstart_v = 18;
406 }
407 } else {
408 /* VGA mode */
409 /* XXX: What else needs to be checked? */
e9705a77 410 /*
1da177e4
LT		 411 * XXX: We have a little freedom in VGA modes, what ranges
412 * should be here (i.e. hsync/vsync totals, etc.)?
413 */
414 par->borderstart_h = 126;
415 par->borderstart_v = 40;
416 }
417
418 /* Calculate the remainding offsets */
419 par->diwstart_h = par->borderstart_h + var->left_margin;
420 par->diwstart_v = par->borderstart_v + var->upper_margin;
e9705a77
PM		 421 par->borderstop_h = par->diwstart_h + var->xres +
422 var->right_margin;
1da177e4
LT		 423 par->borderstop_v = par->diwstart_v + var->yres +
424 var->lower_margin;
425
426 if (!par->is_interlaced)
427 par->borderstop_v /= 2;
428 if (info->var.xres < 640)
429 par->is_lowres = 1;
430
431 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
432 par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
433 info->fix.line_length = line_length;
434 return 0;
435}
436
437static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
438{
439 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
440 unsigned int vtotal, hsync_total;
441 unsigned long line_length;
442
443 if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
444 pr_debug("Invalid pixclock value %d\n", var->pixclock);
445 return -EINVAL;
446 }
447
448 if (var->xres < 320)
449 var->xres = 320;
450 if (var->yres < 240)
451 var->yres = 240;
452 if (var->xres_virtual < var->xres)
453 var->xres_virtual = var->xres;
454 if (var->yres_virtual < var->yres)
455 var->yres_virtual = var->yres;
456
457 if (var->bits_per_pixel <= 16)
458 var->bits_per_pixel = 16;
459 else if (var->bits_per_pixel <= 24)
460 var->bits_per_pixel = 24;
461 else if (var->bits_per_pixel <= 32)
462 var->bits_per_pixel = 32;
463
464 set_color_bitfields(var);
465
466 if (var->vmode & FB_VMODE_YWRAP) {
e9705a77 467 if (var->xoffset || var->yoffset < 0 ||
1da177e4
LT		 468 var->yoffset >= var->yres_virtual) {
469 var->xoffset = var->yoffset = 0;
470 } else {
471 if (var->xoffset > var->xres_virtual - var->xres ||
e9705a77 472 var->yoffset > var->yres_virtual - var->yres ||
1da177e4
LT		 473 var->xoffset < 0 || var->yoffset < 0)
474 var->xoffset = var->yoffset = 0;
475 }
476 } else {
477 var->xoffset = var->yoffset = 0;
478 }
479
e9705a77 480 /*
1da177e4
LT		 481 * XXX: Need to be more creative with this (i.e. allow doublecan for
482 * PAL/NTSC output).
483 */
484 if (var->yres < 480 && video_output == VO_VGA)
485 var->vmode |= FB_VMODE_DOUBLE;
486
487 if (video_output != VO_VGA) {
488 var->sync |= FB_SYNC_BROADCAST;
489 var->vmode |= FB_VMODE_INTERLACED;
490 } else {
491 var->sync &= ~FB_SYNC_BROADCAST;
492 var->vmode &= ~FB_VMODE_INTERLACED;
493 var->vmode |= pvr2_var.vmode;
494 }
495
496 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
497 var->right_margin = par->borderstop_h -
498 (par->diwstart_h + var->xres);
499 var->left_margin = par->diwstart_h - par->borderstart_h;
500 var->hsync_len = par->borderstart_h +
501 (par->hsync_total - par->borderstop_h);
502
503 var->upper_margin = par->diwstart_v - par->borderstart_v;
504 var->lower_margin = par->borderstop_v -
505 (par->diwstart_v + var->yres);
506 var->vsync_len = par->borderstop_v +
507 (par->vsync_total - par->borderstop_v);
508 }
e9705a77 509
1da177e4
LT		 510 hsync_total = var->left_margin + var->xres + var->right_margin +
511 var->hsync_len;
512 vtotal = var->upper_margin + var->yres + var->lower_margin +
513 var->vsync_len;
514
515 if (var->sync & FB_SYNC_BROADCAST) {
516 if (var->vmode & FB_VMODE_INTERLACED)
517 vtotal /= 2;
518 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
519 /* PAL video output */
520 /* XXX: Should be using a range here ... ? */
521 if (hsync_total != PAL_HTOTAL) {
522 pr_debug("invalid hsync total for PAL\n");
523 return -EINVAL;
524 }
525 } else {
526 /* NTSC video output */
527 if (hsync_total != NTSC_HTOTAL) {
528 pr_debug("invalid hsync total for NTSC\n");
529 return -EINVAL;
530 }
531 }
532 }
e9705a77 533
1da177e4
LT		 534 /* Check memory sizes */
535 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
536 if (line_length * var->yres_virtual > info->fix.smem_len)
537 return -ENOMEM;
538
539 return 0;
540}
541
542static void pvr2_update_display(struct fb_info *info)
543{
544 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
545 struct fb_var_screeninfo *var = &info->var;
546
547 /* Update the start address of the display image */
548 fb_writel(par->disp_start, DISP_DIWADDRL);
549 fb_writel(par->disp_start +
550 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
551 DISP_DIWADDRS);
552}
553
e9705a77 554/*
1da177e4
LT		 555 * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
556 * very stable. It's probably due to the fact that a lot of the 2D video
557 * registers are still undocumented.
558 */
559
560static void pvr2_init_display(struct fb_info *info)
561{
562 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
563 struct fb_var_screeninfo *var = &info->var;
564 unsigned int diw_height, diw_width, diw_modulo = 1;
565 unsigned int bytesperpixel = var->bits_per_pixel >> 3;
566
567 /* hsync and vsync totals */
568 fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
569
570 /* column height, modulo, row width */
571 /* since we're "panning" within vram, we need to offset things based
572 * on the offset from the virtual x start to our real gfx. */
573 if (video_output != VO_VGA && par->is_interlaced)
574 diw_modulo += info->fix.line_length / 4;
575 diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
576 diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
577 fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
578 DISP_DIWSIZE);
579
580 /* display address, long and short fields */
581 fb_writel(par->disp_start, DISP_DIWADDRL);
582 fb_writel(par->disp_start +
583 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
584 DISP_DIWADDRS);
585
586 /* border horizontal, border vertical, border color */
587 fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
588 fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
589 fb_writel(0, DISP_BRDRCOLR);
590
591 /* display window start position */
592 fb_writel(par->diwstart_h, DISP_DIWHSTRT);
593 fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
e9705a77 594
1da177e4
LT		 595 /* misc. settings */
596 fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
597
598 /* clock doubler (for VGA), scan doubler, display enable */
e9705a77 599 fb_writel(((video_output == VO_VGA) << 23) |
1da177e4
LT		 600 (par->is_doublescan << 1) | 1, DISP_DIWMODE);
601
602 /* bits per pixel */
603 fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
306c869c 604 fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);
1da177e4 605
e9705a77 606 /* video enable, color sync, interlace,
1da177e4
LT		 607 * hsync and vsync polarity (currently unused) */
608 fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
609}
610
611/* Simulate blanking by making the border cover the entire screen */
612
613#define BLANK_BIT (1<<3)
614
615static void pvr2_do_blank(void)
616{
617 struct pvr2fb_par *par = currentpar;
618 unsigned long diwconf;
619
620 diwconf = fb_readl(DISP_DIWCONF);
621 if (do_blank > 0)
622 fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
623 else
624 fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
625
626 is_blanked = do_blank > 0 ? do_blank : 0;
627}
628
7d12e780 629static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id)
1da177e4
LT		 630{
631 struct fb_info *info = dev_id;
632
633 if (do_vmode_pan || do_vmode_full)
634 pvr2_update_display(info);
635 if (do_vmode_full)
636 pvr2_init_display(info);
637 if (do_vmode_pan)
638 do_vmode_pan = 0;
639 if (do_vmode_full)
640 do_vmode_full = 0;
641 if (do_blank) {
642 pvr2_do_blank();
643 do_blank = 0;
644 }
645 return IRQ_HANDLED;
646}
647
648/*
649 * Determine the cable type and initialize the cable output format. Don't do
650 * anything if the cable type has been overidden (via "cable:XX").
651 */
652
653#define PCTRA 0xff80002c
654#define PDTRA 0xff800030
655#define VOUTC 0xa0702c00
656
657static int pvr2_init_cable(void)
658{
659 if (cable_type < 0) {
e9705a77 660 fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
1da177e4
LT		 661 PCTRA);
662 cable_type = (fb_readw(PDTRA) >> 8) & 3;
663 }
664
665 /* Now select the output format (either composite or other) */
666 /* XXX: Save the previous val first, as this reg is also AICA
667 related */
668 if (cable_type == CT_COMPOSITE)
669 fb_writel(3 << 8, VOUTC);
78d7e0e5
AM		 670 else if (cable_type == CT_RGB)
671 fb_writel(1 << 9, VOUTC);
1da177e4
LT		 672 else
673 fb_writel(0, VOUTC);
674
675 return cable_type;
676}
677
678#ifdef CONFIG_SH_DMA
3f9b0880 679static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
1da177e4
LT		 680 size_t count, loff_t *ppos)
681{
682 unsigned long dst, start, end, len;
683 unsigned int nr_pages;
684 struct page **pages;
685 int ret, i;
686
687 nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
688
689 pages = kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
690 if (!pages)
691 return -ENOMEM;
e9705a77 692
1da177e4
LT		 693 down_read(&current->mm->mmap_sem);
694 ret = get_user_pages(current, current->mm, (unsigned long)buf,
695 nr_pages, WRITE, 0, pages, NULL);
696 up_read(&current->mm->mmap_sem);
697
698 if (ret < nr_pages) {
699 nr_pages = ret;
700 ret = -EINVAL;
701 goto out_unmap;
702 }
703
704 dma_configure_channel(shdma, 0x12c1);
e9705a77 705
1da177e4
LT		 706 dst = (unsigned long)fb_info->screen_base + *ppos;
707 start = (unsigned long)page_address(pages[0]);
708 end = (unsigned long)page_address(pages[nr_pages]);
709 len = nr_pages << PAGE_SHIFT;
710
711 /* Half-assed contig check */
712 if (start + len == end) {
713 /* As we do this in one shot, it's either all or nothing.. */
714 if ((*ppos + len) > fb_info->fix.smem_len) {
715 ret = -ENOSPC;
716 goto out_unmap;
717 }
718
719 dma_write(shdma, start, 0, len);
720 dma_write(pvr2dma, 0, dst, len);
721 dma_wait_for_completion(pvr2dma);
722
723 goto out;
724 }
725
726 /* Not contiguous, writeout per-page instead.. */
727 for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
728 if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
729 ret = -ENOSPC;
730 goto out_unmap;
731 }
732
733 dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
734 dma_write_page(pvr2dma, 0, dst);
735 dma_wait_for_completion(pvr2dma);
736 }
737
738out:
739 *ppos += count;
740 ret = count;
741
742out_unmap:
743 for (i = 0; i < nr_pages; i++)
744 page_cache_release(pages[i]);
745
746 kfree(pages);
747
748 return ret;
e9705a77 749}
1da177e4
LT		 750#endif /* CONFIG_SH_DMA */
751
752/**
753 * pvr2fb_common_init
754 *
755 * Common init code for the PVR2 chips.
756 *
757 * This mostly takes care of the common aspects of the fb setup and
758 * registration. It's expected that the board-specific init code has
759 * already setup pvr2_fix with something meaningful at this point.
760 *
761 * Device info reporting is also done here, as well as picking a sane
762 * default from the modedb. For board-specific modelines, simply define
763 * a per-board modedb.
764 *
765 * Also worth noting is that the cable and video output types are likely
766 * always going to be VGA for the PCI-based PVR2 boards, but we leave this
767 * in for flexibility anyways. Who knows, maybe someone has tv-out on a
768 * PCI-based version of these things ;-)
769 */
7e7ec0d4 770static int __devinit pvr2fb_common_init(void)
1da177e4
LT		 771{
772 struct pvr2fb_par *par = currentpar;
773 unsigned long modememused, rev;
774
775 fb_info->screen_base = ioremap_nocache(pvr2_fix.smem_start,
776 pvr2_fix.smem_len);
e9705a77 777
1da177e4
LT		 778 if (!fb_info->screen_base) {
779 printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
780 goto out_err;
781 }
782
783 par->mmio_base = (unsigned long)ioremap_nocache(pvr2_fix.mmio_start,
e9705a77 784 pvr2_fix.mmio_len);
1da177e4
LT		 785 if (!par->mmio_base) {
786 printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
787 goto out_err;
788 }
789
d2b06a8b 790 fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
1da177e4
LT		 791
792 pvr2_fix.ypanstep = nopan ? 0 : 1;
793 pvr2_fix.ywrapstep = nowrap ? 0 : 1;
794
795 fb_info->fbops = &pvr2fb_ops;
796 fb_info->fix = pvr2_fix;
797 fb_info->par = currentpar;
9cd1c674 798 fb_info->pseudo_palette = currentpar->palette;
1da177e4
LT		 799 fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
800
801 if (video_output == VO_VGA)
802 defmode = DEFMODE_VGA;
803
804 if (!mode_option)
805 mode_option = "640x480@60";
806
807 if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
808 NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
809 fb_info->var = pvr2_var;
810
811 fb_alloc_cmap(&fb_info->cmap, 256, 0);
812
813 if (register_framebuffer(fb_info) < 0)
814 goto out_err;
306c869c
AM		 815 /*Must write PIXDEPTH to register before anything is displayed - so force init */
816 pvr2_init_display(fb_info);
1da177e4
LT		 817
818 modememused = get_line_length(fb_info->var.xres_virtual,
819 fb_info->var.bits_per_pixel);
820 modememused *= fb_info->var.yres_virtual;
821
822 rev = fb_readl(par->mmio_base + 0x04);
823
824 printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
825 fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
826 modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10));
e9705a77 827 printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
1da177e4 828 fb_info->node, fb_info->var.xres, fb_info->var.yres,
d2b06a8b 829 fb_info->var.bits_per_pixel,
1da177e4
LT		 830 get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
831 (char *)pvr2_get_param(cables, NULL, cable_type, 3),
832 (char *)pvr2_get_param(outputs, NULL, video_output, 3));
833
834#ifdef CONFIG_SH_STORE_QUEUES
835 printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node);
836
837 pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
d2b06a8b 838 fb_info->fix.id, pgprot_val(PAGE_SHARED));
1da177e4
LT		 839
840 printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n",
d2b06a8b 841 fb_info->node, pvr2fb_map);
1da177e4
LT		 842#endif
843
844 return 0;
845
846out_err:
847 if (fb_info->screen_base)
848 iounmap(fb_info->screen_base);
849 if (par->mmio_base)
850 iounmap((void *)par->mmio_base);
851
852 return -ENXIO;
853}
854
855#ifdef CONFIG_SH_DREAMCAST
856static int __init pvr2fb_dc_init(void)
857{
858 if (!mach_is_dreamcast())
859 return -ENXIO;
860
861 /* Make a guess at the monitor based on the attached cable */
862 if (pvr2_init_cable() == CT_VGA) {
863 fb_info->monspecs.hfmin = 30000;
864 fb_info->monspecs.hfmax = 70000;
865 fb_info->monspecs.vfmin = 60;
866 fb_info->monspecs.vfmax = 60;
867 } else {
868 /* Not VGA, using a TV (taken from acornfb) */
869 fb_info->monspecs.hfmin = 15469;
870 fb_info->monspecs.hfmax = 15781;
871 fb_info->monspecs.vfmin = 49;
872 fb_info->monspecs.vfmax = 51;
873 }
874
875 /*
876 * XXX: This needs to pull default video output via BIOS or other means
877 */
878 if (video_output < 0) {
879 if (cable_type == CT_VGA) {
880 video_output = VO_VGA;
881 } else {
882 video_output = VO_NTSC;
883 }
884 }
e9705a77
PM		 885
886 /*
1da177e4
LT		 887 * Nothing exciting about the DC PVR2 .. only a measly 8MiB.
888 */
889 pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
890 pvr2_fix.smem_len = 8 << 20;
891
892 pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
893 pvr2_fix.mmio_len = 0x2000;
894
123f5f18 895 if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, IRQF_SHARED,
1da177e4
LT		 896 "pvr2 VBL handler", fb_info)) {
897 return -EBUSY;
898 }
899
900#ifdef CONFIG_SH_DMA
901 if (request_dma(pvr2dma, "pvr2") != 0) {
902 free_irq(HW_EVENT_VSYNC, 0);
903 return -EBUSY;
904 }
905#endif
906
907 return pvr2fb_common_init();
908}
909
e9705a77 910static void __exit pvr2fb_dc_exit(void)
1da177e4 911{
295a1b47
AL		 912 if (fb_info->screen_base) {
913 iounmap(fb_info->screen_base);
914 fb_info->screen_base = NULL;
915 }
916 if (currentpar->mmio_base) {
917 iounmap((void *)currentpar->mmio_base);
918 currentpar->mmio_base = 0;
919 }
920
1da177e4
LT		 921 free_irq(HW_EVENT_VSYNC, 0);
922#ifdef CONFIG_SH_DMA
923 free_dma(pvr2dma);
924#endif
925}
926#endif /* CONFIG_SH_DREAMCAST */
927
928#ifdef CONFIG_PCI
929static int __devinit pvr2fb_pci_probe(struct pci_dev *pdev,
930 const struct pci_device_id *ent)
931{
932 int ret;
933
934 ret = pci_enable_device(pdev);
935 if (ret) {
936 printk(KERN_ERR "pvr2fb: PCI enable failed\n");
937 return ret;
938 }
939
940 ret = pci_request_regions(pdev, "pvr2fb");
941 if (ret) {
942 printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
943 return ret;
944 }
945
946 /*
947 * Slightly more exciting than the DC PVR2 .. 16MiB!
948 */
949 pvr2_fix.smem_start = pci_resource_start(pdev, 0);
950 pvr2_fix.smem_len = pci_resource_len(pdev, 0);
951
952 pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
953 pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
954
955 fb_info->device = &pdev->dev;
956
957 return pvr2fb_common_init();
958}
959
960static void __devexit pvr2fb_pci_remove(struct pci_dev *pdev)
961{
295a1b47
AL		 962 if (fb_info->screen_base) {
963 iounmap(fb_info->screen_base);
964 fb_info->screen_base = NULL;
965 }
966 if (currentpar->mmio_base) {
967 iounmap((void *)currentpar->mmio_base);
968 currentpar->mmio_base = 0;
969 }
970
1da177e4
LT		 971 pci_release_regions(pdev);
972}
973
974static struct pci_device_id pvr2fb_pci_tbl[] __devinitdata = {
975 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
976 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
977 { 0, },
978};
979
980MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
981
982static struct pci_driver pvr2fb_pci_driver = {
983 .name = "pvr2fb",
984 .id_table = pvr2fb_pci_tbl,
985 .probe = pvr2fb_pci_probe,
986 .remove = __devexit_p(pvr2fb_pci_remove),
987};
988
989static int __init pvr2fb_pci_init(void)
990{
991 return pci_register_driver(&pvr2fb_pci_driver);
992}
993
e9705a77 994static void __exit pvr2fb_pci_exit(void)
1da177e4
LT		 995{
996 pci_unregister_driver(&pvr2fb_pci_driver);
997}
998#endif /* CONFIG_PCI */
999
7e7ec0d4 1000static int __devinit pvr2_get_param(const struct pvr2_params *p, const char *s,
1da177e4
LT		 1001 int val, int size)
1002{
1003 int i;
1004
1005 for (i = 0 ; i < size ; i++ ) {
1006 if (s != NULL) {
1007 if (!strnicmp(p[i].name, s, strlen(s)))
1008 return p[i].val;
1009 } else {
1010 if (p[i].val == val)
1011 return (int)p[i].name;
1012 }
1013 }
1014 return -1;
1015}
1016
1017/*
1018 * Parse command arguments. Supported arguments are:
1019 * inverse Use inverse color maps
1020 * cable:composite|rgb|vga Override the video cable type
1021 * output:NTSC|PAL|VGA Override the video output format
1022 *
1023 * <xres>x<yres>[-<bpp>][@<refresh>] or,
1024 * <name>[-<bpp>][@<refresh>] Startup using this video mode
1025 */
1026
1027#ifndef MODULE
e9705a77 1028static int __init pvr2fb_setup(char *options)
1da177e4
LT		 1029{
1030 char *this_opt;
1031 char cable_arg[80];
1032 char output_arg[80];
1033
1034 if (!options || !*options)
1035 return 0;
1036
1037 while ((this_opt = strsep(&options, ","))) {
1038 if (!*this_opt)
1039 continue;
1040 if (!strcmp(this_opt, "inverse")) {
1041 fb_invert_cmaps();
1042 } else if (!strncmp(this_opt, "cable:", 6)) {
1043 strcpy(cable_arg, this_opt + 6);
1044 } else if (!strncmp(this_opt, "output:", 7)) {
1045 strcpy(output_arg, this_opt + 7);
1046 } else if (!strncmp(this_opt, "nopan", 5)) {
1047 nopan = 1;
1048 } else if (!strncmp(this_opt, "nowrap", 6)) {
1049 nowrap = 1;
1050 } else {
1051 mode_option = this_opt;
1052 }
1053 }
1054
1055 if (*cable_arg)
1056 cable_type = pvr2_get_param(cables, cable_arg, 0, 3);
1057 if (*output_arg)
1058 video_output = pvr2_get_param(outputs, output_arg, 0, 3);
1059
1060 return 0;
1061}
1062#endif
1063
1064static struct pvr2_board {
1065 int (*init)(void);
1066 void (*exit)(void);
1067 char name[16];
e9705a77 1068} board_driver[] = {
1da177e4
LT		 1069#ifdef CONFIG_SH_DREAMCAST
1070 { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
1071#endif
1072#ifdef CONFIG_PCI
1073 { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
1074#endif
1075 { 0, },
1076};
1077
e9705a77 1078static int __init pvr2fb_init(void)
1da177e4
LT		 1079{
1080 int i, ret = -ENODEV;
1081 int size;
1082
1083#ifndef MODULE
1084 char *option = NULL;
1085
1086 if (fb_get_options("pvr2fb", &option))
1087 return -ENODEV;
1088 pvr2fb_setup(option);
1089#endif
1090 size = sizeof(struct fb_info) + sizeof(struct pvr2fb_par) + 16 * sizeof(u32);
1091
9cd1c674
AD		 1092 fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
1093
1da177e4
LT		 1094 if (!fb_info) {
1095 printk(KERN_ERR "Failed to allocate memory for fb_info\n");
1096 return -ENOMEM;
1097 }
1098
1da177e4 1099
9cd1c674 1100 currentpar = fb_info->par;
1da177e4 1101
e9705a77
PM		 1102 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1103 struct pvr2_board *pvr_board = board_driver + i;
1da177e4
LT		 1104
1105 if (!pvr_board->init)
1106 continue;
1107
1108 ret = pvr_board->init();
1109
1110 if (ret != 0) {
1111 printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
1112 pvr_board->name);
9cd1c674 1113 framebuffer_release(fb_info);
1da177e4
LT		 1114 break;
1115 }
1116 }
1117
1118 return ret;
1119}
1120
1121static void __exit pvr2fb_exit(void)
1122{
1123 int i;
1124
e9705a77
PM		 1125 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1126 struct pvr2_board *pvr_board = board_driver + i;
1da177e4
LT		 1127
1128 if (pvr_board->exit)
1129 pvr_board->exit();
1130 }
e9705a77 1131
1da177e4
LT		 1132#ifdef CONFIG_SH_STORE_QUEUES
1133 sq_unmap(pvr2fb_map);
1134#endif
1135
1136 unregister_framebuffer(fb_info);
9cd1c674 1137 framebuffer_release(fb_info);
1da177e4
LT		 1138}
1139
1140module_init(pvr2fb_init);
1141module_exit(pvr2fb_exit);
1142
1143MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
1144MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
1145MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)