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Staging: add rtl8187se driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / rtl8187se / r8185b_init.c
CommitLineData
c8d86be3
GKH		 1/*++
2Copyright (c) Realtek Semiconductor Corp. All rights reserved.
3
4Module Name:
5 r8185b_init.c
6
7Abstract:
8 Hardware Initialization and Hardware IO for RTL8185B
9
10Major Change History:
11 When Who What
12 ---------- --------------- -------------------------------
13 2006-11-15 Xiong Created
14
15Notes:
16 This file is ported from RTL8185B Windows driver.
17
18
19--*/
20
21/*--------------------------Include File------------------------------------*/
22#include <linux/spinlock.h>
23#include "r8180_hw.h"
24#include "r8180.h"
25#include "r8180_sa2400.h" /* PHILIPS Radio frontend */
26#include "r8180_max2820.h" /* MAXIM Radio frontend */
27#include "r8180_gct.h" /* GCT Radio frontend */
28#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
29#include "r8180_rtl8255.h" /* RTL8255 Radio frontend */
30#include "r8180_93cx6.h" /* Card EEPROM */
31#include "r8180_wx.h"
32
33#ifdef CONFIG_RTL8180_PM
34#include "r8180_pm.h"
35#endif
36
37#ifdef ENABLE_DOT11D
38#include "dot11d.h"
39#endif
40
41#ifdef CONFIG_RTL8185B
42
43//#define CONFIG_RTL8180_IO_MAP
44
45#define TC_3W_POLL_MAX_TRY_CNT 5
46#ifdef CONFIG_RTL818X_S
47static u8 MAC_REG_TABLE[][2]={
48 //PAGA 0:
49 // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
50 // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
51 // 0x1F0~0x1F8 set in MacConfig_85BASIC()
52 {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
53 {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
54 {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
55 {0x94, 0x0F}, {0x95, 0x32},
56 {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
57 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
58 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
59 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
60 {0xff, 0x00},
61
62 //PAGE 1:
63 // For Flextronics system Logo PCIHCT failure:
64 // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
65 {0x5e, 0x01},
66 {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
67 {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
68 {0x82, 0xFF}, {0x83, 0x03},
69 {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
70 {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
71 {0xe2, 0x00},
72
73
74 //PAGE 2:
75 {0x5e, 0x02},
76 {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
77 {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
78 {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
79 {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
80 {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
81 {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
82 {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
83
84 //PAGA 0:
85 {0x5e, 0x00},{0x9f, 0x03}
86 };
87
88
89static u8 ZEBRA_AGC[]={
90 0,
91 0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
92 0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
93 0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
94 0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
95 0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
96 0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
97 0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
98 0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
99 };
100
101static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
102 0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
103 0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
104 0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
105 0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
106 0x0183,0x0163,0x0143,0x0123,0x0103
107 };
108
109static u8 OFDM_CONFIG[]={
110 // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
111 // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
112 // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
113
114 // 0x00
115 0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
116 0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
117 // 0x10
118 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
119 0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
120 // 0x20
121 0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
122 0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
123 // 0x30
124 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
125 0xD8, 0x3C, 0x7B, 0x10, 0x10
126 };
127#else
128 static u8 MAC_REG_TABLE[][2]={
129 //PAGA 0:
130 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
131 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
132 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
133 {0xff, 0x00},
134
135 //PAGE 1:
136 {0x5e, 0x01},
137 {0x58, 0x4b}, {0x59, 0x00}, {0x5a, 0x4b}, {0x5b, 0x00}, {0x60, 0x4b},
138 {0x61, 0x09}, {0x62, 0x4b}, {0x63, 0x09}, {0xce, 0x0f}, {0xcf, 0x00},
139 {0xe0, 0xff}, {0xe1, 0x0f}, {0xe2, 0x00}, {0xf0, 0x4e}, {0xf1, 0x01},
140 {0xf2, 0x02}, {0xf3, 0x03}, {0xf4, 0x04}, {0xf5, 0x05}, {0xf6, 0x06},
141 {0xf7, 0x07}, {0xf8, 0x08},
142
143
144 //PAGE 2:
145 {0x5e, 0x02},
146 {0x0c, 0x04}, {0x21, 0x61}, {0x22, 0x68}, {0x23, 0x6f}, {0x24, 0x76},
147 {0x25, 0x7d}, {0x26, 0x84}, {0x27, 0x8d}, {0x4d, 0x08}, {0x4e, 0x00},
148 {0x50, 0x05}, {0x51, 0xf5}, {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0x1f},
149 {0x55, 0x23}, {0x56, 0x45}, {0x57, 0x67}, {0x58, 0x08}, {0x59, 0x08},
150 {0x5a, 0x08}, {0x5b, 0x08}, {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08},
151 {0x63, 0x08}, {0x64, 0xcf}, {0x72, 0x56}, {0x73, 0x9a},
152
153 //PAGA 0:
154 {0x5e, 0x00},
155 {0x34, 0xff}, {0x35, 0x0f}, {0x5b, 0x40}, {0x84, 0x88}, {0x85, 0x24},
156 {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x07}, {0x8d, 0x00}, {0x94, 0x1b},
157 {0x95, 0x12}, {0x96, 0x00}, {0x97, 0x06}, {0x9d, 0x1a}, {0x9f, 0x10},
158 {0xb4, 0x22}, {0xbe, 0x80}, {0xdb, 0x00}, {0xee, 0x00}, {0x5b, 0x42},
159 {0x91, 0x03},
160
161 //PAGE 2:
162 {0x5e, 0x02},
163 {0x4c, 0x03},
164
165 //PAGE 0:
166 {0x5e, 0x00},
167
168 //PAGE 3:
169 {0x5e, 0x03},
170 {0x9f, 0x00},
171
172 //PAGE 0:
173 {0x5e, 0x00},
174 {0x8c, 0x01}, {0x8d, 0x10},{0x8e, 0x08}, {0x8f, 0x00}
175 };
176
177
178static u8 ZEBRA_AGC[]={
179 0,
180 0x5e,0x5e,0x5e,0x5e,0x5d,0x5b,0x59,0x57,0x55,0x53,0x51,0x4f,0x4d,0x4b,0x49,0x47,
181 0x45,0x43,0x41,0x3f,0x3d,0x3b,0x39,0x37,0x35,0x33,0x31,0x2f,0x2d,0x2b,0x29,0x27,
182 0x25,0x23,0x21,0x1f,0x1d,0x1b,0x19,0x17,0x15,0x13,0x11,0x0f,0x0d,0x0b,0x09,0x07,
183 0x05,0x03,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
184 0x19,0x19,0x19,0x019,0x19,0x19,0x19,0x19,0x19,0x19,0x1e,0x1f,0x20,0x21,0x21,0x22,
185 0x23,0x24,0x24,0x25,0x25,0x26,0x26,0x27,0x27,0x28,0x28,0x28,0x29,0x2a,0x2a,0x2b,
186 0x2b,0x2b,0x2c,0x2c,0x2c,0x2d,0x2d,0x2d,0x2e,0x2e,0x2f,0x30,0x31,0x31,0x31,0x31,
187 0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31
188 };
189
190static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
191 0,
192 0x0400,0x0401,0x0402,0x0403,0x0404,0x0405,0x0408,0x0409,
193 0x040a,0x040b,0x0502,0x0503,0x0504,0x0505,0x0540,0x0541,
194 0x0542,0x0543,0x0544,0x0545,0x0580,0x0581,0x0582,0x0583,
195 0x0584,0x0585,0x0588,0x0589,0x058a,0x058b,0x0643,0x0644,
196 0x0645,0x0680,0x0681,0x0682,0x0683,0x0684,0x0685,0x0688,
197 0x0689,0x068a,0x068b,0x068c,0x0742,0x0743,0x0744,0x0745,
198 0x0780,0x0781,0x0782,0x0783,0x0784,0x0785,0x0788,0x0789,
199 0x078a,0x078b,0x078c,0x078d,0x0790,0x0791,0x0792,0x0793,
200 0x0794,0x0795,0x0798,0x0799,0x079a,0x079b,0x079c,0x079d,
201 0x07a0,0x07a1,0x07a2,0x07a3,0x07a4,0x07a5,0x07a8,0x07a9,
202 0x03aa,0x03ab,0x03ac,0x03ad,0x03b0,0x03b1,0x03b2,0x03b3,
203 0x03b4,0x03b5,0x03b8,0x03b9,0x03ba,0x03bb,0x03bb
204};
205
206// 2006.07.13, SD3 szuyitasi:
207// OFDM.0x03=0x0C (original is 0x0F)
208// Use the new SD3 given param, by shien chang, 2006.07.14
209static u8 OFDM_CONFIG[]={
210 0x10, 0x0d, 0x01, 0x0C, 0x14, 0xfb, 0x0f, 0x60, 0x00, 0x60,
211 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00,
212 0x00, 0x00, 0xa8, 0x46, 0xb2, 0x33, 0x07, 0xa5, 0x6f, 0x55,
213 0xc8, 0xb3, 0x0a, 0xe1, 0x1c, 0x8a, 0xb6, 0x83, 0x34, 0x0f,
214 0x4f, 0x23, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 0xc0, 0xc1,
215 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 0x6d, 0x3c, 0xff, 0x07
216};
217#endif
218
219/*---------------------------------------------------------------
220 * Hardware IO
221 * the code is ported from Windows source code
222 ----------------------------------------------------------------*/
223
224void
225PlatformIOWrite1Byte(
226 struct net_device *dev,
227 u32 offset,
228 u8 data
229 )
230{
231#ifndef CONFIG_RTL8180_IO_MAP
232 write_nic_byte(dev, offset, data);
233 read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
234
235#else // Port IO
236 u32 Page = (offset >> 8);
237
238 switch(Page)
239 {
240 case 0: // Page 0
241 write_nic_byte(dev, offset, data);
242 break;
243
244 case 1: // Page 1
245 case 2: // Page 2
246 case 3: // Page 3
247 {
248 u8 psr = read_nic_byte(dev, PSR);
249
250 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
251 write_nic_byte(dev, (offset & 0xff), data);
252 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
253 }
254 break;
255
256 default:
257 // Illegal page number.
258 DMESGE("PlatformIOWrite1Byte(): illegal page number: %d, offset: %#X", Page, offset);
259 break;
260 }
261#endif
262}
263
264void
265PlatformIOWrite2Byte(
266 struct net_device *dev,
267 u32 offset,
268 u16 data
269 )
270{
271#ifndef CONFIG_RTL8180_IO_MAP
272 write_nic_word(dev, offset, data);
273 read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
274
275
276#else // Port IO
277 u32 Page = (offset >> 8);
278
279 switch(Page)
280 {
281 case 0: // Page 0
282 write_nic_word(dev, offset, data);
283 break;
284
285 case 1: // Page 1
286 case 2: // Page 2
287 case 3: // Page 3
288 {
289 u8 psr = read_nic_byte(dev, PSR);
290
291 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
292 write_nic_word(dev, (offset & 0xff), data);
293 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
294 }
295 break;
296
297 default:
298 // Illegal page number.
299 DMESGE("PlatformIOWrite2Byte(): illegal page number: %d, offset: %#X", Page, offset);
300 break;
301 }
302#endif
303}
304u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
305
306void
307PlatformIOWrite4Byte(
308 struct net_device *dev,
309 u32 offset,
310 u32 data
311 )
312{
313#ifndef CONFIG_RTL8180_IO_MAP
314//{by amy 080312
315if (offset == PhyAddr)
316 {//For Base Band configuration.
317 unsigned char cmdByte;
318 unsigned long dataBytes;
319 unsigned char idx;
320 u8 u1bTmp;
321
322 cmdByte = (u8)(data & 0x000000ff);
323 dataBytes = data>>8;
324
325 //
326 // 071010, rcnjko:
327 // The critical section is only BB read/write race condition.
328 // Assumption:
329 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
330 // acquiring the spinlock in such context.
331 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
332 //
333// NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
334
335 for(idx = 0; idx < 30; idx++)
336 { // Make sure command bit is clear before access it.
337 u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
338 if((u1bTmp & BIT7) == 0)
339 break;
340 else
341 mdelay(10);
342 }
343
344 for(idx=0; idx < 3; idx++)
345 {
346 PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
347 }
348 write_nic_byte(dev, offset, cmdByte);
349
350// NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
351 }
352//by amy 080312}
353 else{
354 write_nic_dword(dev, offset, data);
355 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
356 }
357#else // Port IO
358 u32 Page = (offset >> 8);
359
360 switch(Page)
361 {
362 case 0: // Page 0
363 write_nic_word(dev, offset, data);
364 break;
365
366 case 1: // Page 1
367 case 2: // Page 2
368 case 3: // Page 3
369 {
370 u8 psr = read_nic_byte(dev, PSR);
371
372 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
373 write_nic_dword(dev, (offset & 0xff), data);
374 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
375 }
376 break;
377
378 default:
379 // Illegal page number.
380 DMESGE("PlatformIOWrite4Byte(): illegal page number: %d, offset: %#X", Page, offset);
381 break;
382 }
383#endif
384}
385
386u8
387PlatformIORead1Byte(
388 struct net_device *dev,
389 u32 offset
390 )
391{
392 u8 data = 0;
393
394#ifndef CONFIG_RTL8180_IO_MAP
395 data = read_nic_byte(dev, offset);
396
397#else // Port IO
398 u32 Page = (offset >> 8);
399
400 switch(Page)
401 {
402 case 0: // Page 0
403 data = read_nic_byte(dev, offset);
404 break;
405
406 case 1: // Page 1
407 case 2: // Page 2
408 case 3: // Page 3
409 {
410 u8 psr = read_nic_byte(dev, PSR);
411
412 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
413 data = read_nic_byte(dev, (offset & 0xff));
414 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
415 }
416 break;
417
418 default:
419 // Illegal page number.
420 DMESGE("PlatformIORead1Byte(): illegal page number: %d, offset: %#X", Page, offset);
421 break;
422 }
423#endif
424
425 return data;
426}
427
428u16
429PlatformIORead2Byte(
430 struct net_device *dev,
431 u32 offset
432 )
433{
434 u16 data = 0;
435
436#ifndef CONFIG_RTL8180_IO_MAP
437 data = read_nic_word(dev, offset);
438
439#else // Port IO
440 u32 Page = (offset >> 8);
441
442 switch(Page)
443 {
444 case 0: // Page 0
445 data = read_nic_word(dev, offset);
446 break;
447
448 case 1: // Page 1
449 case 2: // Page 2
450 case 3: // Page 3
451 {
452 u8 psr = read_nic_byte(dev, PSR);
453
454 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
455 data = read_nic_word(dev, (offset & 0xff));
456 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
457 }
458 break;
459
460 default:
461 // Illegal page number.
462 DMESGE("PlatformIORead2Byte(): illegal page number: %d, offset: %#X", Page, offset);
463 break;
464 }
465#endif
466
467 return data;
468}
469
470u32
471PlatformIORead4Byte(
472 struct net_device *dev,
473 u32 offset
474 )
475{
476 u32 data = 0;
477
478#ifndef CONFIG_RTL8180_IO_MAP
479 data = read_nic_dword(dev, offset);
480
481#else // Port IO
482 u32 Page = (offset >> 8);
483
484 switch(Page)
485 {
486 case 0: // Page 0
487 data = read_nic_dword(dev, offset);
488 break;
489
490 case 1: // Page 1
491 case 2: // Page 2
492 case 3: // Page 3
493 {
494 u8 psr = read_nic_byte(dev, PSR);
495
496 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
497 data = read_nic_dword(dev, (offset & 0xff));
498 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
499 }
500 break;
501
502 default:
503 // Illegal page number.
504 DMESGE("PlatformIORead4Byte(): illegal page number: %d, offset: %#X\n", Page, offset);
505 break;
506 }
507#endif
508
509 return data;
510}
511
512void
513SetOutputEnableOfRfPins(
514 struct net_device *dev
515 )
516{
517 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
518
519 switch(priv->rf_chip)
520 {
521 case RFCHIPID_RTL8225:
522 case RF_ZEBRA2:
523 case RF_ZEBRA4:
524 write_nic_word(dev, RFPinsEnable, 0x1bff);
525 //write_nic_word(dev, RFPinsEnable, 0x1fff);
526 break;
527 }
528}
529
530void
531ZEBRA_RFSerialWrite(
532 struct net_device *dev,
533 u32 data2Write,
534 u8 totalLength,
535 u8 low2high
536 )
537{
538 ThreeWireReg twreg;
539 int i;
540 u16 oval,oval2,oval3;
541 u32 mask;
542 u16 UshortBuffer;
543
544 u8 u1bTmp;
545#ifdef CONFIG_RTL818X_S
546 // RTL8187S HSSI Read/Write Function
547 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
548 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
549 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
550#endif
551 UshortBuffer = read_nic_word(dev, RFPinsOutput);
552 oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
553
554 oval2 = read_nic_word(dev, RFPinsEnable);
555 oval3 = read_nic_word(dev, RFPinsSelect);
556
557 // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
558 oval3 &= 0xfff8;
559
560 write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
561 write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
562 udelay(10);
563
564 // Add this to avoid hardware and software 3-wire conflict.
565 // 2005.03.01, by rcnjko.
566 twreg.longData = 0;
567 twreg.struc.enableB = 1;
568 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
569 udelay(2);
570 twreg.struc.enableB = 0;
571 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
572 udelay(10);
573
574 mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
575
576 for(i=0; i<totalLength/2; i++)
577 {
578 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
579 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
580 twreg.struc.clk = 1;
581 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
582 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
583
584 mask = (low2high)?(mask<<1):(mask>>1);
585 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
586 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
587 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
588 twreg.struc.clk = 0;
589 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
590 mask = (low2high)?(mask<<1):(mask>>1);
591 }
592
593 twreg.struc.enableB = 1;
594 twreg.struc.clk = 0;
595 twreg.struc.data = 0;
596 write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
597 udelay(10);
598
599 write_nic_word(dev, RFPinsOutput, oval|0x0004);
600 write_nic_word(dev, RFPinsSelect, oval3|0x0000);
601
602 SetOutputEnableOfRfPins(dev);
603}
604//by amy
605
606
607int
608HwHSSIThreeWire(
609 struct net_device *dev,
610 u8 *pDataBuf,
611 u8 nDataBufBitCnt,
612 int bSI,
613 int bWrite
614 )
615{
616 int bResult = 1;
617 u8 TryCnt;
618 u8 u1bTmp;
619
620 do
621 {
622 // Check if WE and RE are cleared.
623 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
624 {
625 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
626 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
627 {
628 break;
629 }
630 udelay(10);
631 }
632 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
633 panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
634
635 // RTL8187S HSSI Read/Write Function
636 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
637
638 if(bSI)
639 {
640 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
641 }else
642 {
643 u1bTmp &= ~RF_SW_CFG_SI; //reg08[1]=0 Parallel Interface(PI)
644 }
645
646 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
647
648 if(bSI)
649 {
650 // jong: HW SI read must set reg84[3]=0.
651 u1bTmp = read_nic_byte(dev, RFPinsSelect);
652 u1bTmp &= ~BIT3;
653 write_nic_byte(dev, RFPinsSelect, u1bTmp );
654 }
655 // Fill up data buffer for write operation.
656
657 if(bWrite)
658 {
659 if(nDataBufBitCnt == 16)
660 {
661 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
662 }
663 else if(nDataBufBitCnt == 64) // RTL8187S shouldn't enter this case
664 {
665 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
666 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
667 }
668 else
669 {
670 int idx;
671 int ByteCnt = nDataBufBitCnt / 8;
672 //printk("%d\n",nDataBufBitCnt);
673 if ((nDataBufBitCnt % 8) != 0)
674 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
675 nDataBufBitCnt);
676
677 if (nDataBufBitCnt > 64)
678 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
679 nDataBufBitCnt);
680
681 for(idx = 0; idx < ByteCnt; idx++)
682 {
683 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
684 }
685 }
686 }
687 else //read
688 {
689 if(bSI)
690 {
691 // SI - reg274[3:0] : RF register's Address
692 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
693 }
694 else
695 {
696 // PI - reg274[15:12] : RF register's Address
697 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
698 }
699 }
700
701 // Set up command: WE or RE.
702 if(bWrite)
703 {
704 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
705 }
706 else
707 {
708 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
709 }
710
711 // Check if DONE is set.
712 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
713 {
714 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
715 if( (u1bTmp & SW_3W_CMD1_DONE) != 0 )
716 {
717 break;
718 }
719 udelay(10);
720 }
721
722 write_nic_byte(dev, SW_3W_CMD1, 0);
723
724 // Read back data for read operation.
725 if(bWrite == 0)
726 {
727 if(bSI)
728 {
729 //Serial Interface : reg363_362[11:0]
730 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
731 }
732 else
733 {
734 //Parallel Interface : reg361_360[11:0]
735 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
736 }
737
738 *((u16*)pDataBuf) &= 0x0FFF;
739 }
740
741 }while(0);
742
743 return bResult;
744}
745//by amy
746
747int
748HwThreeWire(
749 struct net_device *dev,
750 u8 *pDataBuf,
751 u8 nDataBufBitCnt,
752 int bHold,
753 int bWrite
754 )
755{
756 int bResult = 1;
757 u8 TryCnt;
758 u8 u1bTmp;
759
760 do
761 {
762 // Check if WE and RE are cleared.
763 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
764 {
765 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
766 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
767 {
768 break;
769 }
770 udelay(10);
771 }
772 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
773 panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
774
775 // Fill up data buffer for write operation.
776 if(nDataBufBitCnt == 16)
777 {
778 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
779 }
780 else if(nDataBufBitCnt == 64)
781 {
782 write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
783 write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
784 }
785 else
786 {
787 int idx;
788 int ByteCnt = nDataBufBitCnt / 8;
789
790 if ((nDataBufBitCnt % 8) != 0)
791 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
792 nDataBufBitCnt);
793
794 if (nDataBufBitCnt > 64)
795 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
796 nDataBufBitCnt);
797
798 for(idx = 0; idx < ByteCnt; idx++)
799 {
800 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
801 }
802 }
803
804 // Fill up length field.
805 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
806 if(bHold)
807 u1bTmp |= SW_3W_CMD0_HOLD;
808 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
809
810 // Set up command: WE or RE.
811 if(bWrite)
812 {
813 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
814 }
815 else
816 {
817 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
818 }
819
820 // Check if WE and RE are cleared and DONE is set.
821 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
822 {
823 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
824 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
825 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
826 {
827 break;
828 }
829 udelay(10);
830 }
831 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
832 {
833 //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
834 // ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
835 // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
836 write_nic_byte(dev, SW_3W_CMD1, 0);
837 }
838
839 // Read back data for read operation.
840 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
841 if(bWrite == 0)
842 {
843 if(nDataBufBitCnt == 16)
844 {
845 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
846 }
847 else if(nDataBufBitCnt == 64)
848 {
849 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
850 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
851 }
852 else
853 {
854 int idx;
855 int ByteCnt = nDataBufBitCnt / 8;
856
857 if ((nDataBufBitCnt % 8) != 0)
858 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
859 nDataBufBitCnt);
860
861 if (nDataBufBitCnt > 64)
862 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
863 nDataBufBitCnt);
864
865 for(idx = 0; idx < ByteCnt; idx++)
866 {
867 *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
868 }
869 }
870 }
871
872 }while(0);
873
874 return bResult;
875}
876
877
878void
879RF_WriteReg(
880 struct net_device *dev,
881 u8 offset,
882 u32 data
883 )
884{
885 //RFReg reg;
886 u32 data2Write;
887 u8 len;
888 u8 low2high;
889 //u32 RF_Read = 0;
890 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
891
892
893 switch(priv->rf_chip)
894 {
895 case RFCHIPID_RTL8225:
896 case RF_ZEBRA2: // Annie 2006-05-12.
897 case RF_ZEBRA4: //by amy
898 switch(priv->RegThreeWireMode)
899 {
900 case SW_THREE_WIRE:
901 { // Perform SW 3-wire programming by driver.
902 data2Write = (data << 4) | (u32)(offset & 0x0f);
903 len = 16;
904 low2high = 0;
905 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
906 }
907 break;
908
909 case HW_THREE_WIRE:
910 { // Pure HW 3-wire.
911 data2Write = (data << 4) | (u32)(offset & 0x0f);
912 len = 16;
913 HwThreeWire(
914 dev,
915 (u8 *)(&data2Write), // pDataBuf,
916 len, // nDataBufBitCnt,
917 0, // bHold,
918 1); // bWrite
919 }
920 break;
921 #ifdef CONFIG_RTL818X_S
922 case HW_THREE_WIRE_PI: //Parallel Interface
923 { // Pure HW 3-wire.
924 data2Write = (data << 4) | (u32)(offset & 0x0f);
925 len = 16;
926 HwHSSIThreeWire(
927 dev,
928 (u8*)(&data2Write), // pDataBuf,
929 len, // nDataBufBitCnt,
930 0, // bSI
931 1); // bWrite
932
933 //printk("33333\n");
934 }
935 break;
936
937 case HW_THREE_WIRE_SI: //Serial Interface
938 { // Pure HW 3-wire.
939 data2Write = (data << 4) | (u32)(offset & 0x0f);
940 len = 16;
941// printk(" enter ZEBRA_RFSerialWrite\n ");
942// low2high = 0;
943// ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
944
945 HwHSSIThreeWire(
946 dev,
947 (u8*)(&data2Write), // pDataBuf,
948 len, // nDataBufBitCnt,
949 1, // bSI
950 1); // bWrite
951
952// printk(" exit ZEBRA_RFSerialWrite\n ");
953 }
954 break;
955 #endif
956
957
958 default:
959 DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
960 break;
961 }
962 break;
963
964 default:
965 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
966 break;
967 }
968}
969
970
971void
972ZEBRA_RFSerialRead(
973 struct net_device *dev,
974 u32 data2Write,
975 u8 wLength,
976 u32 *data2Read,
977 u8 rLength,
978 u8 low2high
979 )
980{
981 ThreeWireReg twreg;
982 int i;
983 u16 oval,oval2,oval3,tmp, wReg80;
984 u32 mask;
985 u8 u1bTmp;
986 ThreeWireReg tdata;
987 //PHAL_DATA_8187 pHalData = GetHalData8187(pAdapter);
988#ifdef CONFIG_RTL818X_S
989 { // RTL8187S HSSI Read/Write Function
990 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
991 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
992 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
993 }
994#endif
995
996 wReg80 = oval = read_nic_word(dev, RFPinsOutput);
997 oval2 = read_nic_word(dev, RFPinsEnable);
998 oval3 = read_nic_word(dev, RFPinsSelect);
999
1000 write_nic_word(dev, RFPinsEnable, oval2|0xf);
1001 write_nic_word(dev, RFPinsSelect, oval3|0xf);
1002
1003 *data2Read = 0;
1004
1005 // We must clear BIT0-3 here, otherwise,
1006 // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
1007 // which will cause the value read become 0. 2005.04.11, by rcnjko.
1008 oval &= ~0xf;
1009
1010 // Avoid collision with hardware three-wire.
1011 twreg.longData = 0;
1012 twreg.struc.enableB = 1;
1013 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
1014
1015 twreg.longData = 0;
1016 twreg.struc.enableB = 0;
1017 twreg.struc.clk = 0;
1018 twreg.struc.read_write = 0;
1019 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
1020
1021 mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
1022 for(i = 0; i < wLength/2; i++)
1023 {
1024 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
1025 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1026 twreg.struc.clk = 1;
1027 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1028 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1029
1030 mask = (low2high) ? (mask<<1): (mask>>1);
1031
1032 if(i == 2)
1033 {
1034 // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
1035 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe); // turn off data enable
1036 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
1037
1038 twreg.struc.read_write=1;
1039 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1040 twreg.struc.clk = 0;
1041 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1042 break;
1043 }
1044 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
1045 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1046 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1047
1048 twreg.struc.clk = 0;
1049 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1050
1051 mask = (low2high) ? (mask<<1) : (mask>>1);
1052 }
1053
1054 twreg.struc.clk = 0;
1055 twreg.struc.data = 0;
1056 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1057 mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
1058
1059 //
1060 // 061016, by rcnjko:
1061 // We must set data pin to HW controled, otherwise RF can't driver it and
1062 // value RF register won't be able to read back properly.
1063 //
1064 write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
1065
1066 for(i = 0; i < rLength; i++)
1067 {
1068 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1069 twreg.struc.clk = 1;
1070 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1071 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1072 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1073 tmp = read_nic_word(dev, RFPinsInput);
1074 tdata.longData = tmp;
1075 *data2Read |= tdata.struc.clk ? mask : 0;
1076
1077 twreg.struc.clk = 0;
1078 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1079
1080 mask = (low2high) ? (mask<<1) : (mask>>1);
1081 }
1082 twreg.struc.enableB = 1;
1083 twreg.struc.clk = 0;
1084 twreg.struc.data = 0;
1085 twreg.struc.read_write = 1;
1086 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1087
1088 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8); // Set To Output Enable
1089 write_nic_word(dev, RFPinsEnable, oval2); // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
1090 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
1091 write_nic_word(dev, RFPinsSelect, oval3); // Set To SW Switch
1092 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
1093 write_nic_word(dev, RFPinsOutput, 0x3a0);
1094 //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
1095}
1096
1097
1098u32
1099RF_ReadReg(
1100 struct net_device *dev,
1101 u8 offset
1102 )
1103{
1104 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1105 u32 data2Write;
1106 u8 wlen;
1107 u8 rlen;
1108 u8 low2high;
1109 u32 dataRead;
1110
1111 switch(priv->rf_chip)
1112 {
1113 case RFCHIPID_RTL8225:
1114 case RF_ZEBRA2:
1115 case RF_ZEBRA4:
1116 switch(priv->RegThreeWireMode)
1117 {
1118#ifdef CONFIG_RTL818X_S
1119 case HW_THREE_WIRE_PI: // For 87S Parallel Interface.
1120 {
1121 data2Write = ((u32)(offset&0x0f));
1122 wlen=16;
1123 HwHSSIThreeWire(
1124 dev,
1125 (u8*)(&data2Write), // pDataBuf,
1126 wlen, // nDataBufBitCnt,
1127 0, // bSI
1128 0); // bWrite
1129 dataRead= data2Write;
1130 }
1131 break;
1132
1133 case HW_THREE_WIRE_SI: // For 87S Serial Interface.
1134 {
1135 data2Write = ((u32)(offset&0x0f)) ;
1136 wlen=16;
1137 HwHSSIThreeWire(
1138 dev,
1139 (u8*)(&data2Write), // pDataBuf,
1140 wlen, // nDataBufBitCnt,
1141 1, // bSI
1142 0 // bWrite
1143 );
1144 dataRead= data2Write;
1145 }
1146 break;
1147
1148#endif
1149 // Perform SW 3-wire programming by driver.
1150 default:
1151 {
1152 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
1153 wlen = 6;
1154 rlen = 12;
1155 low2high = 0;
1156 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
1157 }
1158 break;
1159 }
1160 break;
1161 default:
1162 dataRead = 0;
1163 break;
1164 }
1165
1166 return dataRead;
1167}
1168
1169
1170// by Owen on 04/07/14 for writing BB register successfully
1171void
1172WriteBBPortUchar(
1173 struct net_device *dev,
1174 u32 Data
1175 )
1176{
1177 //u8 TimeoutCounter;
1178 u8 RegisterContent;
1179 u8 UCharData;
1180
1181 UCharData = (u8)((Data & 0x0000ff00) >> 8);
1182 PlatformIOWrite4Byte(dev, PhyAddr, Data);
1183 //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
1184 {
1185 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
1186 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1187 //if(UCharData == RegisterContent)
1188 // break;
1189 }
1190}
1191
1192u8
1193ReadBBPortUchar(
1194 struct net_device *dev,
1195 u32 addr
1196 )
1197{
1198 //u8 TimeoutCounter;
1199 u8 RegisterContent;
1200
1201 PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
1202 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1203
1204 return RegisterContent;
1205}
1206//{by amy 080312
1207#ifdef CONFIG_RTL818X_S
1208//
1209// Description:
1210// Perform Antenna settings with antenna diversity on 87SE.
1211// Created by Roger, 2008.01.25.
1212//
1213bool
1214SetAntennaConfig87SE(
1215 struct net_device *dev,
1216 u8 DefaultAnt, // 0: Main, 1: Aux.
1217 bool bAntDiversity // 1:Enable, 0: Disable.
1218)
1219{
1220 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1221 bool bAntennaSwitched = true;
1222
1223 //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
1224
1225 // Threshold for antenna diversity.
1226 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1227
1228 if( bAntDiversity ) // Enable Antenna Diversity.
1229 {
1230 if( DefaultAnt == 1 ) // aux antenna
1231 {
1232 // Mac register, aux antenna
1233 write_nic_byte(dev, ANTSEL, 0x00);
1234
1235 // Config CCK RX antenna.
1236 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1237 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1238
1239 // Config OFDM RX antenna.
1240 write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54
1241 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
1242 }
1243 else // use main antenna
1244 {
1245 // Mac register, main antenna
1246 write_nic_byte(dev, ANTSEL, 0x03);
1247 //base band
1248 // Config CCK RX antenna.
1249 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1250 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1251
1252 // Config OFDM RX antenna.
1253 write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c
1254 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
1255 }
1256 }
1257 else // Disable Antenna Diversity.
1258 {
1259 if( DefaultAnt == 1 ) // aux Antenna
1260 {
1261 // Mac register, aux antenna
1262 write_nic_byte(dev, ANTSEL, 0x00);
1263
1264 // Config CCK RX antenna.
1265 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1266 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1267
1268 // Config OFDM RX antenna.
1269 write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54
1270 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1271 }
1272 else // main Antenna
1273 {
1274 // Mac register, main antenna
1275 write_nic_byte(dev, ANTSEL, 0x03);
1276
1277 // Config CCK RX antenna.
1278 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1279 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1280
1281 // Config OFDM RX antenna.
1282 write_phy_ofdm(dev, 0x0D, 0x5c); // Reg0d : 5c
1283 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1284 }
1285 }
1286 priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1287 return bAntennaSwitched;
1288}
1289#endif
1290//by amy 080312
1291/*---------------------------------------------------------------
1292 * Hardware Initialization.
1293 * the code is ported from Windows source code
1294 ----------------------------------------------------------------*/
1295
1296void
1297ZEBRA_Config_85BASIC_HardCode(
1298 struct net_device *dev
1299 )
1300{
1301
1302 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1303 u32 i;
1304 u32 addr,data;
1305 u32 u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1306 u8 u1b24E;
1307
1308#ifdef CONFIG_RTL818X_S
1309
1310 //=============================================================================
1311 // 87S_PCIE :: RADIOCFG.TXT
1312 //=============================================================================
1313
1314
1315 // Page1 : reg16-reg30
1316 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); // switch to page1
1317 u4bRF23= RF_ReadReg(dev, 0x08); mdelay(1);
1318 u4bRF24= RF_ReadReg(dev, 0x09); mdelay(1);
1319
1320 if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1321 priv->card_8185 = VERSION_8187S_D;
1322
1323 // Page0 : reg0-reg15
1324
1325// RF_WriteReg(dev, 0x00, 0x003f); mdelay(1);//1
1326 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);// 1
1327
1328 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1);
1329
1330// RF_WriteReg(dev, 0x02, 0x004c); mdelay(1);//2
1331 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);// 2
1332
1333// RF_WriteReg(dev, 0x03, 0x0000); mdelay(1);//3
1334 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);// 3
1335
1336 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1);
1337 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
1338 RF_WriteReg(dev, 0x06, 0x0ae6); mdelay(1);
1339 RF_WriteReg(dev, 0x07, 0x00ca); mdelay(1);
1340 RF_WriteReg(dev, 0x08, 0x0e1c); mdelay(1);
1341 RF_WriteReg(dev, 0x09, 0x02f0); mdelay(1);
1342 RF_WriteReg(dev, 0x0a, 0x09d0); mdelay(1);
1343 RF_WriteReg(dev, 0x0b, 0x01ba); mdelay(1);
1344 RF_WriteReg(dev, 0x0c, 0x0640); mdelay(1);
1345 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
1346 RF_WriteReg(dev, 0x0e, 0x0020); mdelay(1);
1347 RF_WriteReg(dev, 0x0f, 0x0990); mdelay(1);
1348
1349
1350 // Page1 : reg16-reg30
1351 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1);
1352
1353 RF_WriteReg(dev, 0x03, 0x0806); mdelay(1);
1354
1355 if(priv->card_8185 < VERSION_8187S_C)
1356 {
1357 RF_WriteReg(dev, 0x04, 0x03f7); mdelay(1);
1358 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1);
1359 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
1360 }
1361 else
1362 {
1363 RF_WriteReg(dev, 0x04, 0x03a7); mdelay(1);
1364 RF_WriteReg(dev, 0x05, 0x059b); mdelay(1);
1365 RF_WriteReg(dev, 0x06, 0x0081); mdelay(1);
1366 }
1367
1368
1369 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
1370// Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1371// RF_WriteReg(dev, 0x08, 0x0597); mdelay(1);
1372// RF_WriteReg(dev, 0x09, 0x050a); mdelay(1);
1373 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
1374 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
1375
1376 if(priv->card_8185 == VERSION_8187S_D)
1377 {
1378 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
1379 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
1380 RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1); // RX LO buffer
1381 }
1382 else
1383 {
1384 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
1385 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
1386 RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1); // RX LO buffer
1387 }
1388
1389 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1390
1391// RF_WriteReg(dev, 0x00, 0x017f); mdelay(1);//6
1392 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1);// 6
1393
1394 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1);
1395 RF_WriteReg(dev, 0x04, 0x0e50); mdelay(1);
1396 for(i=0;i<=36;i++)
1397 {
1398 RF_WriteReg(dev, 0x01, i); mdelay(1);
1399 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1400 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1401 }
1402
1403 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /// 203, 343
1404 //RF_WriteReg(dev, 0x06, 0x0300); mdelay(1); // 400
1405 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); // 400
1406
1407 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30, and HSSI disable 137
1408 mdelay(10); // Deay 10 ms. //0xfd
1409
1410// RF_WriteReg(dev, 0x0c, 0x09be); mdelay(1); // 7
1411 //RF_WriteReg(dev, 0x0c, 0x07be); mdelay(1);
1412 //mdelay(10); // Deay 10 ms. //0xfd
1413
1414 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); // Z4 synthesizer loop filter setting, 392
1415 mdelay(10); // Deay 10 ms. //0xfd
1416
1417 RF_WriteReg(dev, 0x00, 0x0037); mdelay(1); // switch to reg0-reg15, and HSSI disable
1418 mdelay(10); // Deay 10 ms. //0xfd
1419
1420 RF_WriteReg(dev, 0x04, 0x0160); mdelay(1); // CBC on, Tx Rx disable, High gain
1421 mdelay(10); // Deay 10 ms. //0xfd
1422
1423 RF_WriteReg(dev, 0x07, 0x0080); mdelay(1); // Z4 setted channel 1
1424 mdelay(10); // Deay 10 ms. //0xfd
1425
1426 RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); // LC calibration
1427 mdelay(200); // Deay 200 ms. //0xfd
1428 mdelay(10); // Deay 10 ms. //0xfd
1429 mdelay(10); // Deay 10 ms. //0xfd
1430
1431 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30 137, and HSSI disable 137
1432 mdelay(10); // Deay 10 ms. //0xfd
1433
1434 RF_WriteReg(dev, 0x07, 0x0000); mdelay(1);
1435 RF_WriteReg(dev, 0x07, 0x0180); mdelay(1);
1436 RF_WriteReg(dev, 0x07, 0x0220); mdelay(1);
1437 RF_WriteReg(dev, 0x07, 0x03E0); mdelay(1);
1438
1439 // DAC calibration off 20070702
1440 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
1441 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
1442//{by amy 080312
1443 // For crystal calibration, added by Roger, 2007.12.11.
1444 if( priv->bXtalCalibration ) // reg 30.
1445 { // enable crystal calibration.
1446 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0].
1447 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1448 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1449 // So we should minus 4 BITs offset.
1450 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9); mdelay(1);
1451 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1452 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1453 }
1454 else
1455 { // using default value. Xin=6, Xout=6.
1456 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1457 }
1458//by amy 080312
1459// RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); //-by amy 080312
1460
1461 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); // switch to reg0-reg15, and HSSI enable
1462// RF_WriteReg(dev, 0x0d, 0x009f); mdelay(1); // Rx BB start calibration, 00c//-edward
1463 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); // Rx BB start calibration, 00c//+edward
1464 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); // temperature meter off
1465 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); // Rx mode
1466 mdelay(10); // Deay 10 ms. //0xfe
1467 mdelay(10); // Deay 10 ms. //0xfe
1468 mdelay(10); // Deay 10 ms. //0xfe
1469 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1); // Rx mode//+edward
1470 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1); // Rx mode//+edward
1471 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1); // Rx mode//+edward
1472
1473#if 0//-edward
1474 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1);
1475 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1);
1476 RF_WriteReg(dev, 0x00, 0x009F); mdelay(1);
1477#endif
1478 RF_WriteReg(dev, 0x01, 0x0000); mdelay(1); // Rx mode//+edward
1479 RF_WriteReg(dev, 0x02, 0x0000); mdelay(1); // Rx mode//+edward
1480 //power save parameters.
1481 u1b24E = read_nic_byte(dev, 0x24E);
1482 write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1483
1484 //=============================================================================
1485
1486 //=============================================================================
1487 // CCKCONF.TXT
1488 //=============================================================================
1489
1490 /* [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1491 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1492 CCK reg0x00[6]=1'b1: power saving for RX (default)
1493 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1494 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1495 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1496 */
1497#if 0
1498 write_nic_dword(dev, PHY_ADR, 0x0100c880);
1499 write_nic_dword(dev, PHY_ADR, 0x01001c86);
1500 write_nic_dword(dev, PHY_ADR, 0x01007890);
1501 write_nic_dword(dev, PHY_ADR, 0x0100d0ae);
1502 write_nic_dword(dev, PHY_ADR, 0x010006af);
1503 write_nic_dword(dev, PHY_ADR, 0x01004681);
1504#endif
1505 write_phy_cck(dev,0x00,0xc8);
1506 write_phy_cck(dev,0x06,0x1c);
1507 write_phy_cck(dev,0x10,0x78);
1508 write_phy_cck(dev,0x2e,0xd0);
1509 write_phy_cck(dev,0x2f,0x06);
1510 write_phy_cck(dev,0x01,0x46);
1511
1512 // power control
1513 write_nic_byte(dev, CCK_TXAGC, 0x10);
1514 write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1515 write_nic_byte(dev, ANTSEL, 0x03);
1516#else
1517 //=============================================================================
1518 // RADIOCFG.TXT
1519 //=============================================================================
1520
1521 RF_WriteReg(dev, 0x00, 0x00b7); mdelay(1);
1522 RF_WriteReg(dev, 0x01, 0x0ee0); mdelay(1);
1523 RF_WriteReg(dev, 0x02, 0x044d); mdelay(1);
1524 RF_WriteReg(dev, 0x03, 0x0441); mdelay(1);
1525 RF_WriteReg(dev, 0x04, 0x08c3); mdelay(1);
1526 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
1527 RF_WriteReg(dev, 0x06, 0x00e6); mdelay(1);
1528 RF_WriteReg(dev, 0x07, 0x082a); mdelay(1);
1529 RF_WriteReg(dev, 0x08, 0x003f); mdelay(1);
1530 RF_WriteReg(dev, 0x09, 0x0335); mdelay(1);
1531 RF_WriteReg(dev, 0x0a, 0x09d4); mdelay(1);
1532 RF_WriteReg(dev, 0x0b, 0x07bb); mdelay(1);
1533 RF_WriteReg(dev, 0x0c, 0x0850); mdelay(1);
1534 RF_WriteReg(dev, 0x0d, 0x0cdf); mdelay(1);
1535 RF_WriteReg(dev, 0x0e, 0x002b); mdelay(1);
1536 RF_WriteReg(dev, 0x0f, 0x0114); mdelay(1);
1537
1538 RF_WriteReg(dev, 0x00, 0x01b7); mdelay(1);
1539
1540
1541 for(i=1;i<=95;i++)
1542 {
1543 RF_WriteReg(dev, 0x01, i); mdelay(1);
1544 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1545 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1546 }
1547
1548 RF_WriteReg(dev, 0x03, 0x0080); mdelay(1); // write reg 18
1549 RF_WriteReg(dev, 0x05, 0x0004); mdelay(1); // write reg 20
1550 RF_WriteReg(dev, 0x00, 0x00b7); mdelay(1); // switch to reg0-reg15
1551 //0xfd
1552 //0xfd
1553 //0xfd
1554 RF_WriteReg(dev, 0x02, 0x0c4d); mdelay(1);
1555 mdelay(100); // Deay 100 ms. //0xfe
1556 mdelay(100); // Deay 100 ms. //0xfe
1557 RF_WriteReg(dev, 0x02, 0x044d); mdelay(1);
1558 RF_WriteReg(dev, 0x00, 0x02bf); mdelay(1); //0x002f disable 6us corner change, 06f--> enable
1559
1560 //=============================================================================
1561
1562 //=============================================================================
1563 // CCKCONF.TXT
1564 //=============================================================================
1565
1566 //=============================================================================
1567
1568 //=============================================================================
1569 // Follow WMAC RTL8225_Config()
1570 //=============================================================================
1571
1572 // power control
1573 write_nic_byte(dev, CCK_TXAGC, 0x03);
1574 write_nic_byte(dev, OFDM_TXAGC, 0x07);
1575 write_nic_byte(dev, ANTSEL, 0x03);
1576
1577 //=============================================================================
1578
1579 // OFDM BBP setup
1580// SetOutputEnableOfRfPins(dev);//by amy
1581#endif
1582
1583
1584
1585 //=============================================================================
1586 // AGC.txt
1587 //=============================================================================
1588
1589// PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280); // Annie, 2006-05-05
1590 write_phy_ofdm(dev, 0x00, 0x12);
1591 //WriteBBPortUchar(dev, 0x00001280);
1592
1593 for (i=0; i<128; i++)
1594 {
1595 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1596
1597 data = ZEBRA_AGC[i+1];
1598 data = data << 8;
1599 data = data | 0x0000008F;
1600
1601 addr = i + 0x80; //enable writing AGC table
1602 addr = addr << 8;
1603 addr = addr | 0x0000008E;
1604
1605 WriteBBPortUchar(dev, data);
1606 WriteBBPortUchar(dev, addr);
1607 WriteBBPortUchar(dev, 0x0000008E);
1608 }
1609
1610 PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080); // Annie, 2006-05-05
1611 //WriteBBPortUchar(dev, 0x00001080);
1612
1613 //=============================================================================
1614
1615 //=============================================================================
1616 // OFDMCONF.TXT
1617 //=============================================================================
1618
1619 for(i=0; i<60; i++)
1620 {
1621 u4bRegOffset=i;
1622 u4bRegValue=OFDM_CONFIG[i];
1623
1624 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1625
1626 WriteBBPortUchar(dev,
1627 (0x00000080 |
1628 (u4bRegOffset & 0x7f) |
1629 ((u4bRegValue & 0xff) << 8)));
1630 }
1631
1632 //=============================================================================
1633//by amy for antenna
1634 //=============================================================================
1635//{by amy 080312
1636#ifdef CONFIG_RTL818X_S
1637 // Config Sw/Hw Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1638 SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1639#endif
1640//by amy 080312}
1641#if 0
1642 // Config Sw/Hw Antenna Diversity
1643 if( priv->bSwAntennaDiverity ) // Use SW+Hw Antenna Diversity
1644 {
1645 if( priv->bDefaultAntenna1 == true ) // aux antenna
1646 {
1647 // Mac register, aux antenna
1648 write_nic_byte(dev, ANTSEL, 0x00);
1649 // Config CCK RX antenna.
1650 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1651 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1652 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1653 // Config OFDM RX antenna.
1654 write_phy_ofdm(dev, 0x0d, 0x54); // Reg0d : 54
1655 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
1656 }
1657 else // main antenna
1658 {
1659 // Mac register, main antenna
1660 write_nic_byte(dev, ANTSEL, 0x03);
1661 //base band
1662 // Config CCK RX antenna.
1663 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1664 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1665 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1666 // Config OFDM RX antenna.
1667 write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c
1668 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
1669 }
1670 }
1671 else // Disable Antenna Diversity
1672 {
1673 if( priv->bDefaultAntenna1 == true ) // aux Antenna
1674 {
1675 // Mac register, aux antenna
1676 write_nic_byte(dev, ANTSEL, 0x00);
1677 // Config CCK RX antenna.
1678 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1679 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1680 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1681 // Config OFDM RX antenna.
1682 write_phy_ofdm(dev, 0x0d, 0x54); // Reg0d : 54
1683 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1684 }
1685 else // main Antenna
1686 {
1687 // Mac register, main antenna
1688 write_nic_byte(dev, ANTSEL, 0x03);
1689 // Config CCK RX antenna.
1690 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1691 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1692 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1693 // Config OFDM RX antenna.
1694 write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c
1695 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1696 }
1697 }
1698#endif
1699//by amy for antenna
1700}
1701
1702
1703void
1704UpdateInitialGain(
1705 struct net_device *dev
1706 )
1707{
1708 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1709 //unsigned char* IGTable;
1710 //u8 DIG_CurrentInitialGain = 4;
1711 //unsigned char u1Tmp;
1712
1713 //lzm add 080826
1714 if(priv->eRFPowerState != eRfOn)
1715 {
1716 //Don't access BB/RF under disable PLL situation.
1717 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1718 // Back to the original state
1719 priv->InitialGain= priv->InitialGainBackUp;
1720 return;
1721 }
1722
1723 switch(priv->rf_chip)
1724 {
1725#if 0
1726 case RF_ZEBRA2:
1727 // Dynamic set initial gain, by shien chang, 2006.07.14
1728 switch(priv->InitialGain)
1729 {
1730 case 1: //m861dBm
1731 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm \n");
1732 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1733 write_nic_dword(dev, PhyAddr, 0x86a4); mdelay(1);
1734 write_nic_dword(dev, PhyAddr, 0xfa85); mdelay(1);
1735 break;
1736
1737 case 2: //m862dBm
1738 DMESG("RTL8185B + 8225 Initial Gain State 2: -82 dBm \n");
1739 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1740 write_nic_dword(dev, PhyAddr, 0x86a4); mdelay(1);
1741 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1742 break;
1743
1744 case 3: //m863dBm
1745 DMESG("RTL8185B + 8225 Initial Gain State 3: -82 dBm \n");
1746 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1747 write_nic_dword(dev, PhyAddr, 0x96a4); mdelay(1);
1748 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1749 break;
1750
1751 case 4: //m864dBm
1752 DMESG("RTL8185B + 8225 Initial Gain State 4: -78 dBm \n");
1753 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1754 write_nic_dword(dev, PhyAddr, 0xa6a4); mdelay(1);
1755 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1756 break;
1757
1758 case 5: //m82dBm
1759 DMESG("RTL8185B + 8225 Initial Gain State 5: -74 dBm \n");
1760 write_nic_dword(dev, PhyAddr, 0x3697); mdelay(1);
1761 write_nic_dword(dev, PhyAddr, 0xa6a4); mdelay(1);
1762 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1763 break;
1764
1765 case 6: //m78dBm
1766 DMESG("RTL8185B + 8225 Initial Gain State 6: -70 dBm \n");
1767 write_nic_dword(dev, PhyAddr, 0x4697); mdelay(1);
1768 write_nic_dword(dev, PhyAddr, 0xa6a4); mdelay(1);
1769 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1770 break;
1771
1772 case 7: //m74dBm
1773 DMESG("RTL8185B + 8225 Initial Gain State 7: -66 dBm \n");
1774 write_nic_dword(dev, PhyAddr, 0x5697); mdelay(1);
1775 write_nic_dword(dev, PhyAddr, 0xa6a4); mdelay(1);
1776 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1777 break;
1778
1779 default: //MP
1780 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm (default)\n");
1781 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1782 write_nic_dword(dev, PhyAddr, 0x86a4); mdelay(1);
1783 write_nic_dword(dev, PhyAddr, 0xfa85); mdelay(1);
1784 break;
1785 }
1786 break;
1787#endif
1788 case RF_ZEBRA4:
1789 // Dynamic set initial gain, follow 87B
1790 switch(priv->InitialGain)
1791 {
1792 case 1: //m861dBm
1793 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1794 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
1795 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1796 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1797 break;
1798
1799 case 2: //m862dBm
1800 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1801 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
1802 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1803 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1804 break;
1805
1806 case 3: //m863dBm
1807 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1808 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
1809 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1810 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1811 break;
1812
1813 case 4: //m864dBm
1814 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1815 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
1816 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1817 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1818 break;
1819
1820 case 5: //m82dBm
1821 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1822 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
1823 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
1824 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1825 break;
1826
1827 case 6: //m78dBm
1828 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1829 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
1830 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
1831 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1832 break;
1833
1834 case 7: //m74dBm
1835 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1836 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
1837 write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1);
1838 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1839 break;
1840
1841 case 8:
1842 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1843 write_phy_ofdm(dev, 0x17, 0x66); mdelay(1);
1844 write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1);
1845 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1846 break;
1847
1848
1849 default: //MP
1850 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1851 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
1852 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1853 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1854 break;
1855 }
1856 break;
1857
1858
1859 default:
1860 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1861 break;
1862 }
1863}
1864#ifdef CONFIG_RTL818X_S
1865//
1866// Description:
1867// Tx Power tracking mechanism routine on 87SE.
1868// Created by Roger, 2007.12.11.
1869//
1870void
1871InitTxPwrTracking87SE(
1872 struct net_device *dev
1873)
1874{
1875 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1876 u32 u4bRfReg;
1877
1878 u4bRfReg = RF_ReadReg(dev, 0x02);
1879
1880 // Enable Thermal meter indication.
1881 //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1882 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
1883}
1884
1885#endif
1886void
1887PhyConfig8185(
1888 struct net_device *dev
1889 )
1890{
1891 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1892 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1893 priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1894 // RF config
1895 switch(priv->rf_chip)
1896 {
1897 case RF_ZEBRA2:
1898 case RF_ZEBRA4:
1899 ZEBRA_Config_85BASIC_HardCode( dev);
1900 break;
1901 }
1902//{by amy 080312
1903#ifdef CONFIG_RTL818X_S
1904 // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1905 if(priv->bDigMechanism)
1906 {
1907 if(priv->InitialGain == 0)
1908 priv->InitialGain = 4;
1909 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1910 }
1911
1912 //
1913 // Enable thermal meter indication to implement TxPower tracking on 87SE.
1914 // We initialize thermal meter here to avoid unsuccessful configuration.
1915 // Added by Roger, 2007.12.11.
1916 //
1917 if(priv->bTxPowerTrack)
1918 InitTxPwrTracking87SE(dev);
1919
1920#endif
1921//by amy 080312}
1922 priv->InitialGainBackUp= priv->InitialGain;
1923 UpdateInitialGain(dev);
1924
1925 return;
1926}
1927
1928
1929
1930
1931void
1932HwConfigureRTL8185(
1933 struct net_device *dev
1934 )
1935{
1936 //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1937// u8 bUNIVERSAL_CONTROL_RL = 1;
1938 u8 bUNIVERSAL_CONTROL_RL = 0;
1939
1940 u8 bUNIVERSAL_CONTROL_AGC = 1;
1941 u8 bUNIVERSAL_CONTROL_ANT = 1;
1942 u8 bAUTO_RATE_FALLBACK_CTL = 1;
1943 u8 val8;
1944 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1945 //struct ieee80211_device *ieee = priv->ieee80211;
1946 //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1947//{by amy 080312 if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1948// {
1949// write_nic_word(dev, BRSR, 0xffff);
1950// }
1951// else
1952// {
1953// write_nic_word(dev, BRSR, 0x000f);
1954// }
1955//by amy 080312}
1956 write_nic_word(dev, BRSR, 0x0fff);
1957 // Retry limit
1958 val8 = read_nic_byte(dev, CW_CONF);
1959
1960 if(bUNIVERSAL_CONTROL_RL)
1961 val8 = val8 & 0xfd;
1962 else
1963 val8 = val8 | 0x02;
1964
1965 write_nic_byte(dev, CW_CONF, val8);
1966
1967 // Tx AGC
1968 val8 = read_nic_byte(dev, TXAGC_CTL);
1969 if(bUNIVERSAL_CONTROL_AGC)
1970 {
1971 write_nic_byte(dev, CCK_TXAGC, 128);
1972 write_nic_byte(dev, OFDM_TXAGC, 128);
1973 val8 = val8 & 0xfe;
1974 }
1975 else
1976 {
1977 val8 = val8 | 0x01 ;
1978 }
1979
1980
1981 write_nic_byte(dev, TXAGC_CTL, val8);
1982
1983 // Tx Antenna including Feedback control
1984 val8 = read_nic_byte(dev, TXAGC_CTL );
1985
1986 if(bUNIVERSAL_CONTROL_ANT)
1987 {
1988 write_nic_byte(dev, ANTSEL, 0x00);
1989 val8 = val8 & 0xfd;
1990 }
1991 else
1992 {
1993 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1994 }
1995
1996 write_nic_byte(dev, TXAGC_CTL, val8);
1997
1998 // Auto Rate fallback control
1999 val8 = read_nic_byte(dev, RATE_FALLBACK);
2000 val8 &= 0x7c;
2001 if( bAUTO_RATE_FALLBACK_CTL )
2002 {
2003 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
2004
2005 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
2006 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
2007//by amy
2008#if 0
2009 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); // set 1M ~ 54M
2010#endif
2011#ifdef CONFIG_RTL818X_S
2012 // Aadded by Roger, 2007.11.15.
2013 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
2014#else
2015 PlatformIOWrite2Byte(dev, ARFR, 0x0c00); //set 48Mbps, 54Mbps.
2016 // By SD3 szuyi's request. by Roger, 2007.03.26.
2017#endif
2018//by amy
2019 }
2020 else
2021 {
2022 }
2023 write_nic_byte(dev, RATE_FALLBACK, val8);
2024}
2025
2026
2027
2028static void
2029MacConfig_85BASIC_HardCode(
2030 struct net_device *dev)
2031{
2032 //============================================================================
2033 // MACREG.TXT
2034 //============================================================================
2035 int nLinesRead = 0;
2036
2037 u32 u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
2038 int i;
2039
2040 nLinesRead=sizeof(MAC_REG_TABLE)/2;
2041
2042 for(i = 0; i < nLinesRead; i++) //nLinesRead=101
2043 {
2044 u4bRegOffset=MAC_REG_TABLE[i][0];
2045 u4bRegValue=MAC_REG_TABLE[i][1];
2046
2047 if(u4bRegOffset == 0x5e)
2048 {
2049 u4bPageIndex = u4bRegValue;
2050 }
2051 else
2052 {
2053 u4bRegOffset |= (u4bPageIndex << 8);
2054 }
2055 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
2056 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
2057 }
2058 //============================================================================
2059}
2060
2061
2062
2063static void
2064MacConfig_85BASIC(
2065 struct net_device *dev)
2066{
2067
2068 u8 u1DA;
2069 MacConfig_85BASIC_HardCode(dev);
2070
2071 //============================================================================
2072
2073 // Follow TID_AC_MAP of WMac.
2074 write_nic_word(dev, TID_AC_MAP, 0xfa50);
2075
2076 // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
2077 write_nic_word(dev, IntMig, 0x0000);
2078
2079 // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
2080 PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
2081 PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
2082 PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
2083
2084 // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
2085 //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
2086//by amy
2087#if 0
2088 write_nic_dword(dev, RFTiming, 0x00004001);
2089#endif
2090#ifdef CONFIG_RTL818X_S
2091 // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
2092
2093 //Enable DA10 TX power saving
2094 u1DA = read_nic_byte(dev, PHYPR);
2095 write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
2096
2097 //POWER:
2098 write_nic_word(dev, 0x360, 0x1000);
2099 write_nic_word(dev, 0x362, 0x1000);
2100
2101 // AFE.
2102 write_nic_word(dev, 0x370, 0x0560);
2103 write_nic_word(dev, 0x372, 0x0560);
2104 write_nic_word(dev, 0x374, 0x0DA4);
2105 write_nic_word(dev, 0x376, 0x0DA4);
2106 write_nic_word(dev, 0x378, 0x0560);
2107 write_nic_word(dev, 0x37A, 0x0560);
2108 write_nic_word(dev, 0x37C, 0x00EC);
2109// write_nic_word(dev, 0x37E, 0x00FE);//-edward
2110 write_nic_word(dev, 0x37E, 0x00EC);//+edward
2111#else
2112 write_nic_dword(dev, RFTiming, 0x00004003);
2113#endif
2114 write_nic_byte(dev, 0x24E,0x01);
2115//by amy
2116
2117}
2118
2119
2120
2121
2122u8
2123GetSupportedWirelessMode8185(
2124 struct net_device *dev
2125)
2126{
2127 u8 btSupportedWirelessMode = 0;
2128 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2129
2130 switch(priv->rf_chip)
2131 {
2132 case RF_ZEBRA2:
2133 case RF_ZEBRA4:
2134 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
2135 break;
2136 default:
2137 btSupportedWirelessMode = WIRELESS_MODE_B;
2138 break;
2139 }
2140
2141 return btSupportedWirelessMode;
2142}
2143
2144void
2145ActUpdateChannelAccessSetting(
2146 struct net_device *dev,
2147 WIRELESS_MODE WirelessMode,
2148 PCHANNEL_ACCESS_SETTING ChnlAccessSetting
2149 )
2150{
2151 struct r8180_priv *priv = ieee80211_priv(dev);
2152 struct ieee80211_device *ieee = priv->ieee80211;
2153 AC_CODING eACI;
2154 AC_PARAM AcParam;
2155 //PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos;
2156 u8 bFollowLegacySetting = 0;
2157 u8 u1bAIFS;
2158
2159 //
2160 // <RJ_TODO_8185B>
2161 // TODO: We still don't know how to set up these registers, just follow WMAC to
2162 // verify 8185B FPAG.
2163 //
2164 // <RJ_TODO_8185B>
2165 // Jong said CWmin/CWmax register are not functional in 8185B,
2166 // so we shall fill channel access realted register into AC parameter registers,
2167 // even in nQBss.
2168 //
2169 ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
2170 ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
2171 ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
2172 ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2173 ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
2174 ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
2175
2176 write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
2177 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer ); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
2178 write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
2179
2180 u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
2181
2182 //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
2183 //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
2184 //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
2185 //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
2186
2187 write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
2188
2189 write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2190
2191#ifdef TODO
2192 // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
2193 if( pStaQos->CurrentQosMode > QOS_DISABLE )
2194 { // QoS mode.
2195 if(pStaQos->QBssWirelessMode == WirelessMode)
2196 {
2197 // Follow AC Parameters of the QBSS.
2198 for(eACI = 0; eACI < AC_MAX; eACI++)
2199 {
2200 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
2201 }
2202 }
2203 else
2204 {
2205 // Follow Default WMM AC Parameters.
2206 bFollowLegacySetting = 1;
2207 }
2208 }
2209 else
2210#endif
2211 { // Legacy 802.11.
2212 bFollowLegacySetting = 1;
2213
2214 }
2215
2216 // this setting is copied from rtl8187B. xiong-2006-11-13
2217 if(bFollowLegacySetting)
2218 {
2219
2220
2221 //
2222 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
2223 // 2005.12.01, by rcnjko.
2224 //
2225 AcParam.longData = 0;
2226 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2227 AcParam.f.AciAifsn.f.ACM = 0;
2228 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
2229 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
2230 AcParam.f.TXOPLimit = 0;
2231
2232 //lzm reserved 080826
2233#if 1
2234#ifdef THOMAS_TURBO
2235 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
2236 if( ieee->current_network.Turbo_Enable == 1 )
2237 AcParam.f.TXOPLimit = 0x01FF;
2238#endif
2239 // For 87SE with Intel 4965 Ad-Hoc mode have poor throughput (19MB)
2240 if (ieee->iw_mode == IW_MODE_ADHOC)
2241 AcParam.f.TXOPLimit = 0x0020;
2242#endif
2243
2244 for(eACI = 0; eACI < AC_MAX; eACI++)
2245 {
2246 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2247 {
2248 PAC_PARAM pAcParam = (PAC_PARAM)(&AcParam);
2249 AC_CODING eACI;
2250 u8 u1bAIFS;
2251 u32 u4bAcParam;
2252
2253 // Retrive paramters to udpate.
2254 eACI = pAcParam->f.AciAifsn.f.ACI;
2255 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
2256 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
2257 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
2258 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
2259 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2260
2261 switch(eACI)
2262 {
2263 case AC1_BK:
2264 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2265 break;
2266
2267 case AC0_BE:
2268 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2269 break;
2270
2271 case AC2_VI:
2272 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2273 break;
2274
2275 case AC3_VO:
2276 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2277 break;
2278
2279 default:
2280 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2281 break;
2282 }
2283
2284 // Cehck ACM bit.
2285 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2286 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
2287 {
2288 PACI_AIFSN pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
2289 AC_CODING eACI = pAciAifsn->f.ACI;
2290
2291 //modified Joseph
2292 //for 8187B AsynIORead issue
2293#ifdef TODO
2294 u8 AcmCtrl = pHalData->AcmControl;
2295#else
2296 u8 AcmCtrl = 0;
2297#endif
2298 if( pAciAifsn->f.ACM )
2299 { // ACM bit is 1.
2300 switch(eACI)
2301 {
2302 case AC0_BE:
2303 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN); // or 0x21
2304 break;
2305
2306 case AC2_VI:
2307 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN); // or 0x42
2308 break;
2309
2310 case AC3_VO:
2311 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN); // or 0x84
2312 break;
2313
2314 default:
2315 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
2316 break;
2317 }
2318 }
2319 else
2320 { // ACM bit is 0.
2321 switch(eACI)
2322 {
2323 case AC0_BE:
2324 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xDE
2325 break;
2326
2327 case AC2_VI:
2328 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xBD
2329 break;
2330
2331 case AC3_VO:
2332 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0x7B
2333 break;
2334
2335 default:
2336 break;
2337 }
2338 }
2339
2340 //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2341
2342#ifdef TO_DO
2343 pHalData->AcmControl = AcmCtrl;
2344#endif
2345 //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
2346 write_nic_byte(dev, ACM_CONTROL, 0);
2347 }
2348 }
2349 }
2350
2351
2352 }
2353}
2354
2355void
2356ActSetWirelessMode8185(
2357 struct net_device *dev,
2358 u8 btWirelessMode
2359 )
2360{
2361 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2362 struct ieee80211_device *ieee = priv->ieee80211;
2363 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
2364 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2365
2366 if( (btWirelessMode & btSupportedWirelessMode) == 0 )
2367 { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
2368 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
2369 btWirelessMode, btSupportedWirelessMode);
2370 return;
2371 }
2372
2373 // 1. Assign wireless mode to swtich if necessary.
2374 if (btWirelessMode == WIRELESS_MODE_AUTO)
2375 {
2376 if((btSupportedWirelessMode & WIRELESS_MODE_A))
2377 {
2378 btWirelessMode = WIRELESS_MODE_A;
2379 }
2380 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
2381 {
2382 btWirelessMode = WIRELESS_MODE_G;
2383 }
2384 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
2385 {
2386 btWirelessMode = WIRELESS_MODE_B;
2387 }
2388 else
2389 {
2390 DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
2391 btSupportedWirelessMode);
2392 btWirelessMode = WIRELESS_MODE_B;
2393 }
2394 }
2395
2396
2397 // 2. Swtich band: RF or BB specific actions,
2398 // for example, refresh tables in omc8255, or change initial gain if necessary.
2399 switch(priv->rf_chip)
2400 {
2401 case RF_ZEBRA2:
2402 case RF_ZEBRA4:
2403 {
2404 // Nothing to do for Zebra to switch band.
2405 // Update current wireless mode if we swtich to specified band successfully.
2406 ieee->mode = (WIRELESS_MODE)btWirelessMode;
2407 }
2408 break;
2409
2410 default:
2411 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
2412 break;
2413 }
2414
2415 // 3. Change related setting.
2416 if( ieee->mode == WIRELESS_MODE_A ){
2417 DMESG("WIRELESS_MODE_A\n");
2418 }
2419 else if( ieee->mode == WIRELESS_MODE_B ){
2420 DMESG("WIRELESS_MODE_B\n");
2421 }
2422 else if( ieee->mode == WIRELESS_MODE_G ){
2423 DMESG("WIRELESS_MODE_G\n");
2424 }
2425
2426 ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
2427}
2428
2429void rtl8185b_irq_enable(struct net_device *dev)
2430{
2431 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2432
2433 priv->irq_enabled = 1;
2434 write_nic_dword(dev, IMR, priv->IntrMask);
2435}
2436//by amy for power save
2437void
2438DrvIFIndicateDisassociation(
2439 struct net_device *dev,
2440 u16 reason
2441 )
2442{
2443 //printk("==> DrvIFIndicateDisassociation()\n");
2444
2445 // nothing is needed after disassociation request.
2446
2447 //printk("<== DrvIFIndicateDisassociation()\n");
2448}
2449void
2450MgntDisconnectIBSS(
2451 struct net_device *dev
2452)
2453{
2454 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2455 u8 i;
2456
2457 //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
2458
2459 DrvIFIndicateDisassociation(dev, unspec_reason);
2460
2461// PlatformZeroMemory( pMgntInfo->Bssid, 6 );
2462 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x55;
2463
2464 priv->ieee80211->state = IEEE80211_NOLINK;
2465
2466 //Stop Beacon.
2467
2468 // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
2469 // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
2470 // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
2471
2472 // Disable Beacon Queue Own bit, suggested by jong
2473// Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
2474 ieee80211_stop_send_beacons(priv->ieee80211);
2475
2476 priv->ieee80211->link_change(dev);
2477 notify_wx_assoc_event(priv->ieee80211);
2478
2479 // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
2480#if 0
2481 if(pMgntInfo->bEnableSwBeaconTimer)
2482 {
2483 // SwBeaconTimer will stop if pMgntInfo->mIbss==FALSE, see SwBeaconCallback() for details.
2484// comment out by haich, 2007.10.01
2485//#if DEV_BUS_TYPE==USB_INTERFACE
2486 PlatformCancelTimer( Adapter, &pMgntInfo->SwBeaconTimer);
2487//#endif
2488 }
2489#endif
2490
2491// MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
2492
2493}
2494void
2495MlmeDisassociateRequest(
2496 struct net_device *dev,
2497 u8* asSta,
2498 u8 asRsn
2499 )
2500{
2501 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2502 u8 i;
2503
2504 SendDisassociation(priv->ieee80211, asSta, asRsn );
2505
2506 if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
2507 //ShuChen TODO: change media status.
2508 //ShuChen TODO: What to do when disassociate.
2509 DrvIFIndicateDisassociation(dev, unspec_reason);
2510
2511
2512 // pMgntInfo->AsocTimestamp = 0;
2513 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22;
2514// pMgntInfo->mBrates.Length = 0;
2515// Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2516
2517 ieee80211_disassociate(priv->ieee80211);
2518
2519
2520 }
2521
2522}
2523
2524void
2525MgntDisconnectAP(
2526 struct net_device *dev,
2527 u8 asRsn
2528)
2529{
2530 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2531
2532//
2533// Commented out by rcnjko, 2005.01.27:
2534// I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2535//
2536// //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2537// SecClearAllKeys(Adapter);
2538
2539 // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2540#ifdef TODO
2541 if( pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2542 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) ) // In CCKM mode will Clear key
2543 {
2544 SecClearAllKeys(Adapter);
2545 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2546 }
2547#endif
2548 // 2004.10.11, by rcnjko.
2549 //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2550 MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2551
2552 priv->ieee80211->state = IEEE80211_NOLINK;
2553// pMgntInfo->AsocTimestamp = 0;
2554}
2555bool
2556MgntDisconnect(
2557 struct net_device *dev,
2558 u8 asRsn
2559)
2560{
2561 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2562 //
2563 // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2564 //
2565#ifdef TODO
2566 if(pMgntInfo->mPss != eAwake)
2567 {
2568 //
2569 // Using AwkaeTimer to prevent mismatch ps state.
2570 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2571 //
2572 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2573 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2574 }
2575#endif
2576
2577 // Indication of disassociation event.
2578 //DrvIFIndicateDisassociation(Adapter, asRsn);
2579#ifdef ENABLE_DOT11D
2580 if(IS_DOT11D_ENABLE(priv->ieee80211))
2581 Dot11d_Reset(priv->ieee80211);
2582#endif
2583 // In adhoc mode, update beacon frame.
2584 if( priv->ieee80211->state == IEEE80211_LINKED )
2585 {
2586 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2587 {
2588// RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2589 //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2590 MgntDisconnectIBSS(dev);
2591 }
2592 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2593 {
2594 // We clear key here instead of MgntDisconnectAP() because that
2595 // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2596 // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2597 // used to handle disassociation related things to AP, e.g. send Disassoc
2598 // frame to AP. 2005.01.27, by rcnjko.
2599// SecClearAllKeys(Adapter);
2600
2601// RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2602 //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2603 MgntDisconnectAP(dev, asRsn);
2604 }
2605
2606 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2607// MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2608 }
2609
2610 return true;
2611}
2612//
2613// Description:
2614// Chang RF Power State.
2615// Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2616//
2617// Assumption:
2618// PASSIVE LEVEL.
2619//
2620bool
2621SetRFPowerState(
2622 struct net_device *dev,
2623 RT_RF_POWER_STATE eRFPowerState
2624 )
2625{
2626 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2627 bool bResult = false;
2628
2629// printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2630 if(eRFPowerState == priv->eRFPowerState)
2631 {
2632// printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2633 return bResult;
2634 }
2635
2636 switch(priv->rf_chip)
2637 {
2638 case RF_ZEBRA2:
2639 case RF_ZEBRA4:
2640 bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2641 break;
2642
2643 default:
2644 printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2645 break;;
2646}
2647// printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2648
2649 return bResult;
2650}
2651void
2652HalEnableRx8185Dummy(
2653 struct net_device *dev
2654 )
2655{
2656}
2657void
2658HalDisableRx8185Dummy(
2659 struct net_device *dev
2660 )
2661{
2662}
2663
2664bool
2665MgntActSet_RF_State(
2666 struct net_device *dev,
2667 RT_RF_POWER_STATE StateToSet,
2668 u32 ChangeSource
2669 )
2670{
2671 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2672 bool bActionAllowed = false;
2673 bool bConnectBySSID = false;
2674 RT_RF_POWER_STATE rtState;
2675 u16 RFWaitCounter = 0;
2676 unsigned long flag;
2677// printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2678 //
2679 // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2680 // Only one thread can change the RF state at one time, and others should wait to be executed.
2681 //
2682#if 1
2683 while(true)
2684 {
2685// down(&priv->rf_state);
2686 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2687 if(priv->RFChangeInProgress)
2688 {
2689// printk("====================>haha111111111\n");
2690// up(&priv->rf_state);
2691// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2692 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2693 // Set RF after the previous action is done.
2694 while(priv->RFChangeInProgress)
2695 {
2696 RFWaitCounter ++;
2697// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2698 udelay(1000); // 1 ms
2699
2700 // Wait too long, return FALSE to avoid to be stuck here.
2701 if(RFWaitCounter > 1000) // 1sec
2702 {
2703// RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2704 printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2705 // TODO: Reset RF state?
2706 return false;
2707 }
2708 }
2709 }
2710 else
2711 {
2712// printk("========================>haha2\n");
2713 priv->RFChangeInProgress = true;
2714// up(&priv->rf_state);
2715 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2716 break;
2717 }
2718 }
2719#endif
2720 rtState = priv->eRFPowerState;
2721
2722
2723 switch(StateToSet)
2724 {
2725 case eRfOn:
2726 //
2727 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2728 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2729 //
2730 priv->RfOffReason &= (~ChangeSource);
2731
2732 if(! priv->RfOffReason)
2733 {
2734 priv->RfOffReason = 0;
2735 bActionAllowed = true;
2736
2737 if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2738 {
2739 bConnectBySSID = true;
2740 }
2741 }
2742 else
2743// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2744 ;
2745 break;
2746
2747 case eRfOff:
2748 // 070125, rcnjko: we always keep connected in AP mode.
2749
2750 if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2751 {
2752 //
2753 // 060808, Annie:
2754 // Disconnect to current BSS when radio off. Asked by QuanTa.
2755 //
2756
2757 //
2758 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2759 // because we do NOT need to set ssid to dummy ones.
2760 // Revised by Roger, 2007.12.04.
2761 //
2762 MgntDisconnect( dev, disas_lv_ss );
2763
2764 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2765 // 2007.05.28, by shien chang.
2766// PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2767// pMgntInfo->NumBssDesc = 0;
2768// PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2769// pMgntInfo->NumBssDesc4Query = 0;
2770 }
2771
2772
2773
2774 priv->RfOffReason |= ChangeSource;
2775 bActionAllowed = true;
2776 break;
2777
2778 case eRfSleep:
2779 priv->RfOffReason |= ChangeSource;
2780 bActionAllowed = true;
2781 break;
2782
2783 default:
2784 break;
2785 }
2786
2787 if(bActionAllowed)
2788 {
2789// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2790 // Config HW to the specified mode.
2791// printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2792 SetRFPowerState(dev, StateToSet);
2793
2794 // Turn on RF.
2795 if(StateToSet == eRfOn)
2796 {
2797 HalEnableRx8185Dummy(dev);
2798 if(bConnectBySSID)
2799 {
2800 // by amy not supported
2801// MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2802 }
2803 }
2804 // Turn off RF.
2805 else if(StateToSet == eRfOff)
2806 {
2807 HalDisableRx8185Dummy(dev);
2808 }
2809 }
2810 else
2811 {
2812 // printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2813 }
2814
2815 // Release RF spinlock
2816// down(&priv->rf_state);
2817 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2818 priv->RFChangeInProgress = false;
2819// up(&priv->rf_state);
2820 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2821// printk("<===MgntActSet_RF_State()\n");
2822 return bActionAllowed;
2823}
2824void
2825InactivePowerSave(
2826 struct net_device *dev
2827 )
2828{
2829 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2830 //u8 index = 0;
2831
2832 //
2833 // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2834 // is really scheduled.
2835 // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2836 // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2837 // blocks the IPS procedure of switching RF.
2838 // By Bruce, 2007-12-25.
2839 //
2840 priv->bSwRfProcessing = true;
2841
2842 MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2843
2844 //
2845 // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2846 //
2847#if 0
2848 while( index < 4 )
2849 {
2850 if( ( pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP104_Encryption ) ||
2851 (pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP40_Encryption) )
2852 {
2853 if( pMgntInfo->SecurityInfo.KeyLen[index] != 0)
2854 pAdapter->HalFunc.SetKeyHandler(pAdapter, index, 0, FALSE, pMgntInfo->SecurityInfo.PairwiseEncAlgorithm, TRUE, FALSE);
2855
2856 }
2857 index++;
2858 }
2859#endif
2860 priv->bSwRfProcessing = false;
2861}
2862
2863//
2864// Description:
2865// Enter the inactive power save mode. RF will be off
2866// 2007.08.17, by shien chang.
2867//
2868void
2869IPSEnter(
2870 struct net_device *dev
2871 )
2872{
2873 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2874 RT_RF_POWER_STATE rtState;
2875 //printk("==============================>enter IPS\n");
2876 if (priv->bInactivePs)
2877 {
2878 rtState = priv->eRFPowerState;
2879
2880 //
2881 // Added by Bruce, 2007-12-25.
2882 // Do not enter IPS in the following conditions:
2883 // (1) RF is already OFF or Sleep
2884 // (2) bSwRfProcessing (indicates the IPS is still under going)
2885 // (3) Connectted (only disconnected can trigger IPS)
2886 // (4) IBSS (send Beacon)
2887 // (5) AP mode (send Beacon)
2888 //
2889 if (rtState == eRfOn && !priv->bSwRfProcessing
2890 && (priv->ieee80211->state != IEEE80211_LINKED ))
2891 {
2892 // printk("IPSEnter(): Turn off RF.\n");
2893 priv->eInactivePowerState = eRfOff;
2894 InactivePowerSave(dev);
2895 }
2896 }
2897// printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2898}
2899void
2900IPSLeave(
2901 struct net_device *dev
2902 )
2903{
2904 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2905 RT_RF_POWER_STATE rtState;
2906 //printk("===================================>leave IPS\n");
2907 if (priv->bInactivePs)
2908 {
2909 rtState = priv->eRFPowerState;
2910 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2911 {
2912// printk("IPSLeave(): Turn on RF.\n");
2913 priv->eInactivePowerState = eRfOn;
2914 InactivePowerSave(dev);
2915 }
2916 }
2917// printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2918}
2919//by amy for power save
2920void rtl8185b_adapter_start(struct net_device *dev)
2921{
2922 struct r8180_priv *priv = ieee80211_priv(dev);
2923 struct ieee80211_device *ieee = priv->ieee80211;
2924
2925 u8 SupportedWirelessMode;
2926 u8 InitWirelessMode;
2927 u8 bInvalidWirelessMode = 0;
2928 //int i;
2929 u8 tmpu8;
2930 //u8 u1tmp,u2tmp;
2931 u8 btCR9346;
2932 u8 TmpU1b;
2933 u8 btPSR;
2934
2935 //rtl8180_rtx_disable(dev);
2936//{by amy 080312
2937 write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2938//by amy 080312}
2939 rtl8180_reset(dev);
2940
2941 priv->dma_poll_mask = 0;
2942 priv->dma_poll_stop_mask = 0;
2943
2944 //rtl8180_beacon_tx_disable(dev);
2945
2946 HwConfigureRTL8185(dev);
2947
2948 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2949 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2950
2951 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); // default network type to 'No Link'
2952
2953 //write_nic_byte(dev, BRSR, 0x0); // Set BRSR= 1M
2954
2955 write_nic_word(dev, BcnItv, 100);
2956 write_nic_word(dev, AtimWnd, 2);
2957
2958 //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2959 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2960
2961 write_nic_byte(dev, WPA_CONFIG, 0);
2962
2963 MacConfig_85BASIC(dev);
2964
2965 // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2966 // BT_DEMO_BOARD type
2967 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2968//by amy
2969//#ifdef CONFIG_RTL818X_S
2970 // for jong required
2971// PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2972//#endif
2973//by amy
2974 //BT_QA_BOARD
2975 //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2976
2977 //-----------------------------------------------------------------------------
2978 // Set up PHY related.
2979 //-----------------------------------------------------------------------------
2980 // Enable Config3.PARAM_En to revise AnaaParm.
2981 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
2982//by amy
2983 tmpu8 = read_nic_byte(dev, CONFIG3);
2984#ifdef CONFIG_RTL818X_S
2985 write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2986#else
2987 write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En | CONFIG3_CLKRUN_En) );
2988#endif
2989//by amy
2990 // Turn on Analog power.
2991 // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2992 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2993 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2994//by amy
2995#ifdef CONFIG_RTL818X_S
2996 write_nic_word(dev, ANAPARAM3, 0x0010);
2997#else
2998 write_nic_byte(dev, ANAPARAM3, 0x00);
2999#endif
3000//by amy
3001
3002 write_nic_byte(dev, CONFIG3, tmpu8);
3003 write_nic_byte(dev, CR9346, 0x00);
3004//{by amy 080312 for led
3005 // enable EEM0 and EEM1 in 9346CR
3006 btCR9346 = read_nic_byte(dev, CR9346);
3007 write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
3008
3009 // B cut use LED1 to control HW RF on/off
3010 TmpU1b = read_nic_byte(dev, CONFIG5);
3011 TmpU1b = TmpU1b & ~BIT3;
3012 write_nic_byte(dev,CONFIG5, TmpU1b);
3013
3014 // disable EEM0 and EEM1 in 9346CR
3015 btCR9346 &= ~(0xC0);
3016 write_nic_byte(dev, CR9346, btCR9346);
3017
3018 //Enable Led (suggested by Jong)
3019 // B-cut RF Radio on/off 5e[3]=0
3020 btPSR = read_nic_byte(dev, PSR);
3021 write_nic_byte(dev, PSR, (btPSR | BIT3));
3022//by amy 080312 for led}
3023 // setup initial timing for RFE.
3024 write_nic_word(dev, RFPinsOutput, 0x0480);
3025 SetOutputEnableOfRfPins(dev);
3026 write_nic_word(dev, RFPinsSelect, 0x2488);
3027
3028 // PHY config.
3029 PhyConfig8185(dev);
3030
3031 // We assume RegWirelessMode has already been initialized before,
3032 // however, we has to validate the wireless mode here and provide a reasonble
3033 // initialized value if necessary. 2005.01.13, by rcnjko.
3034 SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
3035 if( (ieee->mode != WIRELESS_MODE_B) &&
3036 (ieee->mode != WIRELESS_MODE_G) &&
3037 (ieee->mode != WIRELESS_MODE_A) &&
3038 (ieee->mode != WIRELESS_MODE_AUTO))
3039 { // It should be one of B, G, A, or AUTO.
3040 bInvalidWirelessMode = 1;
3041 }
3042 else
3043 { // One of B, G, A, or AUTO.
3044 // Check if the wireless mode is supported by RF.
3045 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
3046 (ieee->mode & SupportedWirelessMode) == 0 )
3047 {
3048 bInvalidWirelessMode = 1;
3049 }
3050 }
3051
3052 if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
3053 { // Auto or other invalid value.
3054 // Assigne a wireless mode to initialize.
3055 if((SupportedWirelessMode & WIRELESS_MODE_A))
3056 {
3057 InitWirelessMode = WIRELESS_MODE_A;
3058 }
3059 else if((SupportedWirelessMode & WIRELESS_MODE_G))
3060 {
3061 InitWirelessMode = WIRELESS_MODE_G;
3062 }
3063 else if((SupportedWirelessMode & WIRELESS_MODE_B))
3064 {
3065 InitWirelessMode = WIRELESS_MODE_B;
3066 }
3067 else
3068 {
3069 DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
3070 SupportedWirelessMode);
3071 InitWirelessMode = WIRELESS_MODE_B;
3072 }
3073
3074 // Initialize RegWirelessMode if it is not a valid one.
3075 if(bInvalidWirelessMode)
3076 {
3077 ieee->mode = (WIRELESS_MODE)InitWirelessMode;
3078 }
3079 }
3080 else
3081 { // One of B, G, A.
3082 InitWirelessMode = ieee->mode;
3083 }
3084//by amy for power save
3085#ifdef ENABLE_IPS
3086// printk("initialize ENABLE_IPS\n");
3087 priv->eRFPowerState = eRfOff;
3088 priv->RfOffReason = 0;
3089 {
3090 // u32 tmp2;
3091 // u32 tmp = jiffies;
3092 MgntActSet_RF_State(dev, eRfOn, 0);
3093 // tmp2 = jiffies;
3094 // printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
3095 }
3096// DrvIFIndicateCurrentPhyStatus(priv);
3097 //
3098 // If inactive power mode is enabled, disable rf while in disconnected state.
3099 // 2007.07.16, by shien chang.
3100 //
3101 if (priv->bInactivePs)
3102 {
3103 // u32 tmp2;
3104 // u32 tmp = jiffies;
3105 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
3106 // tmp2 = jiffies;
3107 // printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
3108
3109 }
3110#endif
3111// IPSEnter(dev);
3112//by amy for power save
3113#ifdef TODO
3114 // Turn off RF if necessary. 2005.08.23, by rcnjko.
3115 // We shall turn off RF after setting CMDR, otherwise,
3116 // RF will be turnned on after we enable MAC Tx/Rx.
3117 if(Adapter->MgntInfo.RegRfOff == TRUE)
3118 {
3119 SetRFPowerState8185(Adapter, RF_OFF);
3120 }
3121 else
3122 {
3123 SetRFPowerState8185(Adapter, RF_ON);
3124 }
3125#endif
3126
3127/* //these is equal with above TODO.
3128 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
3129 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
3130 RF_WriteReg(dev, 0x4, 0x9FF);
3131 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
3132 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
3133 write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
3134 write_nic_byte(dev, CR9346, 0x00);
3135*/
3136
3137 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
3138
3139 //-----------------------------------------------------------------------------
3140
3141 rtl8185b_irq_enable(dev);
3142
3143 netif_start_queue(dev);
3144
3145 }
3146
3147
3148void rtl8185b_rx_enable(struct net_device *dev)
3149{
3150 u8 cmd;
3151 //u32 rxconf;
3152 /* for now we accept data, management & ctl frame*/
3153 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3154#if 0
3155 rxconf=read_nic_dword(dev,RX_CONF);
3156 rxconf = rxconf &~ MAC_FILTER_MASK;
3157 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
3158 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
3159 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
3160 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
3161// rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
3162 if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3163
3164 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3165 dev->flags & IFF_PROMISC){
3166 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3167 }else{
3168 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
3169 if(priv->card_8185 == 0)
3170 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3171 }
3172
3173 /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3174 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3175 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3176 }*/
3177
3178 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3179 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
3180 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
3181 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
3182 }
3183
3184 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3185 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
3186
3187 //if(!priv->card_8185){
3188 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
3189 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
3190 //}
3191
3192 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
3193 rxconf = rxconf &~ MAX_RX_DMA_MASK;
3194 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
3195
3196 //if(!priv->card_8185)
3197 rxconf = rxconf | RCR_ONLYERLPKT;
3198
3199 rxconf = rxconf &~ RCR_CS_MASK;
3200 if(!priv->card_8185)
3201 rxconf |= (priv->rcr_csense<<RCR_CS_SHIFT);
3202// rxconf &=~ 0xfff00000;
3203// rxconf |= 0x90100000;//9014f76f;
3204 write_nic_dword(dev, RX_CONF, rxconf);
3205#endif
3206
3207 if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3208
3209 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3210 dev->flags & IFF_PROMISC){
3211 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
3212 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
3213 }
3214
3215 /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3216 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3217 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3218 }*/
3219
3220 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3221 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
3222 }
3223
3224 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3225 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
3226
3227 write_nic_dword(dev, RCR, priv->ReceiveConfig);
3228
3229 fix_rx_fifo(dev);
3230
3231#ifdef DEBUG_RX
3232 DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
3233#endif
3234 cmd=read_nic_byte(dev,CMD);
3235 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
3236
3237}
3238
3239void rtl8185b_tx_enable(struct net_device *dev)
3240{
3241 u8 cmd;
3242 //u8 tx_agc_ctl;
3243 u8 byte;
3244 //u32 txconf;
3245 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3246
3247#if 0
3248 txconf= read_nic_dword(dev,TX_CONF);
3249 if(priv->card_8185){
3250
3251
3252 byte = read_nic_byte(dev,CW_CONF);
3253 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
3254 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
3255 write_nic_byte(dev, CW_CONF, byte);
3256
3257 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
3258 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
3259 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
3260 tx_agc_ctl |=(1<<TX_AGC_CTL_FEEDBACK_ANT);
3261 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
3262 /*
3263 write_nic_word(dev, 0x5e, 0x01);
3264 force_pci_posting(dev);
3265 mdelay(1);
3266 write_nic_word(dev, 0xfe, 0x10);
3267 force_pci_posting(dev);
3268 mdelay(1);
3269 write_nic_word(dev, 0x5e, 0x00);
3270 force_pci_posting(dev);
3271 mdelay(1);
3272 */
3273 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
3274 }
3275
3276 if(priv->card_8185){
3277
3278 txconf = txconf &~ (1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
3279
3280 }else{
3281
3282 if(hwseqnum)
3283 txconf= txconf &~ (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3284 else
3285 txconf= txconf | (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3286 }
3287
3288 txconf = txconf &~ TX_LOOPBACK_MASK;
3289 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
3290 txconf = txconf &~ TCR_DPRETRY_MASK;
3291 txconf = txconf &~ TCR_RTSRETRY_MASK;
3292 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
3293 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
3294 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
3295
3296 if(priv->card_8185){
3297 if(priv->hw_plcp_len)
3298 txconf = txconf &~ TCR_PLCP_LEN;
3299 else
3300 txconf = txconf | TCR_PLCP_LEN;
3301 }else{
3302 txconf = txconf &~ TCR_SAT;
3303 }
3304 txconf = txconf &~ TCR_MXDMA_MASK;
3305 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
3306 txconf = txconf | TCR_CWMIN;
3307 txconf = txconf | TCR_DISCW;
3308
3309// if(priv->ieee80211->hw_wep)
3310// txconf=txconf &~ (1<<TX_NOICV_SHIFT);
3311// else
3312 txconf=txconf | (1<<TX_NOICV_SHIFT);
3313
3314 write_nic_dword(dev,TX_CONF,txconf);
3315#endif
3316
3317 write_nic_dword(dev, TCR, priv->TransmitConfig);
3318 byte = read_nic_byte(dev, MSR);
3319 byte |= MSR_LINK_ENEDCA;
3320 write_nic_byte(dev, MSR, byte);
3321
3322 fix_tx_fifo(dev);
3323
3324#ifdef DEBUG_TX
3325 DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
3326#endif
3327
3328 cmd=read_nic_byte(dev,CMD);
3329 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
3330
3331 //write_nic_dword(dev,TX_CONF,txconf);
3332
3333
3334/*
3335 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
3336 write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
3337 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3338 */
3339}
3340
3341
3342#endif
kernel source for telekom puls (alcatel/mediatek)